KR20080012084A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

A semiconductor device is provided to increase a memory density while guaranteeing greater effective channel length and charge storage layer than a semiconductor device with a conventional 2-bit storage node by installing charge storage layers in an upper portion and a lower portion of an active layer pattern, respectively. An active layer pattern(120) is separated from a semiconductor substrate(100) by a predetermined distance. A lower gate structure is formed on the lower surface of the active layer pattern wherein at least one first lower insulation layer(500a1) and at least one lower gate electrode(600a) are sequentially stacked in the lower gate structure. At least one second lower insulation layer has a mirror structure of the first lower insulation layer formed between the lower gate electrode and the semiconductor substrate. An upper gate structure is formed on the upper surface of the active layer pattern wherein at least one upper insulation layer(500a2) and at least one upper gate electrode(600b) are sequentially stacked in the upper gate structure. The first lower insulation layer includes an ONO(Oxide Nitride Oxide) layer composed of a first oxide layer, a nitride layer and a second layer that are sequentially stacked on the lower surface of the active layer pattern. A conductive layer for forming a floating gate is formed between the first lower insulation layers.

Description

Semiconductor device and method of manufacturing the same

1 is a cross-sectional view illustrating a NROM SONOS (nitride read only memory silicon-oxide-nitride-oxide-silicon) memory device having a storage node of 2 bits per cell as a technique for increasing the number of storage bits of a memory cell.

2A to 2H are plan views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

3A to 3J are cross-sectional views taken along the line X-X 'of the structure shown in FIGS. 2A to 2J, respectively.

4A to 4C are cross-sectional views each illustrating a semiconductor device manufactured by a method of manufacturing a semiconductor device according to one embodiment of the present invention.

5A through 5C are equivalent circuits of the semiconductor device illustrated in FIGS. 4A through 4B.

6A through 6J are plan views illustrating a method of manufacturing a semiconductor device in accordance with another embodiment of the present invention.

7A to 7J are cross-sectional views taken along the line X-X 'of the structure shown in FIGS. 6A to 6J, respectively.

Explanation of symbols on the main parts of the drawings

100: semiconductor substrate 110: sacrificial layer pattern

120: active layer pattern 200: first mask film pattern

300: device isolation layer 400: second mask layer pattern

500a ₁ : first lower insulating film 500a ₂ : upper insulating film

600a: lower gate electrode 600b: upper gate electrode

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a multi-bit storage node and a method of manufacturing the same.

In recent years, with the trend of miniaturization of semiconductor products, scale reduction of semiconductor devices has been accelerated. In particular, in the case of a semiconductor memory device, in order to secure an appropriate storage capacity, a technique for increasing the memory density by increasing the number of storage bits of the memory cell with an attempt to increase the memory density by reducing the memory cell size has been proposed. Among them, the technique of reducing the cell size of the memory is limited in its application due to the short channel effect that appears as the channel width of the transistor element is reduced.

In contrast, a technique of increasing the number of storage bits of a memory cell has attracted attention as an alternative technique for securing a high storage capacity because of a relatively small demand for scale reduction of the memory cell.

1 is a cross-sectional view showing a NROM SONOS (nitride read only memory silicon-oxide-nitride-oxide-silicon) memory element 5 having a storage node of 2 bits per cell as a technique for increasing the number of storage bits of a memory cell.

Referring to FIG. 1, the NROM SONOS memory element 5 may have a storage node of 2 bits per cell, thereby increasing the number of storage states of the memory cell. The NROM SONOS memory device 5 includes an oxide film 21 serving as a tunneling insulating film between the gate electrode 30 and the semiconductor substrate 10, a nitride film 22 serving as a charge trapping film, and an oxide film serving as a charge blocking film ( 23) an ONO film which is a charge storage layer consisting of 23). The NROM SONOS memory element 5 is expected to be capable of two-bit operation by forward read and reverse read by means of charges that can be stored at different locations.

For example, when a voltage of 9 V and 5 V is applied to the word line WL and the N + bit line 2 BL2 for the programming operation of the NROM SONOS memory device, the charge near the junction of the bit line 2 BL2 is applied. Hot electrons are injected into one portion of the trap layer, bit 2 (b2). Bit 2 (b2) is programmed by the injected hot electrons. For the erase operation of the bit 2 (b2), voltages of −5 V and 5 V may be applied to the gate electrode 30 and the bit line 2 BL2, respectively. At this time, the passion holes induced by the inter-band tunneling occurring near the bit line 2 (BL2) junction may be injected into the bit 2 (b2), and the stored electrons may be erased.

For the read operation of the bit 2 (b2), the bit line 2 (bl2) is in the ground state, by applying a normal voltage to the gate electrode 30 and the bit line 1 (BL1), respectively, to perform the reverse read operation Can be. In a similar manner, programming, erasing and reading operations for bit 1 (b1) can be performed.

 However, as the above-described NROM SONOS memory element 5 is also highly integrated, the channel length of the NROM SONOS memory element 5 is gradually reduced to 100 nm or less, and thus the interval between bit 1 (b1) and bit 2 (b2). This has been reduced, causing a problem of deterioration of device reliability due to overlapping of stored charges. For this reason, there is a need for a semiconductor device having a new structure that is more advantageous for integration than a conventional NROM SONOS memory cell having a 2-bit storage node per cell, and a manufacturing method thereof.

Accordingly, the technical problem to be achieved by the present invention is to increase the memory density while providing a larger effective channel length and a charge storage layer length than a semiconductor device having a conventional 2-bit storage node, and even with the same structure, Accordingly, a multifunction can be performed as a switching element or as a memory element to provide a semiconductor device having excellent process matching.

In addition, another technical problem to be achieved by the present invention is to increase the memory density while providing a larger effective channel length and charge storage layer length than the conventional two-bit storage node, even in the same structure as the switching element according to the operating voltage Another object of the present invention is to provide a method of manufacturing a semiconductor device having excellent process matching, which can perform multifunction as a memory device.

A semiconductor device according to the present invention for achieving the above technical problem, the semiconductor substrate; An active layer pattern spaced apart from the semiconductor substrate by a predetermined distance; A lower gate structure including at least one first lower insulating layer and a lower gate electrode sequentially stacked on the bottom surface of the active layer pattern; At least one second lower insulating film having a mirror structure for the first lower insulating film formed between the lower gate electrode and the semiconductor substrate; And an upper gate structure including at least one upper insulating layer and at least one upper gate electrode sequentially stacked on an upper surface of the active layer pattern.

In the semiconductor device of the present invention, the first lower insulating film may include an ONO film including a first oxide film, a nitride film, and a second oxide film sequentially stacked on the bottom surface of the active layer pattern. In addition, the upper insulating film may be applied as a semiconductor memory device having a 4-bit storage node by including an ONO film including a first oxide film, a nitride film, and a second oxide film sequentially stacked on the upper surface of the active layer pattern. In addition, the semiconductor device of the present invention has a semiconductor device in which the first lower insulating film and the upper insulating film have the same thickness so that the upper gate and the lower gate can be driven at the same operating voltage during the actual programming / erase / read operation. Can provide.

In accordance with an aspect of the present invention for achieving the above technical problem, a method of manufacturing a semiconductor device laminates a sacrificial layer and an active layer sequentially on a semiconductor substrate. Thereafter, a first mask layer pattern is formed on the active layer, and the active layer and the sacrificial layer are continuously etched using the first mask layer pattern as an etching mask, thereby forming a sacrificial layer pattern stacked on the semiconductor substrate. And a trench defining an active layer pattern. Next, after forming the device isolation layer filling the trench, a second mask layer pattern is formed on the device isolation layer to form a recess region exposing at least a portion of the sacrificial layer pattern. The recess region is formed in the device isolation layer using the second mask layer pattern as an etching mask, and the sacrificial layer pattern exposed by the recess region is removed.

The lower gate structure is formed by sequentially stacking at least one lower insulating film and a lower gate conductive film on the bottom surface of the active layer pattern by using a space generated by removing the sacrificial layer pattern. Subsequently, the first mask layer pattern is removed, and at least one upper insulating layer and the upper gate conductive layer are sequentially stacked on the exposed active layer pattern to complete the upper gate structure.

In addition, according to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a sacrificial layer, an active layer, and at least one upper insulating film are sequentially formed on a semiconductor substrate. 1 A mask film pattern is formed. Next, the upper insulating layer, the active layer, and the sacrificial layer are sequentially etched using the first mask layer pattern as an etching mask to define the sacrificial layer pattern, the active layer pattern, and the upper insulating layer pattern stacked on the semiconductor substrate. After the trench is formed, an isolation layer for filling the trench is formed.

A second mask layer pattern is formed on the device isolation layer to form a recess region for exposing at least a portion of the sacrificial layer pattern, and the recess is formed in the device isolation layer using the second mask layer pattern as an etching mask. After forming the region, the sacrificial layer pattern exposed by the recess region is removed. Thereafter, at least one lower insulating layer and the lower gate conductive layer are sequentially stacked on the bottom surface of the active layer pattern to form a lower gate structure, and the first mask layer pattern is removed to expose the upper insulating layer pattern. Next, the upper gate conductive layer is sequentially stacked on the exposed upper insulating layer pattern to complete the upper gate structure.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The embodiments of the present invention are provided to more fully explain the present invention to those skilled in the art, and the following examples can be modified in various other forms, and the scope of the present invention is It is not limited to an Example. In addition, the thickness or size of each layer in the drawings is exaggerated for convenience and clarity, the same reference numerals in the drawings refer to the same elements.

2A to 2H are plan views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention. 3A to 3J are cross-sectional views taken along the line X-X 'of the structure shown in FIGS. 2A to 2J, respectively.

2A and 3A, the sacrificial layer 110L and the active layer 120L are sequentially stacked on the semiconductor substrate 100. The sacrificial layer 110L is formed of a material having an etch selectivity with respect to the semiconductor substrate 100 and the active layer 110L. In order to form the active layer 110L as a single crystal semiconductor layer, the sacrificial layer 110L and the active layer 120L may be formed by heteroepitaxial growth.

For example, on the silicon semiconductor substrate 100, a sacrificial layer 110L made of silicon germanium (SiGe) or silicon germanium carbide (SiGeC) having an etch selectivity with respect to silicon is formed by epitaxial growth. can do. Thereafter, the active layer 120L made of, for example, silicon single crystal may be formed on the sacrificial layer 110L by the epitaxial growth method.

In this case, since the sacrificial layer 110L must have a sufficient space to form a lower gate structure, which will be described later, the sacrificial layer 110L may be formed to have a thickness of 500 kPa to 2000 kPa. The active layer 120L may be formed to have a thickness of 100 kPa to 2000 kPa depending on a driving method of the semiconductor device to be manufactured, for example, fully depleted or partial depleted.

The active layer 120L may contain impurities as necessary. For this purpose, a dopant is in-situ using a mixed gas containing impurities in the epitaxial growth process or a separate ion implantation process after the active layer is formed. You can also do

2B and 3B, a first mask layer is stacked on the active layer 120L and patterned to form a line type first mask layer pattern 200. The first mask layer pattern 200 may be formed of a material having an etch selectivity with respect to the active layer 120L, the sacrificial layer 110L, and the semiconductor substrate 100. For example, the first mask layer pattern 200 may be formed of silicon nitride. In this case, a pad film (not shown) may be further formed to protect the active layer 120L before the first mask film is laminated. By sequentially etching the active layer 120L and the sacrificial layer 110L by using the first mask layer pattern 200 as an etching mask, the line type sacrificial layer pattern 110 and the active layer stacked on the semiconductor substrate 100 are etched. A trench T defining the pattern 120 is formed.

2C and 3C, an isolation layer 300 may be formed to fill the trench T between the stacked line type sacrificial layer pattern 110 and the active layer patterns 120. For example, a silicon oxide layer is laminated on the entire surface of the semiconductor substrate 100 in which the trench T is formed, for example, the trench T by the chemical vapor deposition method, and the first mask layer pattern ( By planarization by an etch back or chemical mechanical polishing process until the surface of the substrate 200 is exposed, the device isolation layer 300 filling the trench T may be formed.

2D and 3D, a second mask layer pattern 400 is formed on the device isolation layer 300 to form a recess region (R of FIG. 2E) that exposes at least a portion of the sacrificial layer pattern 110. do. For example, the second mask layer pattern 400 may have a line type that intersects the line type first mask layer pattern 200.

In this case, the width W ₁ and the interval W _{2 of} the second mask layer pattern 400 facilitate the penetration of the etching solution in the removal process of the sacrificial layer pattern 110, and the active layer pattern 120 and the first layer may be formed. 1 is determined so as to provide the strength for mechanically supporting the mask film pattern 200. The second mask layer pattern 400 may be made of photoresist.

2E and 3E, a portion of the device isolation layer exposed between the line type second mask layer patterns 400 is removed to form a recess region R. Referring to FIGS. In this case, the recess region R of the device isolation layer 300a may be formed by a plasma etching process having an anisotropic etching characteristic. Next, the second mask film pattern 400 is removed.

2F and 3F, the sacrificial layer pattern 110 exposed by the recess region R is removed. For example, the sacrificial layer pattern 110 may be selectively removed by an etching solution that may penetrate through the space formed by the recess region R of the device isolation layer 300a.

As a result, the active layer pattern 120 and the first mask layer pattern 200 are spaced apart from the semiconductor substrate 100 by the thickness of the sacrificial layer pattern 110. The active layer pattern 120 and the first mask layer pattern 200 spaced apart from the semiconductor substrate 100 may be supported by contacting an unrecessed portion of the device isolation layer 300a.

2G and 3G, at least one first lower insulating film 500a ₁ is sequentially formed on the bottom surface of the active layer pattern 120. For example, in order to form a lower charge storage layer providing a 2-bit storage node, the first oxide film 501, the nitride film 502, and the second oxide film 503 are sequentially formed as the first lower insulating film 500a ₁ . The made ONO film can be formed.

In this case, the first oxide film 501 may be formed by a thermal oxidation process, the nitride film 502 may be formed by a chemical vapor deposition method, and the second oxide film 503 may be formed by a chemical vapor deposition method. The first oxide film 501s, the nitride film 502s, and the second having the same material and the same thickness are sequentially on the surface of the semiconductor substrate 100 exposed to the process for forming the first lower insulating film 500a ₁ . A second lower insulating film 500s may be formed on which the oxide film 503s is stacked.

The first lower insulating film 500a1 is not limited to the ONO film, and instead of the nitride film 502, a polysilicon film (not shown) that is a conductive film is stacked to form a lower charge storage layer including a floating gate. It may be formed. In addition, a control insulating layer (not shown) may be further included between the lower charge storage layer and the lower gate electrode 600a to control coupling of the lower charge storage layer. Further, only the lower gate insulating film (see 500c ₁ of FIG. 4C) may be formed as the first lower insulating film 500a ₁ .

Thereafter, a lower gate conductive layer made of a conductive material such as polysilicon or a metal may be stacked on the first lower insulating layer 500a ₁ . After the lower gate conductive layer is stacked, the first lower portion exposed to the recess region R is formed by using the device isolation layer 300a including the first mask layer pattern 200 and the recess region R as an etching mask. The insulating film 500a ₁ and the lower gate conductive film are etched. As a result, the lower gate electrode 600a may be formed between the cells of the semiconductor device.

Alternatively, the lower common gate electrode may be formed in the cells of the semiconductor device by not etching the lower gate conductive layer according to the driving method of the semiconductor device. In this case, however, the lower gate conductive layer should not be in contact with the active layer pattern 120 to electrically separate the active layer pattern 120 from the lower gate electrode 600a.

As described above, according to the method of manufacturing a semiconductor device according to one embodiment of the present invention, in a typical ONO film, the first oxide film 501, the nitride film 502, and the second oxide film 503 are about 30 kV, 100 kV and 60 kV, respectively. When considering the height of the empty space formed by the removed sacrificial layer pattern 120 is 500 kPa to 2000 kPa, the charge storage layer such as the ONO film and the floating gate and the lower gate electrode on the bottom surface of the active layer pattern 120 The process margin for forming the 600a can be sufficiently secured.

Further, in the process of forming the first lower insulating film 500a ₁ , the first lower insulating film 500a ₁ may be formed of substantially the same material and substantially the same thickness as the insulating films 501, 502, and 503 stacked on the bottom surface of the active layer pattern 120. The lower gate electrode 600a may be insulated from the semiconductor substrate 100 by the second lower insulating layer 500s having the mirror structure, that is, the insulating layers 501s, 502s, and 503s. As described above, according to the present invention, the semiconductor substrate 100 and the lower gate electrode 600a may be electrically insulated without performing a separate insulation process for the lower gate electrode 600a.

In addition, when the upper insulating film (see 500a ₂ of FIG. 4A) is formed to have the same thickness as the first lower insulating film 500a ₁ , in the completed semiconductor device, for example, an upper gate and The bottom gate can be operated with the same operating voltage.

2H and 3H, the recess region R of the isolation layer 300a is filled with an insulating material. For example, an insulating material layer having excellent gap fill characteristics may be formed on the entire surface of the semiconductor substrate 100 by chemical vapor deposition, and the surfaces of the first mask layer pattern 200 and the device isolation layer 300a may be exposed. By planarization by an etch back or chemical mechanical polishing process, the recess region R of the isolation layer 300a may be filled with an insulating material. The insulating material may be the same material as that of the device isolation layer 300, for example, silicon oxide.

2I and 3I, the first mask layer pattern 200 may be selectively removed through dry etching or wet etching. For example, when the first mask layer pattern 200 is formed of a silicon nitride layer, the first mask layer pattern 200 may be removed by reactive dry etching using CF ₄ gas or by wet etching using phosphoric acid. In this case, when the device isolation layer 300 is recessed at least lower than the upper surface of the active layer pattern 120 to expose the side surface of the active layer pattern 120, the fin type active layer pattern 120 may be formed.

2J and 3J, at least one upper insulating film 500a ₂ is sequentially formed on the exposed top surface of the active layer pattern 120. For example, in order to form an upper charge storage layer providing a 2-bit storage node, an ONO film made of a first oxide film 504L, a nitride film 505L, and a second oxide film 506L is sequentially stacked and patterned to form an upper layer. An insulating film (see 500a2 in FIG. 4A) can be formed. The first oxide film 504L may be formed by, for example, a thermal oxidation process, the nitride film 505L may be formed by chemical vapor deposition, and the second oxide film 506L may be formed by chemical vapor deposition.

The upper insulating film 500a ₂ is not limited to the ONO film, and instead of the nitride film 505L, a polysilicon film as a conductive film may be stacked to form an upper charge storage layer including a floating gate. Further, a control insulating layer (not shown) for controlling the coupling of the upper charge storage layer may be further included between the upper charge storage layer and the upper gate electrode (see 600b of FIG. 4A). Further, only the gate insulating film (see 500b _{2 in} FIG. 4B) may be formed as the upper insulating film 500a ₂ .

Thereafter, a semiconductor device having various structures shown in FIGS. 4A to 5C is completed by a conventional transistor forming process. Subsequent processes for completing the semiconductor device will be described later with reference to FIGS. 4A to 5C.

According to the method for manufacturing a semiconductor device according to the embodiment of the present invention described above, both the upper insulating film 500a ₂ and the first lower insulating film 500a ₁ are formed of an ONO film or, optionally, the ONO film only for one of the insulating films. It can be formed as. In addition, a charge storage layer may be formed using a conductive film such as polysilicon instead of the nitride film of the ONO film. Note that only the gate insulating film (see FIGS. 4B and 4C) may be formed as the upper insulating film 500a ₂ and the first lower insulating film 500a ₁ , instead of the charge storage layer made of a multilayer film.

As described above, according to the method of manufacturing the semiconductor device according to the embodiment of the present invention, the first lower insulating film 500a ₁ capable of performing various functions may be formed by adjusting the thickness of the diluted layer pattern 110. At the same time, a process margin capable of forming the lower gate electrode 600a may be secured.

Hereinafter, a subsequent process according to an embodiment of the present invention will be described in detail with reference to FIGS. 4A to 5B.

4A to 4C are cross-sectional views illustrating semiconductor devices manufactured by a method of manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 5A to 5C are equivalent circuits of the semiconductor devices shown in FIGS. 4A to 4B. to be.

4A and 5A, an upper gate conductive layer, for example, a polysilicon layer, is deposited and patterned on the second oxide layer 506L illustrated in FIGS. 2J and 3J to form an upper gate electrode 600b. After depositing an insulating layer, for example, a silicon nitride layer, on the entire surface of the resultant on which the upper gate electrode 600b is formed, the insulating layer may be etched back to form a spacer 601 on the sidewall of the upper gate electrode 600b. At this time, the stacked ONO films 504L, 505L, and 506L are simultaneously etched to form a self-aligned upper charge storage layer.

Next, the impurity ions are implanted into the active layer pattern 120 using the upper gate electrode 600b and the spacer 601 as an ion implantation mask, thereby forming a high concentration source region S and a drain region D. Can be. Thereafter, the interlayer insulating film 700 is formed, the contact plug VC is formed by a normal via plug forming process, and the bit lines BL ₁ and BL ₂ are connected to the source S and the drain D. The word line WL ₁ and WL ₂ wiring processes for the upper gate electrode 600b and the lower gate electrode 600a are performed.

The semiconductor device according to the present embodiment may be used as a flash memory having a charge storage layer on both top and bottom thereof. In particular, when the first lower insulating film 500a1 is an ONO film, the first lower insulating film 500a1 may be used as a flash memory having a 4-bit storage node. In addition, the thicknesses of the upper insulating film 500a ₂ and the first lower insulating film 500a ₁ , for example, the thicknesses of the tunneling insulating film, the charge trapping film, and the charge blocking film are equally formed to have a symmetrical structure. The gate and the bottom gate can be driven with the same operating voltage during the actual program / erase / read operation.

4B and 5B, as described above with reference to FIGS. 2J and 3J, an ONO film is formed as the first lower insulating film 500b ₁ , and only a gate insulating film is formed as the upper insulating film 500b ₂ , thereby forming two bits. It is possible to provide a flash memory device having a storage node. In the semiconductor device according to the present exemplary embodiment, the active layer pattern 120 is separated from the semiconductor substrate 100 by the first lower insulating film 500b ₁ , thereby providing an upper transistor having a floating body channel suitable for low voltage and high speed operation devices. Can be.

Similarly, although not shown, as described above with reference to FIG. 2G, by forming only the gate insulating film (see 500c ₁ of FIG. 4C) as the first lower insulating film 500b ₁ , and forming the ONO film as the upper insulating film 500a ₂ , It is also possible to provide a semiconductor memory device having a two bit storage node.

4C and 5C, as described above with reference to FIGS. 2J and 2G, a transistor having a lower gate insulating film and an upper gate insulating film as the first lower insulating film 500c ₁ ) and the upper insulating film 500a ₂ , respectively. May be provided. In addition, the semiconductor device according to the present embodiment may not only provide an upper transistor having a floating body channel suitable for low voltage and high speed operation devices in which the active layer pattern 120 is separated from the semiconductor substrate 100, but also increase the thickness of the active layer. It can be adjusted to provide a fully depeleted or partially depeleted transistor.

As described above, by forming only the lower gate insulating film and the upper gate insulating film as the first lower insulating film and the upper insulating film, respectively, a transistor suitable for low voltage and high speed operation devices in which the floating body channel control capability is improved by controlling the voltage applied to the lower gate independently. Can be provided. In addition, the semiconductor device according to the present exemplary embodiment may be used as a semiconductor memory device such as a 1T DRAM by storing charge such as holes in the floating body channel by the lower gate electrode 600a.

In the semiconductor device according to the embodiments of the present invention illustrated in FIGS. 4A to 5C, a process of forming a lower gate structure including a first lower insulating layer 500a ₁ , 500b ₁ , 500c ₂ and a lower gate electrode 600a is provided. Insulating films 501s, 502s, and 503s having a mirror structure formed of substantially the same material and having substantially the same thickness as the insulating films 501, 502, and 503 stacked on the bottom surface of the active layer pattern 120 in FIG. The lower gate electrode 600a may be insulated from the semiconductor substrate 100 by the second lower insulating layer 500s. Accordingly, according to the present invention, the semiconductor substrate 100 and the lower gate electrode 600a may be electrically insulated without performing a separate insulating process to form an independent lower gate electrode between cells of the semiconductor device.

In addition, when a transistor for performing various functions in one semiconductor chip is required, a semiconductor device having any one of the semiconductor devices according to the present invention may be used. This is because the semiconductor element described above provides an upper gate electrode and a lower gate electrode capable of independently controlling the floating body channel, and thus can function as a normal switching element or as a memory element depending on the operating voltage, even if they have the same structure. Due to the point.

As a result, for example, semiconductor devices that perform different functions required in a memory area and a logic area can be simultaneously formed by the same process. As a result, since the semiconductor devices of the memory region and the logic region can be manufactured simultaneously in one process, an economical manufacturing method can be provided in terms of integration of the process. Alternatively, it is apparent that even one semiconductor chip may be formed to have a different structure for each region as a switching element or a memory element, as necessary.

4A to 4C of the semiconductor device according to some embodiments of the inventive concept, it is illustrated that one upper gate electrode 600b is formed on the active layer pattern 120, but two or more upper portions are formed on the active layer pattern 120. The cell density may be increased by forming a gate electrode 600b and manufacturing a semiconductor device having a structure in which two transistors commonly use either the source S or the drain D.

In the semiconductor device shown in FIGS. 4B to 4C, a CMOS transistor may be configured by forming an nMOS transistor on the left side and a pMOS transistor on the right side. In this case, the nMOS transistor and the lower gate electrode of the pMOS transistor may be configured. It is apparent that can be doped with impurities of different conductivity types.

6A through 6J are plan views illustrating a method of manufacturing a semiconductor device in accordance with another embodiment of the present invention. 7A-7J are cross-sectional views taken along the line XX 'for the structure shown in FIGS. 6A-6J, respectively. Unlike the embodiments described with reference to FIGS. 2A to 2J and FIGS. 3A to 3J, the present embodiment is a method for manufacturing an upper insulating film 500a ₂ first and then a first lower insulating film 500a ₁ . It is about. The descriptions of the components shown in FIGS. 2A to 4C may also be applied as reference to components having the same reference numerals in this embodiment.

6A and 7A, as described above with reference to FIGS. 2A and 3A, the sacrificial layer 110L and the active layer 120L are sequentially stacked on the semiconductor substrate 100. The sacrificial layer 110L may be formed to a thickness of 500 kPa to 2000 kPa. The active layer 110L may be formed to a thickness of 10 nm to 200 nm according to the structure of the semiconductor device (FIGS. 4A to 5C) to be manufactured. The active layer 110L may contain impurities as necessary.

6B and 7B, at least one upper insulating film 500a ₂ L is formed on the top surface of the active layer 110. For example, the 2-bit storage in order to form a top of the charge storage layer to provide a node, as sequential as the upper insulation film (500a ₂ L) consisting of a first oxide film (504L), a nitride film (505L) and the second oxide film (506L) An ONO film can be formed.

Then, it is possible to laminate the upper insulating film (not shown), a top gate conductive film made of a conductive material such as polysilicon or metal in the (500a ₂ L). However, the upper gate conductive layer may be stacked in a process of forming the upper gate structure after the removing of the first mask layer pattern 200 described later with reference to FIGS. 6J and 7J. Upper insulating film (500a ₂ L) is not limited to an ONO film, and to form the top of the charge storage layer comprising a floating gate and a nitride film (505L) instead of the conductive film of a polysilicon laminated film, the upper insulating film (500a ₂ It is as described above that only the gate insulating film (see 500b2 in Fig. 4B) may be formed as

6C and 7C, a first mask layer is stacked on the upper insulating layer 500a ₂ L and patterned to form a line type first mask layer pattern 200. Thereafter, by using the first mask layer pattern 200 as an etching mask, the upper insulating layer 500a ₂ L, the active layer 120L, and the sacrificial layer 110L are continuously etched to form a line type on the semiconductor substrate 100. A trench T defining the sacrificial layer pattern 110, the active layer pattern 120, and the upper insulating layer 500a ₂ is formed.

6D and 7D, the device isolation layer 300 filling the trench T is formed. By forming an insulating material layer filling the trench T by a chemical vapor deposition method on the entire surface of the semiconductor substrate, and planarization by an etch back or chemical mechanical polishing process until the surface of the first mask film pattern 200 is exposed, An isolation layer 300 may be formed to fill the trench T.

6E and 7E, in order to form a recess region R for exposing at least a portion of the sacrificial layer pattern 110 in the device isolation layer 300, the first mask layer pattern 200 having a line type is formed. A second mask film pattern 400 of a line type intersecting with is formed. In this case, the width W ₁ and the interval W _{2 of} the second mask layer pattern 400 may prevent penetration of the etching solution in the process of removing the sacrificial layer pattern 200, as described above with reference to FIGS. 2D and 3D. It is determined to facilitate, and to provide strength for mechanically supporting the stacked active layer pattern 120, the upper insulating film 500a ₂ , and the first mask film pattern 200.

6F and 7F, a portion of the isolation layer 300 exposed between the second mask layer patterns 400 is removed by a plasma etching process to form a recess region R. Referring to FIGS. Next, the second mask film pattern 400 is removed.

6G and 7G, the sacrificial layer pattern 110 existing between the semiconductor substrate 100 and the active layer pattern 120 by an etching solution that may penetrate through the space formed by the recess region R. Referring to FIGS. ). As a result, the active layer pattern 120 may be spaced apart from the semiconductor substrate 100 by the thickness of the sacrificial layer pattern 110 together with the active layer pattern 200 and the upper insulating layer 500a2 on the active layer pattern 120. .

6H and 7H, on the bottom of the active layer pattern 120, sequentially forming at least one or more first lower insulating layers 500a ₁ , for example, a lower charge storage layer providing a two bit storage node. For this purpose, an ONO film composed of the first oxide film 501, the nitride film 502, and the second oxide film 503 is formed. In this case, the first oxide film 501s, the nitride film 502s, and the second oxide film 503s are sequentially stacked on the surface of the semiconductor substrate 100 exposed to the process for forming the first lower insulating film 500a ₁ . The second insulating film 500s may be formed.

Thereafter, a lower gate conductive layer made of a conductive material such as polysilicon or a metal may be stacked on the first lower insulating layer 500a ₁ . After the lower gate conductive layer is stacked, the lower charge storage exposed to the recess region R is formed by using the device isolation layer 300a including the first mask layer pattern 200 and the recess region R as an etching mask. By etching the layer 500a1 and the lower gate conductive layer, the lower gate electrode 600a may be formed between the semiconductor devices. Alternatively, the lower common gate electrode may be formed in the semiconductor device cells without etching the stacked lower gate conductive layer according to the driving method of the semiconductor device.

6I and 7I, the recess region R of the device isolation layer 300a is buried using an insulating material having excellent gap fill characteristics.

6J and 7J, the first mask layer pattern 200 may be selectively removed through dry etching or wet etching. Thereafter, as described above with reference to FIGS. 4A to 5C, a semiconductor device or a semiconductor memory device having various structures according to the present invention may be completed by a conventional transistor forming process.

Although embodiments of the present invention have been described with respect to the active layer having a flat structure, the present invention is not limited thereto, and the active layer is grown by a process of exposing sidewalls of the active layer pattern as described above with reference to FIGS. 2I and 3I. It will be apparent to those skilled in the art that a semiconductor device or semiconductor memory device having an extended effective channel region can be provided later by performing a suitable patterning process to form a fin type active layer. In addition, it is apparent that the semiconductor memory device may include a semiconductor memory device having a multi-level bit storage node by using a nano crystal as an upper or lower charge storage layer. Further, a plurality of upper gate electrodes arranged in rows is formed on the active layer pattern of the line pattern, and the active layers of the line pattern are arranged in columns, and then electrically connected to the upper gate electrodes of the semiconductor elements arranged in the rows. A plurality of upper word lines, a plurality of lower word lines electrically connected to the lower gate electrodes of the semiconductor elements arranged in the rows, and a plurality of electrically connected to the source / drain regions of the semiconductor elements arranged in the columns, respectively. It is apparent that an array of semiconductor devices including bit lines may be configured.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and alterations are possible within the scope without departing from the technical spirit of the present invention, which are common in the art. It will be clear to those who have knowledge.

The semiconductor device of the present invention has a charge storage layer on the upper and lower portions of the active layer pattern, respectively, and increases the memory density while ensuring a larger effective channel length and charge storage layer length than a semiconductor device having a conventional 2-bit storage node. Since the upper gate electrode and the lower gate electrode which can independently control the floating body channel can be provided, even if the same structure, it can function as a normal switching element or a memory element depending on the operating voltage, so that process consistency An excellent semiconductor element can be provided.

In addition, the manufacturing method of the semiconductor device of the present invention, it is possible to easily secure the process margin for forming the lower charge storage layer and the lower gate electrode by using the sacrificial layer pattern, the semiconductor device to the lower gate electrode without additional process Provided are a method of manufacturing a semiconductor device capable of forming an upper gate electrode and a lower gate electrode that are insulated from a substrate to independently control a floating body channel.

Claims (27)

Semiconductor substrates; An active layer pattern spaced apart from the semiconductor substrate by a predetermined distance; A lower gate structure including at least one first lower insulating layer and a lower gate electrode sequentially stacked on the bottom surface of the active layer pattern; At least one second lower insulating film having a mirror structure for the first lower insulating film formed between the lower gate electrode and the semiconductor substrate; And And an upper gate structure including at least one upper insulating layer and at least one upper gate electrode sequentially stacked on an upper surface of the active layer pattern. The method of claim 1, The thickness of the active layer pattern is a semiconductor device 100 ~ 2000 GPa. The method of claim 1, The first lower insulating layer may include an ONO film including a first oxide film, a nitride film, and a second oxide film sequentially stacked on a bottom surface of the active layer pattern. The method of claim 1, The upper insulating film includes an ONO film including a first oxide film, a nitride film, and a second oxide film sequentially stacked on an upper surface of the active layer pattern. The method of claim 1, And a conductive layer for forming a floating gate between the first lower insulating layers. The method of claim 1, The semiconductor device further comprises a conductive film for forming a floating gate between the upper insulating film. The method of claim 1, And the first lower insulating film and the upper insulating film have the same thickness. The method of claim 1, At least two upper gate electrodes are disposed on the active layer pattern, and the semiconductor device uses one of a source and a drain in common. The method of claim 1, A semiconductor device for determining a conductivity type of the lower gate electrode to provide an nMOS or pMOS transistor. The method of claim 1, And the upper gate electrode and / or the lower gate electrode is made of a metal. Stacking the sacrificial layer and the active layer sequentially on the semiconductor substrate; Forming a first mask layer pattern on the active layer; Continuously etching the active layer and the sacrificial layer using the first mask layer pattern as an etching mask to form a trench defining a sacrificial layer pattern and an active layer pattern stacked on the semiconductor substrate; Forming an isolation layer filling the trench; Forming a second mask layer pattern on the device isolation layer to form a recess region exposing at least a portion of the first sacrificial layer pattern; Forming the recess region in the device isolation layer using the second mask layer pattern as an etching mask; Removing the sacrificial layer pattern exposed by the recess region; Stacking at least one lower insulating layer and a lower gate conductive layer on the bottom surface of the active layer pattern in order to form a lower gate structure; Removing the first mask layer pattern to expose the active layer pattern; And Stacking at least one upper insulating film and an upper gate conductive film sequentially on the active layer pattern to form an upper gate structure. Sequentially forming a sacrificial layer, an active layer and at least one upper insulating film on the semiconductor substrate; Forming a first mask layer pattern on the upper insulating layer; A trench defining the sacrificial layer pattern, the active layer pattern, and the upper insulating film pattern stacked on the semiconductor substrate by successively etching the upper insulating film, the active layer, and the sacrificial layer using the first mask film pattern as an etching mask. Forming; Forming an isolation layer filling the trench; Forming a second mask layer pattern on the device isolation layer to form a recess region exposing at least a portion of the sacrificial layer pattern; Forming the recess region in the device isolation layer using the second mask layer pattern as an etching mask; Removing the sacrificial layer pattern exposed by the recess region; Stacking at least one lower insulating layer and a lower gate conductive layer on the bottom surface of the active layer pattern in order to form a lower gate structure; Removing the first mask layer pattern to expose the upper insulating layer; And Forming an upper gate structure by sequentially laminating an upper gate conductive layer on the upper insulating layer pattern. The method according to claim 11 or 12, Wherein the sacrificial layer is formed with respect to the semiconductor substrate, and the active layer is formed with a hetero epitaxial growth method with respect to the sacrificial layer, respectively. The method of claim 13, And the semiconductor substrate is a silicon single crystal, the sacrificial layer is silicon germanium or silicon germanium carbide, and the active layer is silicon. The method according to claim 11 or 12, The sacrificial layer has a thickness of 500 kPa to 2000 kPa. The method according to claim 11 or 12, The thickness of the active layer is a method of manufacturing a semiconductor device formed to a thickness of 100 kPa to 2000 kPa. The method according to claim 11 or 12, The first mask layer pattern is a line type, And the second mask layer pattern intersects the first mask layer pattern at a predetermined width and interval. The method of claim 17, The recessed area may be formed by removing a portion of the isolation layer exposed between the second mask layer patterns. The method according to claim 11 or 12, The removing of the sacrificial layer pattern is performed by an etching solution penetrating a space formed by the recess region. The method according to claim 11 or 12, In the forming of the lower gate structure, And etching the first lower insulating layer and the lower gate conductive layer exposed to the recess region using an isolation layer including the first mask layer pattern and the recess region as an etching mask. The method according to claim 11 or 12, After forming the lower gate structure, And filling the recess region of the device isolation layer with an insulating material. The method according to claim 11 or 12, And the lower insulating film is an ONO film made of a first oxide film, a nitride film, and a second oxide film sequentially stacked on the bottom surface of the active layer pattern. The method according to claim 11 or 12, And a conductive film for forming a floating gate between the lower insulating films. The method according to claim 11 or 12, And the upper insulating film is an ONO film made of a first oxide film, a nitride film, and a second oxide film sequentially stacked on a bottom surface of the active layer pattern. The method according to claim 11 or 12, And a conductive film for forming a floating gate between the upper insulating films. The method according to claim 11 or 12, The upper gate conductive film and / or the lower gate conductive film are made of a metal. The method of claim 11, And exposing the active layer pattern, and recessing at least a portion of the device isolation layer surrounding the sidewalls of the active layer pattern to form a fin type active layer pattern.

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