KR20080003049A - Column control circuit for data input/output section control - Google Patents

Abstract

A column control circuit for controlling a data input/output section is provided to assure margin to reduce the width of an external clock in high speed and to assure stability in normal speed, by controlling pulse width of a column pulse according to the speed of a memory device. According to a column control circuit controlling input/output of memory cell data, a latch part(400) generates a column pulse by using a set signal and a reset signal. The column pulse is a column address selection signal. A set signal generation part(100) generates the set signal determining enable time of the column pulse by using an internal command input pulse generated from an external command. A reset part(300) generates the reset signal determining disable time of the column pulse by delaying the column pulse according to a signal of controlling operation speed of a memory device.

Description

COLUMN CONTROL CIRCUIT FOR DATA INPUT / OUTPUT SECTION CONTROL}

1 is a circuit diagram of a column control circuit according to the prior art.

2 is a waveform diagram for explaining the operation of FIG.

3 is a circuit diagram illustrating the delay unit 20 of FIG. 1.

4 is a circuit diagram of a column control circuit according to an embodiment of the present invention.

5 is a circuit diagram illustrating an example of the delay unit 200 of FIG. 4.

6 is a circuit diagram illustrating another example of the delay unit 200 of FIG. 4.

FIG. 7 is a waveform diagram illustrating the operation of FIG. 4. FIG.

The present invention relates to a semiconductor memory device, and more particularly, to a column control circuit for controlling input and output of cell data.

In general, a DRAM is a volatile memory device that stores data in a cell including one transistor and one capacitor. The DRAM turns on a cell transistor by activating a word line by accessing a row address during a read or write operation. At this time, the data stored in the cell capacitor or the data input from the outside is transferred to the bit line pair and then amplified by the bit line sense amplifier so that the bit line pair is developed into the internal voltage VCORE and the ground voltage VSS, respectively. Thereafter, the DRAM accesses the column address to perform a read or write operation through the corresponding bit line.

In the conventional circuit for controlling the column address during such a read or write operation, as shown in FIG. 1, a set signal generator for generating a set signal SB using an internal read / write input pulse RWP generated from an external command ( 10), a delay unit 20 for delaying the signal PYP latched by the set signal SB via the latch unit 40 and outputting the delayed signal RWPDLY, and a reset signal generator for generating the reset signal RB using the delay signal RWPDLY ( 30), a latch unit 40 for generating the latch signal PYP using the set signal SB and the reset signal RB, and an output unit 50 for receiving the latch signal PYP and outputting the column pulse YP which is a column address selection signal. Can be.

Referring to FIG. 2, an operation of a conventional column control circuit having such a configuration is described. When an internal read / write input pulse RWP is generated by an external clock EXT_CLK and an external command, a set signal SB, which is a low pulse, is generated and the latch unit ( The latch signal PYP that is the output of 40) becomes high level. After the latch signal PYP is delayed through the delay unit 20, the reset signal generation unit 30 generates a reset signal RB, which is a low pulse, so that the latch signal PYP, which is the output of the latch unit 40, becomes low. . The latch signal PYP is output as the column pulse YP through the output unit 50.

Meanwhile, in the conventional column control circuit, the delay unit 20 for determining the pulse width of the column pulse YP may be configured as shown in FIG. 3, and the operation of the delay unit 20 having such a configuration will be described below.

That is, as shown in FIG. 3, when the latch signal PYP changes from a low level to a high level, the NMOS transistor N1 is turned on to transmit a signal of a ground voltage level, and the signal of the ground voltage level is a PMOS transistor ( After the delay of the resistor R1 connected to the drain terminal of P1 and the RC component of the MOS capacitors C1 to C4, the delay signal RDPDLY is outputted through the inverter INV1.

As described above, the delay signal RWPDLY output from the delay unit 20 determines the generation time of the reset signal RB that determines the disable timing of the column pulse YP, and the column pulse YP determines the interval for inputting and outputting data into the memory cell. do. If the column pulse YP has a wide pulse width, the stability of the operation is secured, but it is a limitation of the high speed operation.

That is, in the delay unit 20 having the configuration as shown in FIG. 3, the RC delays of the resistors R1 and the MOS capacitors C1 to C4 are determined, so that the operation speed of the semiconductor memory device is determined by the delay unit 20. There is a problem that can be limited due to the pulse width of the column pulse YP.

Accordingly, an object of the present invention is to adjust the pulse width of the column pulse YP in accordance with the speed of the memory device, thereby ensuring the stability of the operation in the case of high speed operation, and margin for reducing the width of the external clock in the high speed operation. To secure it.

According to one or more exemplary embodiments, a column control circuit includes a latch unit configured to generate a column pulse, which is a column address selection signal, using a set signal and a reset signal; A set signal generator configured to generate the set signal for determining an enable time point of the column pulse by using an internal command input pulse generated from an external command; And a reset unit configured to delay the column pulse according to a signal for controlling an operation speed of a memory device and to generate the reset signal for determining a disable point of time of the column pulse.

In the above configuration, the reset unit preferably uses the cas latency set in the mode register set as a signal for controlling the operation speed of the memory device.

In the above configuration, the reset unit may include a delay unit delaying the column pulse and outputting the delayed signal as a delay signal according to a signal for controlling an operation speed of the memory device; And a reset signal generator for generating the reset signal using the delay signal.

In the above configuration, the delay unit may include delay adjustment means for generating a delay adjustment signal for adjusting a delay amount according to a signal for controlling an operation speed of the memory device; And delay means for adjusting the delay degree of the column pulse according to the delay control signal and outputting the delay signal as the delay signal.

In the above configuration, the delay adjusting means may enable the delay adjusting signal if the cas latency set in the mode register set is a signal for controlling the operation speed of the memory device.

In the above configuration, the delay means includes: first driver means for selectively supplying a power supply voltage and a ground voltage to a first output node according to the column pulse; A first resistor and a plurality of first MOS capacitors coupled to the first output node to delay a signal transmitted to the first output node; And a plurality of second MOS capacitors connected to the first output node, the plurality of second MOS capacitors being turned on in accordance with the delay adjustment signal to delay a signal transmitted to the first output node. It is preferable to output the delay signal.

In the above arrangement, the delay means includes: second driver means for selectively supplying a power supply voltage and a ground voltage to a second output node according to the column pulse; A plurality of second resistors and a plurality of third MOS capacitors coupled to the second output node and delaying a signal transmitted to the second output node in response to the column pulses; A fourth MOS type capacitor for delaying the signal transmitted to the second output node; And a MOS type switch for switching between the second output node and the fourth MOS type capacitor according to the delay adjustment signal, and outputting the delay signal through the second output node.

In the above configuration, the reset signal generator may include: a first inverter chain configured to delay invert the delay signal; And a first NAND gate which NAND combines the delay signal and the output signal of the first inverter chain and outputs the reset signal.

In the above configuration, the first inverter chain is preferably composed of an odd number of inverters connected in series.

In the above configuration, the set signal generator may include: a second inverter chain configured to delay and invert the internal command input pulse; And a second NAND gate NAND combining the internal command input pulse and an output signal of the second inverter chain and outputting the set signal.

In the above configuration, the second inverter chain is preferably composed of an odd number of inverters connected in series.

In the above configuration, the latch unit preferably includes an SR latch for receiving the set signal and the reset signal and outputting the column pulse.

In the above configuration, the SR latch may include: a third NAND gate NAND combining the column pulse and the reset signal; And a fourth NAND gate NAND combining the set signal and the output signal of the third NAND gate to output the column pulses.

According to another aspect of the present invention, a column control circuit may receive a set signal through a set terminal and a reset signal through a reset terminal, thereby inverting a column pulse that is a column address selection signal. SR flip-flop output to the terminal; A set signal generator configured to generate the set signal for determining an enable time point of the column pulse by using an internal command input pulse generated from an external command; A delay unit delaying the column pulse and outputting the delayed signal as a delay signal according to a signal for controlling an operation speed of a memory device; And a reset signal generator for generating the reset signal for determining the point of time when the column pulse is disabled using the delay signal.

In the above configuration, the delay unit preferably uses the cas latency set in the mode register set as a signal for controlling the operation speed of the memory device.

In the above configuration, the delay unit may include delay adjustment means for generating a delay adjustment signal for adjusting a delay amount according to a signal for controlling an operation speed of the memory device; And delay means for adjusting the delay degree of the column pulse according to the delay control signal and outputting the delay signal as the delay signal.

In the above configuration, the delay adjusting means may enable the delay adjusting signal if the cas latency set in the mode register set is a signal for controlling the operation speed of the memory device.

In the above configuration, the delay means includes: first driver means for selectively supplying a power supply voltage and a ground voltage to a first output node according to the column pulse; A first resistor and a plurality of first MOS capacitors coupled to the first output node to delay a signal transmitted to the first output node; And a plurality of second MOS capacitors connected to the first output node, the plurality of second MOS capacitors being turned on in accordance with the delay adjustment signal to delay a signal transmitted to the first output node. It is preferable to output the delay signal.

In the above arrangement, the delay means includes: second driver means for selectively supplying a power supply voltage and a ground voltage to a second output node according to the column pulse; A plurality of second resistors and a plurality of third MOS capacitors coupled to the second output node and delaying a signal transmitted to the second output node according to the column pulses; A fourth MOS type capacitor for delaying the signal transmitted to the second output node; And a MOS type switch for switching between the second output node and the fourth MOS type capacitor according to the delay adjustment signal, and outputting the delay signal through the second output node.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

As an embodiment of the present invention, the circuit of FIG. 4 is disclosed, and an embodiment of the present invention provides a cas latency (CL) that is set in a mode register set as a semiconductor memory device operates at a high speed. Since a larger value among 'CL' values is used, a margin for reducing the pulse width of the external clock EXT_CLK during high-speed operation can be secured by adjusting the pulse width of the column pulse YP according to CL.

In detail, the embodiment of FIG. 4 illustrates a set signal generator 100 generating the set signal SB using an internal read / write input pulse RWP generated from an external command, and a signal PYP having the set signal SB latched according to CL. Delay unit 200 for delaying and outputting delay signal RWPDLY, reset signal generator 300 for generating reset signal RB using delay signal RWPDLY, and generating latch signal PYP using set signal SB and reset signal RB The latch unit 400 and an output unit 500 for receiving the latch signal PYP and outputting a column pulse YP which is a column address selection signal.

The set signal generator 100 performs a NAND combination of the inverter chains INV2 to INV4 for delaying and inverting the internal read / write input pulses RWP, and the output signals of the internal read / write input pulses RWP and the inverter chains INV2 to INV4. The NAND gate NA1 may be configured to output the set signal SB.

In the set signal generator 100 having such a configuration, when the internal read / write input pulse RWP is in the low level state, the output signal of the inverter chains INV2 to INV4 is maintained in the high level state, and the internal read / write input is performed. When the pulse RWP changes from a low level to a high level, the NAND gate NA1 outputs a set signal SB having a low level until a low level output signal is generated in the inverter chains INV2 to INV4. That is, when the internal read / write input pulse RWP becomes high, the set signal generator 100 outputs the set signal SB having a low pulse corresponding to the delay of the inverter chains INV2 to INV4.

The reset signal generator 300 performs a NAND combination of the inverter chains INV5 to INV7 for delay inverting the delay signal RWPDLY output from the delay unit 20, and the output signals of the delay signals RWPDLY and the inverter chains INV5 to INV7. The NAND gate NA4 outputs the reset signal RB.

The reset signal generator 300 having such a configuration outputs a reset signal RB having a low pulse corresponding to the delay of the inverter chains INV5 to INV7 when the delay signal RWPDLY becomes high.

The latch unit 400 may be configured as an SR latch outputting the latch signal PYP using the set signal SB and the reset signal RB. The SR latch latches the NAND combination of the set signal SB and the output signal of the NAND gate NA3. And a NAND gate NA3 for outputting the signal PYP, and a NAND gate NA3 for NAND combining the reset signal RB and the output signal PYP of the NAND gate NA2. In addition, the output unit 500 may include an inverter INV8 for inverting the latch signal PYP and an inverter INV9 for inverting the output signal of the inverter INV8 and outputting the column pulse YP.

The latch unit 400 and the output unit 500 having the above configuration enable the column pulse YP when the set signal SB which is a low pulse occurs, and then disable the column pulse YP when the reset signal RB which is a low pulse occurs. .

The delay unit 200 delays the latch signal PYP according to CL and outputs the delayed signal RWPDLY. The delay unit 200 may be configured as shown in FIGS. 5 and 6.

For example, as illustrated in FIG. 5, the delay unit 200 inverts the delay control signal HS by inverting the NOR gate NR1 and the inversion delay control signal HSB, which combine the CL4 to CL6 to output the inversion delay control signal HSB. Inverter INV10 outputting through the PMOS transistor P2 turns on by the latch signal PYP to raise the node ND1 to the power supply voltage level, and turns on by the latch signal PYP to bring the node ND1 to the ground voltage level. NMOS transistor N2, a resistor R2 connected between the node ND1 and the drain terminal of the NMOS transistor N2, and NMOS and PMOS transistor type capacitors C5 and C6 connected to the node ND1 and having a capacitor function. NMOS transistor type capacitor C7 connected to the node ND1 and turned on by the inversion delay control signal HSB having a capacitor function, and turned on by the delay control signal SB to turn on the capacitor function. Having PMOS The transistor C8 and the inverter INV11 which inverts the signal transmitted to the node ND1 and outputs the delayed signal RWPDLY. In FIG. 5, it is assumed that CLs set in the mode register set are CL5, CL6, and CL7 for high-speed operation.

The delay unit 200 having the configuration as shown in FIG. 5 has an NMOS transistor type capacitor C7 and a PMOS transistor type when the semiconductor memory device does not operate at high speed, that is, when CL set in the mode register set is lower than CL5. As the capacitor C8 is turned on to operate as a capacitor, it outputs the same delay signal RWPDLY as in the prior art.

When the semiconductor memory device operates at a high speed, that is, when the CL set in the mode register set is CL5, CL6, or CL7, the NMOS transistor type capacitor C7 and the PMOS transistor type capacitor C8 are turned off. It does not function as a capacitor. Accordingly, the delay unit 200 outputs a delay signal RWPDLY having an RC delay by the resistor R2 and the NMOS and PMOS transistor type capacitors C5 and C6.

As another example, as illustrated in FIG. 6, the delay unit 200 inverts the delay control signal HS by inverting the NOR gate NR2 and the inversion delay control signal HSB that combine CL4 to CL6 to output the inversion delay control signal HSB. Inverter INV12 outputting through the PMOS transistor P3 turns on by the latch signal PYP to raise the node ND2 to the power supply voltage level, and turns on by the latch signal PYP to bring the node ND2 to the ground voltage level. PMOS and NMOS transistors connected to the resistor R3 and the node ND2 connected between the descending NMOS transistor N3, the node ND2 and the drain terminal of the NMOS transistor N3, and having a capacitor function according to the latch signal PYP. The node ND2 as the PMOS transistor P4 and the PMOS transistor P4 switching between the node ND2 and the PMOS transistor type capacitor C11 by the type capacitors C9 and C10 and the delay control signal HS are turned on. Connected with capacitor As the NMOS transistor N4 and the NMOS transistor N4 switching between the node ND2 and the NMOS transistor type capacitor C12 are turned on by the PMOS transistor type capacitor C11 having the capability, the inversion delay control signal HSB. An NMOS transistor type capacitor C12 connected to the node ND2 and having a capacitor function, and an inverter INV13 inverting the signal transmitted to the node ND2 and outputting the inverted signal as the delay signal RWPDLY. Similarly, in FIG. 6, it is assumed that CL set in the mode register set for high speed operation is CL5, CL6, and CL7.

In the delay unit 200 having the configuration as shown in FIG. 6, when the semiconductor memory device does not operate at high speed, that is, when the CL set in the mode register set is lower than CL5, the PMOS transistor type capacitor C9 is turned on. The RC delayed delay signal RWPDLY is output by the resistor R3, the PMOS transistor type capacitor C9, and the PMOS transistor type capacitor C11 as the capacitor operates.

When the semiconductor memory device operates at a high speed, that is, when the CL set in the mode register set is CL5, CL6, or CL7, the PMOS transistor type capacitor C11 is turned off to not perform the capacitor function. Accordingly, the delay unit 200 outputs the RC delayed delay signal RWPDLY by the resistor R3 and the PMOS transistor type capacitor C9.

Hereinafter, an operation of an embodiment of the present invention will be described in detail with reference to FIG. 7.

First, when the internal read / write input pulse RWP is generated by the external clock EXT_CLK and an external command, the set signal generator 100 generates the set signal SB, which is a low pulse, to enable the column pulse YP.

After the latch signal PYP is delayed through the delay unit 200, the reset signal generator 300 generates a low pulse reset signal RB to disable the column pulse YP. At this time, the generation time of the reset signal RB, which determines the timing at which the column pulse YP is disabled, is determined according to the delay degree of the delay unit 200.

That is, when all of CL4 to CL6 are disabled, all of the MOS capacitors (for example, C5 to C8 of FIG. 5) of the delay unit 200 operate to generate a reset signal RB as shown by a dotted line of FIG. 7. The column pulse YP is disabled at the time when the reset signal RB occurs.

When any one of CL4 to CL6 is enabled, some of the MOS capacitors (for example, C5 to C8 of FIG. 5) of the delay unit 200 do not operate and the solid lines of FIG. 7 do not operate. As described above, the reset signal RB is generated, and the column pulse YP is disabled when the reset signal RB is generated.

Therefore, according to an exemplary embodiment of the present invention, when the value of CL increases in response to a high speed operation, the delay amount of the delay unit 200 is reduced to shorten the occurrence time of the reset signal RB, thereby reducing the pulse width of the column pulse YP to thereby increase the high speed. For operation, it is possible to secure a margin for reducing the period tCK of the external clock EXT_CLK.

As described above, the embodiment of the present invention determines the occurrence time of the reset signal RB, which determines the disable timing of the column pulse YP by adjusting the delay amount according to CL, thereby increasing the pulse width of the column pulse YP if it is not a high speed operation. As the stability of the operation is secured and the high speed operation is performed, the high speed operation is possible by reducing the pulse width of the column pulse YP to reduce the period of the external clock EXT_CLK.

While the invention has been shown and described with reference to specific embodiments, the invention is not limited thereto, and the invention is not limited to the scope of the invention as defined by the following claims. Those skilled in the art will readily appreciate that modifications and variations can be made.

Claims (19)

A column control circuit for controlling input and output of memory cell data, A latch unit generating a column pulse which is a column address selection signal using the set signal and the reset signal; A set signal generator configured to generate the set signal for determining an enable time point of the column pulse by using an internal command input pulse generated from an external command; And And a reset unit configured to delay the column pulse according to a signal for controlling an operation speed of a memory device and to generate the reset signal for determining the disable point of time of the column pulse. The method of claim 1, And the reset unit uses a cas latency set in a mode register set as a signal for controlling an operation speed of the memory device. The method of claim 1, The reset unit, A delay unit delaying the column pulse and outputting the delayed signal as a delay signal according to a signal for controlling an operation speed of the memory device; And And a reset signal generator configured to generate the reset signal by using the delay signal. The method of claim 3, wherein The delay unit, Delay adjusting means for generating a delay adjusting signal for adjusting a delay amount according to a signal for controlling an operating speed of the memory device; And And delay means for controlling the delay degree of the column pulse according to the delay control signal and outputting the delay signal as the delay signal. The method of claim 4, wherein And the delay adjusting means enables the delay adjusting signal when the cas latency set in the mode register set is a signal for controlling the operation speed of the memory device. The method of claim 4, wherein The delay means, First driver means for selectively supplying a power supply voltage and a ground voltage to a first output node according to the column pulse; A first resistor and a plurality of first MOS capacitors coupled to the first output node to delay a signal transmitted to the first output node; And And a plurality of second MOS capacitors connected to the first output node and configured to delay a signal transmitted to the first output node by being turned on according to the delay control signal. And output the delay signal through the first output node. The method of claim 4, wherein The delay means, Second driver means for selectively supplying a supply voltage and a ground voltage to a second output node in response to the column pulses; A plurality of second resistors and a plurality of third MOS capacitors coupled to the second output node and delaying a signal transmitted to the second output node in response to the column pulses; A fourth MOS type capacitor for delaying the signal transmitted to the second output node; And And a MOS type switch for switching between the second output node and the fourth MOS type capacitor according to the delay control signal. And output the delay signal through the second output node. The method of claim 3, wherein The reset signal generator, A first inverter chain for delay inverting the delay signal; And And a first NAND gate NAND combining the delay signal and the output signal of the first inverter chain and outputting the reset signal as the reset signal. The method of claim 8, And said first inverter chain consists of an odd number of inverters connected in series. The method of claim 1, The set signal generator, A second inverter chain for delay inverting the internal command input pulse; And And a second NAND gate NAND combining the internal command input pulse and an output signal of the second inverter chain and outputting the set signal as the set signal. The method of claim 10, And said second inverter chain comprises an odd number of inverters connected in series. The method of claim 1, And the latch unit includes an SR latch for receiving the set signal and the reset signal and outputting the set signal as the column pulses. The method of claim 12, The SR latch, A third NAND gate NAND combining the column pulse and the reset signal; And And a fourth NAND gate NAND combining the set signal and the output signal of the third NAND gate to output the column pulses. A column control circuit for controlling input and output of memory cell data, An SR flip-flop that receives a set signal through a set terminal, receives a reset signal through a reset terminal, and outputs a column pulse that is a column address selection signal to an inverting output terminal; A set signal generator configured to generate the set signal for determining an enable time point of the column pulse by using an internal command input pulse generated from an external command; A delay unit delaying the column pulse and outputting the delayed signal as a delay signal according to a signal for controlling an operation speed of a memory device; And And a reset signal generator for generating the reset signal for determining the disable point of time of the column pulse using the delay signal. The method of claim 14, And the delay unit uses a cas latency set in a mode register set as a signal for controlling an operation speed of the memory device. The method of claim 14, The delay unit, Delay adjusting means for generating a delay adjusting signal for adjusting a delay amount according to a signal for controlling an operating speed of the memory device; And And delay means for controlling the delay degree of the column pulse according to the delay control signal and outputting the delay signal as the delay signal. The method of claim 16, And the delay adjusting means enables the delay adjusting signal when the cas latency set in the mode register set is a signal for controlling the operation speed of the memory device. The method of claim 16, The delay means, First driver means for selectively supplying a power supply voltage and a ground voltage to a first output node according to the column pulse; A first resistor and a plurality of first MOS capacitors coupled to the first output node to delay a signal transmitted to the first output node; And And a plurality of second MOS capacitors connected to the first output node and configured to delay a signal transmitted to the first output node by being turned on according to the delay control signal. And output the delay signal through the first output node. The method of claim 16, The delay means, Second driver means for selectively supplying a supply voltage and a ground voltage to a second output node in response to the column pulses; A plurality of second resistors and a plurality of third MOS capacitors coupled to the second output node and delaying a signal transmitted to the second output node in response to the column pulses; A fourth MOS type capacitor for delaying the signal transmitted to the second output node; And And a MOS type switch for switching between the second output node and the fourth MOS type capacitor according to the delay control signal. And output the delay signal through the second output node.

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