KR20070106358A - A method for fabricating a micro structures with multi differential gap on silicon substrate - Google Patents

A method for fabricating a micro structures with multi differential gap on silicon substrate Download PDF

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KR20070106358A
KR20070106358A KR1020060046517A KR20060046517A KR20070106358A KR 20070106358 A KR20070106358 A KR 20070106358A KR 1020060046517 A KR1020060046517 A KR 1020060046517A KR 20060046517 A KR20060046517 A KR 20060046517A KR 20070106358 A KR20070106358 A KR 20070106358A
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mask layer
substrate
silicon substrate
etching
forming
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KR100817813B1 (en
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조동일
최병두
백승준
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재단법인서울대학교산학협력재단
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0003—MEMS mechanisms for assembling automatically hinged components, self-assembly devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3088—Process specially adapted to improve the resolution of the mask

Abstract

A method of forming a micro structure with vertical step height on a silicon substrate is provided to float the micro structure by forming the vertical step height and subjecting the substrate to wet etching. A first mask layer(120) is formed on a single crystal silicon substrate, and then a second mask layer is formed on the substrate. The substrate is etched by using the first or second mask layer. The mask layer is removed, and the substrate is etched by using the first mask layer to form a trench. A protective layer(140) is formed on a sidewall of the trench. The substrate is further etched by using the first mask and the protective layer as a mask. The substrate is subjected to wet etching to form a cavity on a bottom surface of the trench.

Description

실리콘 기판 상에 상이한 수직 단차를 갖는 미세구조물의 제조 방법 {A method for fabricating a micro structures with multi differential gap on silicon substrate}A method for fabricating a micro structures with multi differential gap on silicon substrate}

도 1은 수직 단차를 갖는 MEMS 가속도계의 사시도.1 is a perspective view of a MEMS accelerometer with a vertical step.

도 2a 내지 도 2k는 본 발명의 미세구조물 제조방법에 따른 일실시예의 공정 단면도. Figure 2a to 2k is a cross-sectional view of an embodiment according to the method for manufacturing a microstructure of the present invention.

본 발명은 단결정 실리콘 기판 상에 상이한 단차를 갖는 미세 구조물을 형성하는 방법에 관한 것이다. 본 발명에서는 수직 단차를 형성한 후에 습식 식각을 수행하여 상이한 단차를 갖는 미세 구조물을 바닥면으로부터 부유시켜 형성한다.The present invention relates to a method of forming microstructures having different steps on a single crystal silicon substrate. In the present invention, after forming the vertical step, the wet etching is performed to form fine structures having different steps from the floating surface.

일반적으로, 실리콘 기판 상에 미세 구조물을 형성하는 MEMS (Micro-electro-mechanical System) 기술은 실리콘 공정을 이용하여 시스템의 특정 부위를 마이크로미터 단위의 정교한 형상으로 실리콘 기판 상에 집적 및 형성하는 기술이다. 이러한 MEMS 기술은 박막 증착, 식각 기술, 사진 묘화 기술, 불순물 확산 및 주입 기술 등의 반도체 소자 제조 기술을 기초로 한다.In general, micro-electro-mechanical system (MEMS) technology, which forms a microstructure on a silicon substrate, is a technique for integrating and forming a specific portion of a system on a silicon substrate in a micrometer-detailed shape using a silicon process. . Such MEMS technology is based on semiconductor device manufacturing technology, such as thin film deposition, etching, photo-imaging, impurity diffusion and implantation.

단결정 실리콘 기판, 예를 들어, <111> 실리콘 기판에 고형상비(high aspect ratio)의 수직 단차를 갖는 MEMS 구동기를 제조하는 ESBM(Extended Sacrificial Bulk Micromachining) 기술이 알려져 있다. 그러나, 상기 ESBM 기술은 습식 식각을 수행한 후에, 수직 단차를 형성하기 때문에, 수행 공정 개수가 많고 복잡하여 수율이 떨어지며, 구조물이 부유된 후 건식 식각을 수행하기 때문에 간혹 구조물의 손상(sticktion) 또는 비틀림 등이 발생하는 문제가 있다. Extended Sacrificial Bulk Micromachining (ESBM) technology is known for fabricating MEMS drivers having a vertical difference of high aspect ratio on a single crystal silicon substrate, for example, a <111> silicon substrate. However, since the ESBM technique forms a vertical step after performing wet etching, the yield is low because the number of processes to be performed is large and complex, and sometimes dry etching is performed after the structure is suspended. There is a problem that a torsion occurs.

ESBM을 제외한 기존의 수직 단차를 형성하는 방법으로는 SOI(silicon on insulator), 이중 SOI, SOG(silicon on glass) 등 여러 층의 웨이퍼를 접합하여 수직 단차를 가지는 구조물을 제작하는 방법이 있다. 그렇기 때문에, 잔류 응력 문제, 응력 구배 문제, 및 상부와 하부 구조물 간의 정렬 오차 발생 등이 발생하여 미세 구조물의 성능이 저하된다.Except for ESBM, there is a method of forming a vertical step by fabricating a structure having a vertical step by joining wafers of several layers such as silicon on insulator (SOI), double SOI, and silicon on glass (SOG). As a result, residual stress problems, stress gradient problems, and alignment errors between upper and lower structures occur, thereby degrading the performance of the microstructure.

본 발명은 상기한 바와 같은 문제점을 해결하기 위하여 안출된 것으로서, 본 발명에서는 수직 단차를 형성한 후에 습식 식각을 수행하여, 상이한 단차를 갖는 미세 구조물을 바닥면으로부터 부유시켜 형성한다. 따라서, 기존의 ESBM 공정의 복잡성과 난해함을 해결할 수 있고, 웨이퍼 접합을 이용한 수직 단차 형성 방법이 가지는 잔류 응력 문제, 응력 구배 문제, 및 상부와 하부 구조물 간의 정렬 오차 발생 문제 등을 해결할 수 있다.The present invention has been made to solve the problems described above, in the present invention, by performing a wet etching after forming a vertical step, it is formed by floating a microstructure having a different step from the bottom surface. Therefore, the complexity and difficulty of the existing ESBM process can be solved, and the residual stress problem, stress gradient problem, and alignment error between the upper and lower structures of the vertical step forming method using wafer bonding can be solved.

따라서, 본 발명의 목적은 단결정 실리콘 기판 상에 상이한 단차를 갖는 미 세 구조물을 형성하는 방법을 제공하기 위한 것이다. 또한, 본 발명의 목적은 상이한 단차를 갖는 미세 구조물이 형성된 MEMS 소자에 관한 것이다.Accordingly, it is an object of the present invention to provide a method for forming fine structures having different steps on a single crystal silicon substrate. The object of the present invention also relates to a MEMS device in which microstructures having different steps are formed.

본 발명은 단결정 실리콘 기판 상에 상이한 단차의 미세 구조물을 형성하는 방법에 관한 것이다.The present invention relates to a method of forming microstructures of different steps on a single crystal silicon substrate.

더욱 구체적으로 본 발명은,More specifically, the present invention,

단결정 실리콘 기판 상에 제1마스크층을 형성한 후에 패터닝하는 단계(a);Patterning (a) after forming the first mask layer on the single crystal silicon substrate;

상기 기판 상에 제2마스크층을 형성한 후에 패터닝하는 단계(b);(B) forming and patterning a second mask layer on the substrate;

상기 제1마스크층 또는 상기 제2마스크층을 사용하여 상기 기판을 식각하는 단계(c);Etching (c) the substrate using the first mask layer or the second mask layer;

상기 제2마스크층을 제거하는 단계(d);(D) removing the second mask layer;

상기 제1마스크층을 사용하여 상기 기판을 식각하는 단계(e);(E) etching the substrate using the first mask layer;

식각에 의하여 형성된 트렌치의 측벽에 보호막을 형성하는 단계(f);Forming a protective film on sidewalls of the trench formed by etching (f);

상기 제1마스크층 및 보호막을 식각 마스크로 사용하여 상기 기판을 소정 깊이로 추가로 식각하는 단계(g);(G) further etching the substrate to a predetermined depth by using the first mask layer and the passivation layer as an etching mask;

상기 기판을 습식식각하여 상기 추가로 식각된 트렌치의 바닥면에 캐비티(cavity)를 형성시킴으로써, 상이한 단차를 갖는 미세구조물을 상기 바닥면으로부터 부유시키는 단계(h); 및(H) floating microstructures having different steps from the bottom surface by wet etching the substrate to form a cavity in the bottom surface of the additionally etched trench; And

상기 측벽 보호막 및 제1식각마스크를 제거하는 단계(i)를 포함한다.(I) removing the sidewall protective layer and the first etching mask.

또한, 본 발명은 상기한 방법에 의하여 단결정 실리콘 기판 상에 상이한 단 차의 미세 구조물이 형성된 MEMS 소자에 관한 것이다.The present invention also relates to a MEMS device in which microstructures of different steps are formed on a single crystal silicon substrate by the above method.

단결정 실리콘기판으로는, 기계적으로 매우 안정한 <111> 실리콘 기판을 사용하는 것이 바람직하다.As the single crystal silicon substrate, it is preferable to use a mechanically stable <111> silicon substrate.

이하에서는, 도면을 참조하여 본 발명의 실시예를 구체적으로 설명한다. 그러나, 본 발명이 하기 실시예에 의하여 제한되는 것은 아니다.Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited by the following examples.

도 1은 본 발명에 따른 미세구조물 제작방법을 사용하여 제조된 MEMS 미세구조물의 예(미세가속도계)의 사시도이다. 상기 가속도계는 구동전극, 검지전극(240), 및 내부질량체 등을 포함하며, 상기 내부질량체는 스프링(210)에 의하여 기준전극과 연결된다. 상기 검지전극(240)과 내부질량체는 콤 구조에 의하여 서로 맞물려 있다. 즉, 검지전극의 콤구조(220)와 내부질량체의 콤구조(230)가 서로 맞물려 있는 구조이다. 가속도계가 운동하는 경우, 상기 콤구조(220, 230) 사이의 용량성 성분의 변화를 검지하여 가속도를 측정할 수 있다.1 is a perspective view of an example (micro accelerometer) of a MEMS microstructure manufactured using the microstructure fabrication method according to the present invention. The accelerometer includes a drive electrode, a detection electrode 240, and an internal mass, and the internal mass is connected to the reference electrode by a spring 210. The detection electrode 240 and the internal mass are engaged with each other by the comb structure. That is, the comb structure 220 of the detection electrode and the comb structure 230 of the internal mass are engaged with each other. When the accelerometer is in motion, the acceleration may be measured by detecting a change in the capacitive component between the comb structures 220 and 230.

상기 도 1에 도시되어 있는 바와 같이, 상기 콤 구조(220, 230)는 상이한 단차층을 갖는 것이 바람직하다. 상기 스프링(210)은 얇은 단차를 가지게 할 수도 있고, 얇은 단차를 가지지 않게 할 수도 있다.As shown in FIG. 1, the comb structures 220 and 230 preferably have different stepped layers. The spring 210 may have a thin step or may not have a thin step.

단결정 실리콘기판으로는, 기계적으로 매우 안정한 <111> 실리콘 기판을 사용한다.As the single crystal silicon substrate, a mechanically stable <111> silicon substrate is used.

도 2a 내지 도 2k는 본 발명에 따라 상기 도 1에 도시된 미세구조물을 제조하기 위한 공정을 A-A'라인을 절취한 단면을 통하여 도시한 공정 단면도이다.2A to 2K are cross-sectional views illustrating a process for manufacturing the microstructure shown in FIG. 1 through a cross section taken along the line A-A 'according to the present invention.

먼저, <111> 단결정 실리콘 기판(110) 상에 제1마스크층(예를 들어, TEOS 산화막층)(120)을 형성한 후에, 포토레지스트 등을 사용하여 패터닝한다(도 2a).First, a first mask layer (eg, TEOS oxide layer) 120 is formed on the <111> single crystal silicon substrate 110 and then patterned using a photoresist or the like (FIG. 2A).

이후, 상기 기판 상에 제2마스크층(예를 들어, TEOS 산화막층)(130)을 형성한다(도 2b).Thereafter, a second mask layer (eg, a TEOS oxide layer) 130 is formed on the substrate (FIG. 2B).

이후, 포토레지스트 등을 사용하여 상기 제2마스크층을 패터닝한다(도 2c). 이때, 상기 제1마스크층(120)은 상기 제2마스크층(130)에 의하여 덮여지는 부분(121)과, 제2마스크층(130)에 의하여 덮여지지 않고 그대로 노출되는 부분도 있다(122).Thereafter, the second mask layer is patterned using a photoresist or the like (FIG. 2C). In this case, the first mask layer 120 may include a portion 121 covered by the second mask layer 130 and a portion that is not covered by the second mask layer 130 and is exposed as it is (122). .

이후 상기 제2마스크층(130)으로 제1마스크층(122)를 소정의 두께로 식각한다.Thereafter, the first mask layer 122 is etched by the second mask layer 130 to a predetermined thickness.

이후, 상기 제1마스크층(122) 또는 상기 제2마스크층(130)을 식각 마스크로 사용하여, 상기 기판을 소정 깊이로 식각한다(도 2d). 이 때, 상기 제2마스크층(130)에 의하여 덮여지지 않은 채 그대로 노출된 제1마스크층(122)은 그 두께가 다른 제1마스크층(121)에 비하여 얇아진다.Thereafter, the substrate is etched to a predetermined depth by using the first mask layer 122 or the second mask layer 130 as an etching mask (FIG. 2D). In this case, the first mask layer 122 exposed without being covered by the second mask layer 130 is thinner than the first mask layer 121 having a different thickness.

이후, 상기 제2마스크층(130)을 제거한다(도 2e).Thereafter, the second mask layer 130 is removed (FIG. 2E).

이후, 상기 제1마스크층(120)을 식각 마스크로 사용하여 소정 깊이로 식각한다(도 2f). 상기 식각 깊이에 의하여 상기 콤구조(220) 및 콤구조(230) 사이의 단차의 높이 차가 결정된다.Thereafter, the first mask layer 120 is etched to a predetermined depth using the etching mask (FIG. 2F). The height difference of the step between the comb structure 220 and the comb structure 230 is determined by the etching depth.

이후, 상기 식각에 의하여 형성되는 트렌치의 측벽에 보호막(140)을 형성한다(도 2g).Thereafter, a protective film 140 is formed on sidewalls of the trench formed by the etching (FIG. 2G).

이후, 상기 트렌치의 바닥면에 형성된 보호막(140)을 제거한다(도 2h). 이 때, 다른 제1마스크층보다 상대적으로 얇은 두께를 갖는 제1마스크층(122)도 함께 제거된다. Thereafter, the protective layer 140 formed on the bottom surface of the trench is removed (FIG. 2H). At this time, the first mask layer 122 having a thickness relatively thinner than the other first mask layers is also removed.

이후, 상기 제1마스크층(120) 및 상기 보호막(140)을 식각 마스크로 사용하여, 상기 기판(110)을 소정 깊이로 추가로 식각한다(도 2i).Thereafter, the substrate 110 is further etched to a predetermined depth by using the first mask layer 120 and the passivation layer 140 as an etching mask (FIG. 2I).

이후, 상기 기판(110)을 예를 들어, 알칼리 수용액으로 습식식각하여, 상기 기판의 바닥면 상에 캐비티를 형성시킴으로써, 다양한 단차를 갖는 미세구조물을 상기 바닥면으로부터 부유시킨다(도 2j).Thereafter, the substrate 110 is wet-etched with, for example, an aqueous alkali solution to form a cavity on the bottom surface of the substrate, thereby floating a microstructure having various steps from the bottom surface (FIG. 2J).

이후, 상기 측벽 보호막(140) 및 제1마스크층(120)을 제거한다(도 2k).Thereafter, the sidewall passivation layer 140 and the first mask layer 120 are removed (FIG. 2K).

이러한 공정을 통하여, 상이한 단차의 콤 구조(220, 230)를 동시에 형성할 수 있다.Through this process, comb structures 220 and 230 having different steps can be simultaneously formed.

본 발명은 <111> 실리콘 기판과 같은 단결정 실리콘 기판 상에 상이한 단차를 갖는 미세 구조물을 형성하는 방법에 관한 것이다. 본 발명에서는 수직 단차를 형성한 후에 습식 식각을 수행하여 상이한 단차를 갖는 미세 구조물을 바닥면으로부터 부유시켜 형성한다. 따라서, 기존 ESBM 공정의 습식 식각 후 수직 단차를 형성할 시 공정의 복잡성과 난해함을 해결할 수 있고, 또한, ESBM 공정을 제외한 웨이퍼 접합을 이용한 수직 단차 형성하는 방법이 가지는 잔류 응력 문제, 응력 구배 문제, 상부와 하부 구조물 간의 정렬 오차 발생 등을 방지할 수 있다.The present invention relates to a method of forming microstructures having different steps on a single crystal silicon substrate, such as a <111> silicon substrate. In the present invention, after forming the vertical step, the wet etching is performed to form fine structures having different steps from the floating surface. Therefore, it is possible to solve the complexity and difficulty of forming a vertical step after wet etching of the existing ESBM process, and also has a residual stress problem, a stress gradient problem, It is possible to prevent the occurrence of alignment errors between the upper and lower structures.

Claims (9)

단결정 실리콘 기판 상에 상이한 단차의 미세 구조물을 형성하는 방법으로서,A method of forming microstructures of different steps on a single crystal silicon substrate, 단결정 실리콘 기판 상에 제1마스크층을 형성한 후에 패터닝하는 단계(a);Patterning (a) after forming the first mask layer on the single crystal silicon substrate; 상기 기판 상에 제2마스크층을 형성한 후에 패터닝하는 단계(b);(B) forming and patterning a second mask layer on the substrate; 상기 제1마스크층 또는 상기 제2마스크층을 사용하여 상기 기판을 식각하는 단계(c);Etching (c) the substrate using the first mask layer or the second mask layer; 상기 제2마스크층을 제거하는 단계(d);(D) removing the second mask layer; 상기 제1마스크층을 사용하여 상기 기판을 식각하는 단계(e);(E) etching the substrate using the first mask layer; 식각에 의하여 형성된 트렌치의 측벽에 보호막을 형성하는 단계(f);Forming a protective film on sidewalls of the trench formed by etching (f); 상기 제1마스크층 및 보호막을 식각 마스크로 사용하여 상기 기판을 소정 깊이로 추가로 식각하는 단계(g);(G) further etching the substrate to a predetermined depth by using the first mask layer and the passivation layer as an etching mask; 상기 기판을 습식식각하여 상기 추가로 식각된 트렌치의 바닥면에 캐비티(cavity)를 형성시킴으로써, 상이한 단차를 갖는 미세구조물을 상기 바닥면으로부터 부유시키는 단계(h); 및(H) floating microstructures having different steps from the bottom surface by wet etching the substrate to form a cavity in the bottom surface of the additionally etched trench; And 상기 측벽 보호막 및 제1마스크층을 제거하는 단계(i)를 포함하는 것을 특징으로 하는 미세 구조물 형성 방법.Removing the sidewall passivation layer and the first mask layer (i). 제 1 항에 있어서, 상기 단결정 실리콘 기판은 <111> 실리콘 기판인 것을 특 징으로 하는 미세 구조물 형성 방법.The method of claim 1, wherein the single crystal silicon substrate is a <111> silicon substrate. 제 1 항에 있어서, 상기 단계(b) 수행 시,The method of claim 1, wherein in the step (b), 상기 제1마스크층의 일부분이 상기 제2마스크층에 의하여 덮여지지 않고 노출되도록 상기 제2마스크층이 패터닝되는 것을 특징으로 하는 미세 구조물 형성 방법.And the second mask layer is patterned such that a portion of the first mask layer is not covered by the second mask layer and is exposed. 제 3 항에 있어서, 상기 단계(c) 수행시,The method of claim 3, wherein in performing step (c), 상기 제2마스크층에 의하여 덮여지지 않고 노출된 상기 제1마스크층의 일부분이 함께 식각되어, 그 두께가 얇아지게 되는 것을 특징으로 하는 미세 구조물 형성 방법.A portion of the first mask layer exposed without being covered by the second mask layer is etched together, so that the thickness thereof becomes thin. 제 4 항에 있어서, 상기 단계(f) 및 단계(g) 사이에,The method of claim 4, wherein between steps (f) and (g), 상기 기판 상의 바닥면에 형성된 보호막을 제거하는 단계(j)를 추가로 포함하는 것을 특징으로 하는 미세 구조물 형성 방법.And (j) removing the protective film formed on the bottom surface of the substrate. 제 5 항에 있어서, 상기 단계(j) 수행시,The method of claim 5, wherein when performing step (j), 두께가 얇아진 상기 제1마스크층 일부분이 함께 제거되는 것을 특징으로 하는 미세 구조물 형성 방법.And a portion of the first mask layer, which has become thin, is removed together. 제 1 항에 있어서, 상기 단계(f) 및 단계(g) 사이에,The method of claim 1, wherein between steps (f) and (g), 상기 기판 상의 바닥면에 형성된 보호막을 제거하는 단계(j)를 추가로 포함하는 것을 특징으로 하는 미세 구조물 형성 방법.And (j) removing the protective film formed on the bottom surface of the substrate. 제 1 항에 있어서, 상기 단계(h)에서 알칼리 수용액을 사용하여 습식식각하는 것을 특징으로 하는 방법.The method of claim 1, wherein in the step (h) it is wet etching using an aqueous alkali solution. 제 1 항 내지 제 8 항 중 어느 한 항에 따른 미세 구조물 형성 방법에 의하여 형성된 미세구조물을 포함하는 것을 특징으로 하는 MEMS 소자.MEMS device comprising a microstructure formed by the method for forming a microstructure according to any one of claims 1 to 8.
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US10807863B2 (en) 2017-05-30 2020-10-20 Murata Manufacturing Co., Ltd. Method for manufacturing micromechanical structures in a device wafer
US11524893B2 (en) 2017-05-30 2022-12-13 Murata Manufacturing Co., Ltd. Method for manufacturing micromechanical structures in a device wafer
US11094552B2 (en) 2018-11-23 2021-08-17 Murata Manufacturing Co., Ltd. Method for etching recessed structures

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