KR100748741B1 - Method for manufacture of silicon release structure using Silicon On Insulator - Google Patents

Abstract

The present invention relates to a method of manufacturing a silicon flotation structure using a cross-bonded SOI wafer, and more particularly, to avoid etching the upper vibrating structure and etching only the lower handling wafer while using the thickness of silicon oxide of the conventional SOI wafer. Thus, the present invention relates to a method of manufacturing a silicon flotation structure using a cross-bonded SOI wafer to ensure a gap of 50 microns or more between the silicon structure and the lower handling wafer.

To this end, the present invention comprises the steps of growing an oxide film on each of the process wafer and the handling wafer; Bonding the process wafer and the handling wafer; Adjusting the process wafer to a thickness of a silicon structure to be manufactured; Depositing a mask on an upper surface of the process wafer; Performing a photolithography process to generalize the pattern; Patterning a mask using a PR pattern; Forming a silicon structure by etching a process wafer by the patterned mask; Growing an oxide film to protect sidewall surfaces of the silicon structure; 9 steps of etching and removing the silicon oxide film exposed by the etching of the silicon structure; 10 steps of supporting the silicon structure by etching the handling wafer; And an eleven step of removing the oxide film surrounding the silicon structure.

SOI wafers, silicon oxide, photolithography, masks, process wafers, silicon structures

Description

Method for manufacture of silicon release structure using Silicon On Insulator}

1 is a cross-sectional view showing a conventional SOI wafer.

2A to 2K are cross-sectional views illustrating a method for manufacturing a silicon flotation structure using a cross-bonded SOI wafer according to the present invention.

3 is a conceptual diagram showing a bonding method of a process wafer and a handling wafer according to the present invention.

Figure 4 is an excerpt view showing the thickness of each configuration in the SOI wafer according to the present invention.

Figure 5 is a schematic diagram showing the characteristics of this corrosion angle in the flotation process according to the present invention.

Figure 6 is an image showing the actual etching in the flotation process according to the invention.

<Description of the symbols for the main parts of the drawings>

10: SOI wafer 11: process wafer

12: handling wafer 13: etching mask

14 silicon oxide film 15 oxide film

16: etching hole

The present invention relates to a method of manufacturing a silicon flotation structure using a cross-bonded SOI wafer, and more particularly, to avoid etching the upper vibrating structure and etching only the lower handling wafer while using the thickness of silicon oxide of the conventional SOI wafer. Thus, the present invention relates to a method of manufacturing a silicon flotation structure using a cross-bonded SOI wafer to ensure a gap of 50 microns or more between the silicon structure and the lower handling wafer.

In general, MEMS (Micro-Electro Mechanical Systems, hereinafter referred to as "MEMS") is a technology that combines a computer with tiny machinery such as sensors, valves, gears, reflectors, and drivers embedded in a semiconductor chip. It is also called "thing."

Basically, MEMS devices include microcircuits on tiny silicon chips that some mechanical devices, such as reflectors and sensors, have been built on.

Perhaps these chips can be made cost-effective for many purposes by assembling large quantities at low cost.

MEMS (Micro-Electro-Mechanical System) using silicon wafers have been actively studied in various systems due to the advantage of combining mechanical structures and electrical circuits.

Among them, many systems that vibrate silicon structures such as resonator and gyroscope have been studied.

In order for the silicon vibrator to vibrate at an appropriate frequency, the silicon vibrator should be designed to be less air resistant.

To reduce the air resistance, there is a method of increasing the distance between the silicon structure and the lower substrate, or packaging the silicon structure in a vacuum.

The vacuum packaging method is excellent in reducing air resistance, but has a problem in that cost is high and durability is reduced.

Therefore, recent studies have been actively conducted to support the silicon structure by greatly increasing the distance between the silicon structure and the lower substrate to which the structure is bonded (at least 50 microns or more) without using a vacuum package.

In other words, after combining the silicon wafer (process wafer) and the lower substrate (handling wafer) on which the silicon structure is to be formed, the silicon wafer is patterned and etched to form a structure, and then the lower substrate is etched to a certain thickness to form the structure and the lower substrate. Secure the gap between (floating process).

However, in order to increase the gap between the lower substrate and the silicon structure, the silicon structure and the lower substrate must be differentially etched with respect to the same etching material (process).

To do this, the materials of the silicon structure and the lower substrate must be different. In this case, the biggest problem is the stress at the joints caused by the difference in thermal expansion coefficient of the two materials.

This stress affects the change of the designed resonant frequency and causes malfunction.

In order to minimize the stress, glass having a similar coefficient of thermal expansion to silicon (eg, Corning's 7470, etc.) is used as the substrate, which also exhibits a relatively large difference in coefficient of thermal expansion with silicon in the low temperature region (subzero). There is a disadvantage that the increase of the error of the inevitable.

The best way to avoid this drawback is to use the same silicon wafer as the bottom substrate for the structure.

Wafers that can be used for this purpose include silicon on insulator (SOI) wafers.

As shown in FIG. 1, an SOI wafer is formed between a process wafer 100 on which a silicon structure is to be formed and a handling wafer 110, which is a lower substrate, through a silicon oxide 120 (SiO ₂ -Buried oxide layer). Structure.

In order to create a suspended structure using such a wafer, the thickness of the intermediate silicon oxide 120 is required to be at least 50 microns or more (typically 0.5 or 1 micron), because the wafer is stressed due to a difference in coefficient of thermal expansion with silicon. The manufacture and use of such wafers is impossible.

Therefore, in order to use a conventional SOI wafer (oxide thickness of 1 micron), it is necessary to etch the handling wafer 110 made of silicon, and to etch only the handling wafer 110 while avoiding etching the process wafer 100 of the same material. There is a difficult problem.

The present invention has been made in view of the above, in the SOI substrate in which the process wafer and the handling wafer are combined via silicon oxide, performing a photolithography process to generalize the pattern, and process using the PR pattern Patterning a mask oxide film deposited on the wafer, etching the process wafer using the patterned mask to etch a shape of the silicon structure, forming an oxide film to protect sidewalls of the silicon structure, etching the structure By removing the intermediate oxide film revealed by the anisotropic etching, removing the portion projected on the handling wafer in the same manner as the shape of the silicon structure by isotropic dry etching, and removing the oxide film surrounding the silicon structure, SOI wafer Of the silicon flotation structure using a cross-bonded SOI wafer that avoids the etching of the upper vibrating structure and etches only the lower handling wafer to secure more than 50 microns of gap between the silicon structure and the lower handling wafer while using the thickness of the silicon oxide. The purpose is to provide a manufacturing method.

In order to achieve the above object, the present invention provides a method for manufacturing a silicon flotation structure using an SOI wafer in which a process wafer and a handling wafer are coupled through a silicon oxide film.

Growing an oxide film on the process wafer and the handling wafer, respectively; Bonding the process wafer and the handling wafer; Adjusting the process wafer to a thickness of a silicon structure to be manufactured; Depositing a mask on an upper surface of the process wafer; Performing a photolithography process to generalize the pattern; Patterning a mask using a PR pattern; Forming a silicon structure by etching a process wafer by the patterned mask; Growing an oxide film to protect sidewall surfaces of the silicon structure; 9 steps of etching and removing the silicon oxide film exposed by the etching of the silicon structure; 10 steps of supporting the silicon structure by etching the handling wafer; And an eleven step of removing the oxide film surrounding the silicon structure.

In a preferred embodiment, in the step 2, the bonding of the process wafer and the handling wafer may be performed by tilting the crystal directions of the two wafers at 45 °.

In a more preferred embodiment, the mask in step 4 is characterized by having a sufficient etching selectivity and thickness to etch the process wafer and silicon oxide film by DRIE.

In addition, the silicon oxide film exposed by the etching of the silicon structure in step 6 may be removed by anisotropic dry etching.

In addition, the portion projected on the handling wafer in the same manner as the shape of the silicon structure in step 10 is characterized in that it is removed by anisotropic dry etching.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A to 2H are cross-sectional views illustrating a method of manufacturing a silicon flotation structure using a cross-bonded SOI wafer according to the present invention.

The present invention employs an SOI wafer 10 to secure a gap between the lower substrate, the handling wafer 12, and the process wafer 11 on which the silicon structure is to be formed. The main focus is on the differential etching.

As described above, a silicon on insulator is a wafer having a silicon single crystal layer on an insulating film, which is commonly referred to as SOI.

SOI is characterized in that parasitic capacitance is reduced because a thin insulating layer is buried between the process wafer 11 and the handling wafer 12 forming a circuit, thereby improving the performance of the device.

In addition, SOI can speed up operation at the same voltage and lower the supply voltage at the same speed.

Referring to the manufacturing method of the silicon flotation structure using the cross-bonded SOI wafer according to the present invention.

(1) Wafer Oxidation (Wafer Oxidation): An oxide film 15 (SiO ₂ ) is first grown on the upper and lower surfaces of the process wafer 11 and the handling wafer 12. At this time, the thickness of the growing oxide film 15 is about twice as thick as the silicon oxide film 14 to be described later (see FIG. 2A).

(2) Wafer Bonding: The process wafer 11 and the handling wafer 12 are bonded. At this time, when the process wafer 11 and the handling wafer 12 are bonded together, as shown in FIG. 3, the crystal directions of the two wafers are tilted by 45 ° to bond them together (see FIG. 2B).

③ Wafer thinning and chemical mechanical planarization (CMP): The process wafer 11 is controlled by lapping or chemical etching to match the thickness of the silicon structure to be manufactured. Reference)

Here, the SOI wafer 10 is composed of a process wafer 11, a silicon oxide film 14 (buried SiO ₂ ), and a handling wafer 12 in the order of being located thereon. In this case, the process wafer 11 and the handling wafer 12 are silicon (Si), and the silicon oxide film 14 is SiO ₂ .

As shown in FIG. 4, the thickness of the process wafer 11 is to be the thickness of the device, that is, the silicon structure, to be finally manufactured.

As the thickness t _o2 of the silicon oxide film 14 is thinner, damage (ATTACK) may be minimized at other portions during the six-step anisotropic etching of the oxide film (SiO ₂ ), so that the thickness t _o2 is preferably 0.5 μm or less.

At this time, the handling wafer 12 is preferably about 500μm.

④ Deposition of DRIE Etch Mask 13: An etching mask 13, such as SiO ₂ or Al, is deposited on the upper surface of the process wafer 11. (See FIG. 2D)

The thickness of the etching mask 13 should have a sufficient etching selectivity and thickness to etch the process wafer 11 and the silicon oxide film 14 by deep reactive ion etching (DRIE). In this case, the etching mask 13 may be a TEOS oxide, PECVD oxide or Al thin film.

⑤ Photolithography: The pattern is generalized by performing a photolithography process on the upper surface of the etch mask 13 (see FIG. 2E).

⑥ Etch mask patterning: The etching mask 13 is patterned using the PR pattern formed in step 5 (see FIG. 2F).

At this time, the etching of the etching mask 13, which is an oxide film (SiO ₂ ), may be dry or wet, but dry etching may be used for anisotropic etching for precise patterning.

(7) Process wafer 11 etching: The process wafer 11 to be formed into a silicon structure by the etching mask 13 patterned in step 6 is DRIE to define the silicon structure (see FIG. 2G).

⑧ Formation of sidewall oxide film: An oxide film is formed on the wall surface of the silicon structure by performing oxidation to protect the sidewall surface of the silicon structure. At this time, the thickness of the grown oxide film (SiO ₂ ) is determined in step 11 so that the structure on the process wafer 11 side is not damaged during XeF ₂ dry isotropic etching (see FIG. 2H).

Between steps 4 and 5, a process of removing the polymer film deposited on the silicon structure wall during deep reactive ion etching (DRIE) may be added in some cases for smooth and uniform oxidation.

Etching the silicon oxide film 14: The silicon oxide film 14 (buried oxide) exposed by etching the silicon structure in step 7 is removed by anisotropic dry etching. At this time, care should be taken not to damage the oxide film protecting the sidewall surface of the silicon structure (see FIG. 2I).

구조물 Silicon Structure Lifting: The handling wafer is anisotropic dry etched to remove the projected portion of the handling wafer 12 in the same shape as the silicon structure (see FIG. 2J).

At this time, since the upper and lower surfaces and the side surfaces of the silicon structure are protected by the oxide film (SiO ₂ ), the silicon wafer is not damaged by anisotropic dry etching, and the etching direction of the handling wafer is shifted by 45 ° from the process crystal direction. Perfect flotation is possible.

EDP, KOH, TMAH and the like can be used as the wet chemical solution used here, and these solutions are called anisotropic silicon etching solutions because the etching rate is very different depending on the crystal direction of silicon single crystal (specified by Miller index).

In other words, as shown in FIG. 5, since all of the solutions progress slowly in the crystallization direction of the silicon single crystal, the etching speed in the {111} direction is several tens to many hundreds of times compared to the <100> or <110> directions. After a long time, all of the silicon exposed to the solution remains in the {111} direction, that is, the {111} planes of the silicon single crystal.

However, in the present invention, since the etching is terminated when the vertical depth of the handling wafer 12 is 50 μm, the <100> or <110> planes remain as they are during the etching process as before {111} planes appear, FIGS. 5 and 6. This leaves you with something like this.

Accordingly, the characteristic of the anisotropic etching is perpendicular to the (110) plane of the handling wafer as shown in FIG. 5 and the (100) plane of the wafer surface in a 45 ° tilted direction. (110) plane will exist

Since the SOI substrate used in the process according to the present invention has a 45 ° slope between the process wafer and the handling wafer as shown in FIG. 6, most of the structure is supported by the effect of being etched at the edge of the silicon structure pattern. In the case of a large area, the overlapping portions that are etched away by the etching holes as shown in the left image are generated, and as a result, the entire silicon structure is supported.

On the other hand, another method uses a conventionally sold SOI wafer (process wafer and handling wafer are already combined and the same crystal direction of the two wafers), but rotates 45 ° with respect to the crystal direction when patterning the process wafer. After the formation, after the step 5, the same result can be obtained.

However, this method has the advantage of using the wafers that are sold in the past, but since the silicon structure pattern is rotated by 45 °, the spacing of the individual cells must be widened, and as a result, the number of chips that can be manufactured on one wafer Has the disadvantage of decreasing.

산화 removes the oxide film (SiO ₂ ) surrounding the silicon structure. At this time, it may be removed by wet or dry isotropic etching (see FIG. 2K).

For example, HF or buffered HF may be used for wet isotropic etching, and dry etching using HK fume may be used.

In the method of manufacturing a silicon support structure using the SOI wafer 10 according to the present invention, the process wafer 11 is DRIE to implement a silicon structure, and then the sidewall surface of the silicon structure is protected by an oxide film (SiO ₂ ), thereby By avoiding etching of the vibrating structure, only the lower handling wafer 12 may be etched to secure a gap between the silicon structure and the lower handling wafer 12 by 50 microns or more.

As described above, according to the method of manufacturing a silicon flotation structure using a cross-bonded SOI wafer according to the present invention, the process wafer is DRIE to implement a silicon structure, and then the sidewall surface of the silicon structure is oxide film (SiO ₂ ) By protecting the structure, the gap between the silicon structure and the lower handling wafer can be secured by 50 microns or more by avoiding the etching of the upper vibration structure and etching only the lower handling wafer.

In addition, there is no room for stress because the thermal expansion coefficients of the upper silicon structure and the lower handling wafer are exactly matched. I can make it.

Claims (5)

In the method of manufacturing a silicon flotation structure using a SOI wafer that is a process wafer and a handling wafer is bonded via a silicon oxide film, Growing an oxide film on the process wafer and the handling wafer, respectively; Bonding the process wafer and the handling wafer; Adjusting the process wafer to a thickness of a silicon structure to be manufactured; Depositing a mask on an upper surface of the process wafer; Performing a photolithography process to generalize the pattern; Patterning a mask using a PR pattern; Forming a silicon structure by etching a process wafer by the patterned mask; Growing an oxide film to protect sidewall surfaces of the silicon structure; 9 steps of etching and removing the silicon oxide film exposed by the etching of the silicon structure; 10 to support the silicon structure by removing the portion projected on the handling wafer in the same shape as the silicon structure; And And a step 11 of removing the oxide film surrounding the silicon structure. The method of claim 1, wherein the bonding of the process wafer and the handling wafer is performed by tilting the crystal directions of the two wafers at a 45 ° angle in the second step. delete The method of claim 1, wherein the silicon oxide film exposed by etching the silicon structure in step 9 is removed by anisotropic dry etching. The method of claim 1, wherein the portion projected on the handling wafer in the same manner as the shape of the silicon structure in step 10 is removed by anisotropic wet etching.

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