KR20070093189A - Method of fabricating low metal electrode of mim capacitor - Google Patents

Abstract

A method for forming a lower metal electrode of an MIM capacitor is provided to reduce remarkably the generation of defects at the lower metal electrode in an ashing process by performing a heat treatment on a substrate with the lower metal electrode before forming a dielectric film. A semiconductor substrate(11) having a storage node hole(23) is provided. A conductive layer for a lower metal electrode and a buffer insulating layer are sequentially formed on the substrate. A lower metal electrode(26) is formed in the storage node hole by etching selectively the buffer insulating layer and the conductive layer. The buffer insulating layer is removed from the resultant structure by performing an ashing process on the substrate with the lower metal electrode. A cleaning process is performed on the resultant structure. A heat treatment is performed on the resultant structure.

Description

METHOD OF FABRICATING LOW METAL ELECTRODE OF MIM CAPACITOR}

1A to 1F are cross-sectional views of processes for describing a method of forming a lower metal electrode of an MI capacitor according to the present invention.

** Brief description of the main symbols in the drawing **

11. Semiconductor substrate 13. Interlayer insulating film

15. Conductive plugs 17, 21, 22. Mold Insulation Film

19. Etch stops 23. Storage node holes

26. Lower metal electrodes 27,31. Hafnium Oxide (HfO2)

29. Aluminum oxide (Al2O3) 32. Dielectric films

33,35. Upper metal electrode 37.Buffer insulating film

The present invention relates to a method of forming a capacitor, and more particularly, to a method of forming a lower metal electrode of a metal-insulator-metal capacitor capable of securing a capacitance while minimizing leakage current.

As semiconductor devices have been highly integrated, many techniques for forming capacitors have been developed. For example, as is generally known, the capacitor lower electrode is replaced with a metal film instead of the conventional polysilicon film to prevent oxidation of the capacitor lower electrode, and the dielectric film is an atomic layer in the conventional chemical vapor deposition technique. The semiconductor device has been coping with high integration by replacing it with the Atomic Layer Deposition technology.

In particular, the atomic layer deposition technique is to deposit atoms one by one, which is advantageous in terms of step coverage and particles compared to the chemical vapor deposition technique. Currently, an aluminum oxide film (Al 2 O 3) or a hafnium oxide (HfO 2) film may be used as a dielectric film of a capacitor to which the atomic layer deposition technique is applied. However, the aluminum oxide film (Al2O3) is excellent in leakage current characteristics, but the dielectric constant value is very small as 8 ~ 10 is limited to use as a single film. In addition, the HfO 2 film and the ZrO 2 film have a dielectric constant of 26 to 30, which is larger than that of the Al 2 O 3 film, but the thin film itself is crystallized at a low temperature, making it difficult to secure leakage current characteristics. Therefore, in order to compensate for these characteristics, in conventional MDL devices and memory devices, aluminum oxide (Al 2 O 3) / hafnium oxide (HfO 2) or hafnium oxide (HfO 2) / aluminum oxide (Al 2 O 3) as dielectric layers of capacitors. ) / Halfium oxide film (HfO2) and the like. That is, the aluminum oxide film (Al2O3) has excellent leakage current characteristics, but since the dielectric constant value is small, it is difficult to secure the capacitance, and therefore, a hafnium oxide film (HfO2) having a large dielectric constant value is used together.

On the other hand, the conductive film for the lower electrode of the capacitor is formed using a metal organic chemical vapor deposition (Poly Organic Chemical Vapor Deposition) technology of poor film quality. The lower electrode conductive film may be formed of a metal nitride film such as a titanium nitride film (TiN). The lower electrode conductive pattern is patterned to form a lower electrode. The surface of the lower electrode may be oxidized during O 2 ashing. Therefore, the oxygenated surface of the lower electrode is separately hydrofluoricated to remove the oxygen from the surface of the lower electrode. However, the hydrofluoric acid treatment may cause a defect in the lower electrode itself. Such defects may cause oxygen to escape from the surface of the dielectric film during deposition of the dielectric film in a subsequent process, thereby deteriorating the characteristics of the leakage current.

Therefore, before manufacturing the dielectric capacitor, before the dielectric film is formed, the process of removing defects on the surface of the lower metal electrode is separately performed to prevent the oxygen present in the dielectric film from escaping, thereby improving leakage current characteristics and power failure. Research is needed to ensure capacity.

In order to solve the above problems, an object of the present invention is to provide a method of forming a lower metal electrode of an M capacitor capable of minimizing defects on the surface of the lower metal electrode to improve leakage current characteristics and secure capacitance.

In order to achieve the above object, the present invention provides a method of forming a lower metal electrode of the M capacitor. The method provides a semiconductor substrate having storage node holes. The conductive film for the lower metal electrode and the buffer insulating film of the capacitor are sequentially formed on the substrate. The buffer insulating layer and the conductive layer for the lower metal electrode are etched to form a lower metal electrode in the storage node hole. The substrate having the lower metal electrode is ashed to remove the buffer insulating film. The substrate on which the ashing process is completed is cleaned. The cleaning substrate is subjected to heat treatment.

The ashing treatment is preferably carried out at a temperature of 100 to 150 ° C and a pressure of 0.5 to 2 torr.

Preferably, the ashing process is performed for 30 to 180 seconds.

The ashing treatment preferably flows O 2, H 2 N 2 and CF 4 gas.

The O 2 gas is preferably 1 to 6 slm, the H 2 N 2 gas is 300 to 500 sccm, and the CF 4 gas is preferably 5 to 20 sccm.

It is preferable that the ashing treatment maintains R.F.power at 500W to 2kW.

The buffer insulating film is preferably a photoresist film.

It is preferable that the said washing process uses a hydrofluoric acid solution.

The heat treatment is preferably carried out at a temperature of 450 ~ 600 ℃.

The heat treatment is preferably performed for 10 to 90 seconds.

The heat treatment is preferably maintained at a pressure of 0.1 to 760 torr.

In the heat treatment, it is preferable to flow nitrogen gas at 100 sccm to 10 slm.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed contents are thorough and complete, and that the spirit of the present invention to those skilled in the art can be sufficiently delivered. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout.

1A to 1F are cross-sectional views of processes for describing a method of forming a lower metal electrode of an MI capacitor according to the present invention.

As shown in FIG. 1A, an interlayer insulating film 13 is formed on the semiconductor substrate 11. The interlayer insulating layer 13 is patterned to form a contact hole exposing the semiconductor substrate 11, and a contact plug 15 filling the contact hole is formed. A mold insulating film 22 is formed on the substrate having the contact plug 15. The mold insulating layer 22 may be formed by sequentially stacking the lower mold insulating layer 17, the etch stop layer 19, and the upper mold layer 21 on the substrate having the contact plug 15. However, the etch stop layer 19 is not limited to the position shown in FIG. 2A and may be formed directly on the upper surfaces of the contact plug 15 and the interlayer insulating layer 13. The mold insulating layer 22 may be formed of a double layered mold insulating layer of the lower mold insulating layer 17 and the upper mold insulating layer 21, or may be formed of a single mold insulating layer. The lower mold insulating layer 17 and the upper mold insulating layer 21 preferably have an etching selectivity with respect to the etch stop layer 19. For example, when the lower mold insulating layer 17 and the upper mold insulating layer 21 are silicon oxide layers, the etch stop layer 19 may be formed of a silicon nitride layer. The mold insulating layer 22 is patterned to form a storage node hole 23 exposing an upper surface of the contact plug 15 and an upper surface of the interlayer insulating layer 13 adjacent thereto.

The lower metal electrode conductive layer 25 is formed on the substrate having the storage node holes 23. The lower electrode conductive film 25 is formed of a conductive film having excellent step coverage, less deformation during a process of forming subsequent dielectric films, and having an oxidation resistant property. For example, the lower electrode conductive layer 25 may be formed of a metal nitride layer such as titanium nitride layer TiN.

As described above, the reason for limiting the lower metal electrode conductive film 25 to a metal nitride film such as titanium nitride film (TiN) is that when a metal such as ruthenium film Ru is used, the dielectric film and the upper metal electrode in a subsequent process. This is because the electrode deformation due to grain growth and / or agglomeration may occur during the formation of the oxides, thereby increasing the leakage current flowing through the dielectric film. Therefore, it is preferable that the lower metal electrode conductive film is formed of a metal nitride film that is relatively hard and has little deformation in a subsequent process. The lower metal electrode conductive layer 25 may be formed by a metal organic chemical vapor deposition method. The metal organic vapor deposition method is to send a high vapor pressure metal organic compound vapor to the surface of the heated semiconductor substrate in the process chamber to grow a desired thin film. As such, when the titanium nitride film is formed as the conductive film for the lower metal electrode using a metal organic vapor deposition technique, TDMAT (Ti (N (CH3) 2) 4) may be used as a source material for forming the titanium nitride film. have. At this time, during the deposition process, the deposition temperature is maintained at 300 ~ 400 ℃, the pressure in the process chamber can be maintained at 0.2 to 5 Torr (Torr). After depositing the titanium nitride film, plasma may be excited in an N2 and H2 mixed gas atmosphere to remove impurities such as carbon present in the titanium nitride film. At this time, RF power can be maintained at 500 to 2 kW. This series of deposition and impurity removal processes are repeated to form the final titanium nitride film. The final titanium nitride film may be formed to a thickness of 200 to 400 kPa. Subsequently, a buffer insulating layer 27 is formed on the lower electrode layer 25. The buffer insulating layer may be a photoresist layer.

As shown in FIG. 1B, the lower metal electrode 26 is formed by chemically mechanical polishing or etching back the buffer insulating film and the conductive film for the lower metal electrode. An ashing process 41 is performed on the substrate having the lower metal electrode 26 to remove the remaining buffer insulating layer. The ashing process 41 proceeds at a temperature of 100-150 ° C. and a pressure of 0.5-2 Torr. The ashing process 41 is preferably performed for 30 to 180 seconds. The ashing process 41 flows O2, H2N2 and CF4 gas, respectively, wherein the O2 gas is 1 to 6 slm, the H2N2 gas is 300 to 500 sccm, and the CF4 gas is preferably flowed at 5 to 20 sccm. . In this case, the R.F. power may be maintained at 500W to 2kW. As a result of the ashing process 41, the remaining buffer insulating film is removed but the surface of the lower metal electrode 26 composed of the metal nitride film is oxidized by the O2 gas. That is, a large amount of oxygen atoms penetrate the surface of the lower metal electrode 26 (see part I of FIG. 1B).

As shown in FIG. 1C, a cleaning process 43 is performed on the substrate on which the ashing process is completed. The cleaning step 43 may use a hydrofluoric acid (HF) solution. As a result, oxygen atoms on the surface of the lower metal electrode 26 can be removed. However, as shown in FIG. 1C, it can be seen that defects on the surface of the lower metal electrode 26 are increased.

As shown in FIG. 1D, in order to improve defects on the surface of the lower metal electrode 26, a heat treatment process 45 is performed on the substrate on which the cleaning process 43 is completed. The heat treatment process 45 proceeds to a rapid thermal process. The heat treatment step 45 is preferably performed for 10 to 90 seconds at 450 ~ 600 ℃ temperature. At this time, the process chamber is preferably maintained at a pressure of 0.1 to 760 torr. Meanwhile, in the heat treatment step 45, nitrogen gas may flow into the process chamber at 100 sccm to 10 slm. As a result of the heat treatment process 45, as shown in FIG. 1D, the defect of the lower metal electrode 26 may be improved.

As shown in FIG. 1E, dielectric layers 32 are formed on the substrate on which the heat treatment process 45 is completed. The dielectric layers 32 may have a complex structure in which a first hafnium oxide layer (HfO 2) 27, an aluminum oxide layer (Al 2 O 3) 29, and a second hafnium oxide layer (HfO 2) 31 are sequentially stacked.

The first hafnium oxide layer (HfO 2) 27 may be formed by an atomic layer deposition method having excellent step coverage. The first hafnium oxide layer (HfO 2) 27 may be formed by repeatedly performing a source material flow process, a first purge process, a reaction gas flow process, and a second purge process. The first hafnium oxide layer HfO2 may be formed to have a thickness of 20 to 30 kPa.

Looking at the formation process of the first hafnium oxide (HfO2) 27 in detail as follows. The source material flow process uses TEMAH (Tetra EthylMethyl Amine Hafnium, Hf (NC2H5CH3) 4) as a source material, and may be performed by flowing the TEMAH source material for 0.1 to 15 seconds. In this case, the deposition temperature may be maintained at 250 to 350 ° C. The first purge process may be performed by flowing a purge gas to the substrate on which the source material flow process is completed. In this case, the purge gas may use N 2 gas. In addition, the purge process may be performed by flowing the purge gas for 0.1 seconds to 10 seconds. As a result, impurities in the film may be removed through the first purge process. The reaction gas flow process reflows the O 3 gas into the reaction gas for 0.1 to 15 seconds. The second purge process removes impurities in the film by flowing purge gas for 0.1 to 10 seconds to the substrate on which the reaction gas flow process is completed. The purge gas may be an N 2 gas.

After forming the first hafnium oxide layer (HfO2) 27, in order to prevent crystallization of the first hafnium (HfO2) 27, an aluminum oxide layer on the substrate having the first hafnium oxide layer (HfO2) 27 (29) is formed. That is, the aluminum oxide film (Al 2 O 3) 29 corresponds to a crystallization suppression layer.

The aluminum oxide layer (Al 2 O 3) 29 may be formed to have a thickness of 5˜10 μm by repeatedly performing a source material flow process, a first purge process, a reaction gas flow process, and a second purge process.

The source material flow process may flow the TMA (TriMethyl Aluminum) source material for 0.1 to 10 seconds. The first purge process may be performed by flowing a purge gas to the substrate on which the source material flow process is completed. The first purge process may be performed by flowing N2 purge gas for 0.1 seconds to 10 seconds. As a result, impurities in the film may be removed through the first purge process. Subsequently, the reaction gas flow process flows the O 3 reaction gas for 0.1 to 10 seconds. The second purge process may be applied in the same manner as the first purge process.

A second hafnium oxide layer (HfO 2) 31 is formed on the substrate having the aluminum oxide layer (Al 2 O 3) 29 to complete the process of forming the dielectric layers 32. The process of forming the second hafnium oxide layer (HfO 2) 31 may be applied in the same manner as the process of forming the first hafnium oxide layer (HfO 2) 27.

As shown in FIG. 1F, an upper metal electrode film, that is, an upper metal electrode conductive film 36, is formed on a substrate having the dielectric films 32. The upper electrode conductive layer 36 may be formed of a first metal nitride layer 33 such as a titanium nitride layer (TiN) by applying a metal organic vapor deposition technique in the same manner as the lower electrode conductive layer. In this case, since the first metal nitride film 33 is formed by a metal organic vapor deposition technique, step coverage is poor. Therefore, when the contact is formed on the upper metal electrode in a subsequent process, there is a fear that contact failure occurs. In order to compensate for this, the upper electrode conductive layer 36 is formed on the first metal nitride layer 33 by applying a physical vapor deposition technique to a second metal nitride layer such as a titanium nitride layer (TiN). It is also possible to form 35 by laminating. As a result, by forming the second metal nitride film 36 by a physical vapor deposition technique, a high quality thin film having excellent film quality can be obtained.

According to the present invention, in forming a lower metal electrode of an M capacitor, prior to forming a dielectric film, heat treatment may be performed on a substrate having the lower metal electrode to reduce defects on the surface of the lower metal electrode. That is, by performing heat treatment on the substrate having the lower metal electrode, defects generated on the surface of the lower metal electrode during the ashing process can be reduced. Therefore, the oxygen present in the dielectric layer may be prevented from escaping, thereby improving leakage current characteristics and securing capacitance.

Claims (12)

Providing a semiconductor substrate having storage node holes, A conductive film for the lower metal electrode of the capacitor and a buffer insulating film are sequentially formed on the substrate, Etching the buffer insulating film and the conductive film for the lower metal electrode to form a lower metal electrode in the storage node hole; The substrate having the lower metal electrode is ashed to remove the buffer insulating film, Cleaning the substrate on which the ashing process is completed, And forming a heat treatment on the cleaned substrate. The method of claim 1, wherein the ashing process is performed at a temperature of 100 ~ 150 ℃ and a pressure of 0.5 to 2 torr. The method of claim 1, wherein the ashing process is performed for 30 to 180 seconds. The method of claim 1, wherein the ashing process flows O2, H2N2 and CF4 gas. 5. The method of claim 4, wherein the O2 gas flows from 1 to 6 slm, the H2N2 gas flows from 300 to 500 sccm, and the CF4 gas flows from 5 to 20 sccm. The method of claim 1, wherein the ashing process maintains the R. F. power of 500W to 2kW. The method of claim 1, wherein the buffer insulating film is a photoresist film. The method of claim 1, wherein the cleaning process uses a hydrofluoric acid solution. The method of claim 1, wherein the heat treatment is performed at a temperature of 450 ~ 600 ℃. The method of claim 1, wherein the heat treatment is performed for 10 to 90 seconds. The method of claim 1, wherein the heat treatment maintains a pressure of 0.1 to 760 Torr. 2. The method of claim 1, wherein the heat treatment flows nitrogen gas at 100 sccm to 10 slm.

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