KR20070018068A - Timing generator and semiconductor testing apparatus - Google Patents

Abstract

The pattern dependency jitter is reduced to reduce the timing error of the timing pulse signal at the timing generator. The timing generator 20 is an output terminal side of the flip-flop 31 in the signal input / output circuit 30 having a flip-flop (reference signal delay means) 31 which outputs an output signal in accordance with the input timing of the clock signal. Instead, a delay circuit (variable delay means, clock signal delay circuit) 32 is provided on the input terminal side of the clock signal, and a delay is applied to the clock signal. Instead of the clock signal delay circuit 32, a phase locked loop circuit 34 can be provided.

Pattern-dependent jitter, timing pulse signals, flip-flops, clock signals, data retention circuits, timing errors

Description

TIMING GENERATOR AND SEMICONDUCTOR TESTING APPARATUS}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timing generator for generating a timing pulse signal in order to take a test cycle signal or a test timing of the entire test apparatus, and a semiconductor test apparatus having the same.

Before explaining this invention, the outline of the conventional semiconductor test apparatus is demonstrated with reference to FIG.

As shown in FIG. 5, the semiconductor test apparatus 1 that tests the semiconductor integrated circuit (DUT: device under test) 10 is a main configuration, and performs control of the entire semiconductor test apparatus 1. A test processor (not shown), a pattern generator 11 for generating a test pattern or an expected value pattern, or the like, and a test pattern from the pattern generator 11 is shaped into a test signal waveform to the DUT 10 through the driver 14. The test result sent from the DUT 10 through the waveform shaper 12 and the comparator 15 to be sent to the circuit is compared with the expected value pattern from the pattern generator 11 to detect a coincidence and inconsistency, and the DUT 10 is detected. And a timing comparator 13 for generating a timing pulse signal and supplying the waveform comparator 12, the comparator 15, and the pattern comparator 13 to timing the test. Doing.

Among these, as shown in FIG. 6, the timing generator 20 includes a cycle generator 21 for determining the entire test cycle of the semiconductor test apparatus 1, and each pin of the LSI of the DUT 10. The pattern comparator 13 has a plurality of delay generators 22-1 to 22-n for giving a predetermined timing.

The delay generators 22-1 to 22-n calculate the singular data of the pattern period based on the pattern period data R1, synchronize with the period start data from the input terminal a0, and generate the singular data. The periodic calculation means 23 for sending out, the delay calculation means 24 for adding the singular data and the set delay data R2 from the periodic calculation means 23 to output integer data and the singular data, and the delay calculation Reference signal delay means 310 for delaying the reference signal (reference clock) from the period generator 21 by the constant data from the means 24, and the reference signal from the reference signal delay means 310 is delayed. The variable delay means 320 which delays by the single-stage data from the calculating means 24, and outputs it as a timing pulse signal (for example, refer Unexamined-Japanese-Patent No. 11-125660).

With such a configuration, the timing generator 20 can generate a timing pulse signal with a desired time delay and send it to the pattern comparator 13 or the like.

In addition, as shown in FIG. 6, the part which includes the period calculating means 23 and the delay calculating means 24, and calculates the delay time of a reference signal is called delay time calculating means A. As shown in FIG. In addition, a portion including the reference signal delay means 310 and the variable delay means 320, and delaying the reference signal is referred to as a signal input / output circuit 300.

However, the variable delay means 320 provided in the delay generators 22-1 to 22-n of the conventional timing generator 20 has a reference output from the reference signal delay means 310 as a target to which the delay is applied. Since it is a signal, it is in a situation where pattern-dependent jitter (short time jitter or thermal drift jitter) is likely to occur, and in that state, a timing error occurs in the timing pulse signal output from the timing generator 20. A problem occurred.

A circuit diagram for explaining how this pattern dependent jitter occurs is shown in FIG. FIG. 7 is a diagram showing the circuit configuration of the signal input / output circuit 300 which outputs the data data Data to the outside after synchronizing with the clock signal Clock and delaying the predetermined time.

The signal input / output circuit 300 will be further described by inputting the input data signal (the conventional timing generator 20 (FIG. 6) from the cycle generator 21 to the delay generators 22-1 to 22-n). A flip-flop 310 (corresponding to the reference signal delay means 310 in Fig. 6) for outputting the losing reference signal by the input timing of the clock signal (clock for calculating the output timing), and the flip-flop It is connected to the output terminal side of 310, and has the delay circuit 320 (corresponding to the variable delay means 320 in FIG. 6) which delays the output data signal for a predetermined time, and then outputs it externally.

If the data signal is a random pattern (a pattern in which the pulse wave is randomly generated) and the clock signal is a continuous pattern (a pattern in which the pulse wave is continuously generated at a constant period), the delay circuit 320 is a random pattern. It is connected to the path (the random pattern pass path, C of FIG. 7) through which a pulse wave passes, and is in a state where pattern dependency jitter tends to occur in a random pattern pass path.

Here, the pattern dependent jitter includes short term jitter and thermal drift jitter.

First, short-term jitter will be described. Short-term jitter means that one edge (notice edge) is shaken by the influence of a past edge when a plurality of pulse waves are generated.

For example, as shown in Fig. 8A, when pulse waves are continuously generated, the edges of the past in the pulse wave having the edge of interest (? 8 in the pulse wave having an edge with an edge, FIG. 8 (1)), and past edges other than the pulse wave having each edge (the edge with an edge with a cross) in the past pulse wave. The edge to which (circle) is attached and (2) and (3) of FIG. 8 affect.

On the other hand, as shown in Fig. 8B, when pulse waves are generated singly, the edges of interest in the pulse waves having the edges of interest are mainly influenced by the edges of interest. ((1) of FIG. 8).

In this case, another pulse wave may be randomly generated in the near time in the past as seen from the pulse wave having the edge of interest. For example, when the pulse wave is generated in the near time in the past, FIG. As in (2) of (a), the edge of interest is affected from each edge of the past pulse wave. On the other hand, when a pulse wave does not generate | occur | produce at that time, it is not affected by it (refer to (2) and (3) of FIG. 8B).

Here, the edges influencing the edge of interest when the pulse waves are continuously generated are compared with the edges influencing the edge of the interest when the pulse wave is generated singly.

First, all of the past edges in the pulse wave having the edge of interest have a common influence ((1) in FIG. 8A and (1) in FIG. 8B).

Next, the influence of the edge of the pulse wave generated in the past more than an arbitrary time from the point of time of the occurrence of the edge of interest has an influence, but can be ignored because it is very small ((3) of FIG. 8A and FIG. 8). (B) to (3)).

In the case where the pulse wave is continuously generated for each edge of the pulse wave generated in the past within a time range close to the point of time of the pulse wave having the edge of interest, and the pulse wave is generated singly. The effect is different.

For example, when pulse waves are generated continuously, as shown in Fig. 8A, each edge of the pulse wave generated in the past has a great influence on the edge of interest (Fig. 8). (2) of (a).

On the other hand, when a pulse wave is generated by a single shot, there may be a case where the pulse wave has occurred in the past and may not generate | occur | produce in the time range near the time of generation | occurrence | production of the pulse wave which has an edge of interest.

When pulse waves have been generated in the past, as in the case where pulse waves are continuously generated, they have a great influence on the edge of interest. On the other hand, when no pulse wave has been generated in the past, since no pulse wave exists, as shown in Fig. 8B, the edge of interest is not affected.

From this, the influence of the edge of interest when the pulse waves are generated continuously and the effect of the edge of attention when the pulse waves are generated singly are in a time range close to the point of occurrence of the pulse wave having the edge of interest. It depends on whether or not pulse wave is generated in the past.

In other words, when pulse waves are generated continuously, pulse waves always occur in the past within a time range close to the point of time of the pulse wave having the edge of interest, and the influence of the edge of interest from these other edges is always constant. do. For this reason, in the path through which such continuous pulse waves pass (continuous clock pass path), short-term jitter need not be considered.

On the other hand, in the case where the pulse wave is generated singly, the degree of influence varies depending on whether or not the pulse wave has been generated in the past within a time range close to the point of time of generation of the pulse wave having the edge of interest. That is, the pattern affected by the past edge (pattern shown in Fig. 8C) and the pattern hardly affected by the past edge (pattern shown in Fig. 8D) occur randomly. By doing so, the influence is not constant. For this reason, in the path (random pattern passing path) through which a single pulse wave passes, the influence of the edge of interest changes, resulting in pattern dependent jitter (short-term jitter).

Next, the thermal drift jitter will be described. Thermal drift jitter means fluctuations in a waveform under the influence of temperature change.

The delay circuit 320 shown in FIG. 7 has any number (usually tens to hundreds) of inverters 321 as shown in FIG. 9, for example. By increasing the number of the inverters 321, the delay time can be increased.

In the inverter 321, as shown in FIG. 9, a transistor 322 is provided. In this transistor 322, a temperature change occurs according to a pattern of generating a pulse wave, and thus V _BE (base to emitter voltage) is provided. ) Fluctuates.

For example, in the continuous clock pass path, since the pulse waves are generated continuously, the temperature change is almost constant. On the other hand, in a random pattern path, since a pulse wave generate | occur | produces by a single shot, temperature change will not become constant. For this reason, V _BE fluctuates, the timing which outputs a signal changes, and it becomes pattern dependent jitter (thermal drift jitter). In particular, as the number of inverters 321 increases, the thermal drift jitter also increases.

As described above, in the conventional signal input / output circuit, there was a situation in which short-term jitter and thermal drift jitter may occur in a random pattern pass path. For this reason, in the timing generator provided with the signal input / output circuit, a timing error occurred in the output timing pulse signal. And in the whole semiconductor test apparatus, the problem which the shift | offset | difference to a test timing generate | occur | produced caused the timing error.

In addition, as shown in FIG. 9, the delay circuit 320 usually includes a plurality of inverters 321. For this reason, as the inverter 321 goes to the rear end, a pattern-dependent jitter is added, resulting in a larger timing error of the timing pulse signal.

SUMMARY OF THE INVENTION The present invention has been proposed in order to solve the problems of the prior art as described above, and reduces the pattern dependency jitter, reduces the timing error of the timing pulse signal in the timing generator, and improves the test timing in the semiconductor test apparatus. An object of the present invention is to provide a timing generator and a semiconductor test apparatus that can suppress occurrence of misalignment.

<Start of invention>

The timing generator according to the present invention is a timing generator that delays a reference signal by a predetermined time and outputs it as a timing pulse signal. The timing generator includes delay time calculating means for calculating a delay time applied to the reference signal, and delay calculated by the delay time calculating means. A data input / output circuit for delaying the reference signal over time, the signal input / output circuit inputs a reference signal and outputs a reference signal based on the input timing of the clock signal; The clock signal delay circuit is configured to delay the input timing of the clock signal in the circuit based on the delay time.

With such a configuration, the timing generator can eliminate the delay circuit of the random pattern pass path because the delay circuit is connected to the input terminal side to which the clock signal is input, not to the output terminal side of the data holding circuit. Therefore, the pattern dependency jitter can be reduced.

In the timing generator of the conventional semiconductor test apparatus, a delay circuit (for example, variable delay means) is connected to the output terminal side of a data retention circuit (for example, a reference signal delay means including a flip-flop). Since the output terminal side of the data holding circuit is a random pattern pass path through which a randomly generated output signal (for example, a reference signal) passes, it was necessary to consider the pattern dependent jitter generated when a delay circuit was connected to this path. .

On the other hand, since the input terminal side to which the clock signal is input from the data holding circuit is a continuous clock pass path through which clock signals continuously generated at a constant cycle pass, a delay circuit (clock signal delay circuit) is connected to this path to generate a random signal. Pattern dependent jitter can be reduced by eliminating the delay circuit of the pattern pass path.

In addition, the delay circuit connected to the output terminal side of the data holding circuit serves to delay the output signal, but also delays the output signal even if it delays the clock signal instead of the output signal. For this reason, the delay circuit connected to the input terminal side of the clock signal can play a role of delaying the output signal.

In addition, since the delay circuit is not connected to the output terminal side of the data holding circuit but is connected to the input terminal side of the clock signal, the random pattern pass path can be shortened.

Therefore, in the present invention, by delaying the clock signal by connecting a delay circuit to the input terminal side to which the clock signal is input, rather than the output terminal side of the data holding circuit, the output signal can be delayed by a predetermined time, thereby providing a random pattern. Pattern dependent jitter can be reduced by eliminating the delay circuit of the pass path.

By reducing the pattern dependency jitter, the timing error of the timing pulse signal in the timing generator provided with the signal input / output circuit can be reduced, and the occurrence of misalignment of the test timing in the semiconductor test apparatus can be suppressed. .

Further, in the present invention, since the pattern dependency jitter is reduced by connecting the delay circuit to the continuous clock pass path, the problem that the pattern dependency jitter is increased because there are multiple stages of the inverter can also be solved. In other words, the larger the number of inverters the delay circuit has, the greater the effect when the pattern dependency jitter is reduced.

Moreover, the timing generator of this invention is set as the structure provided with the data delay circuit which gives a delay to the reference signal input into a data holding circuit.

With this configuration, the timing generator can delay the reference signal in accordance with the clock signal delayed by the clock signal delay circuit.

In addition, the timing generator of this invention is comprised with the phase shift circuit instead of a clock signal delay circuit.

With this configuration, the timing generator can connect a phase shift circuit using a phase locked loop circuit (PLL circuit) to the continuous clock pass path to delay the output signal to a desired time, and even in this manner, the random pattern pass path side By eliminating the delay circuit, the pattern-dependent jitter can be reduced.

The timing generator of the present invention is configured such that the data holding circuit includes a flip flop.

With this configuration, the timing generator including the signal input / output circuit configured by the flip-flop and the timing generator including the signal input / output circuit also connects a clock signal delay circuit to the continuous clock pass path to form a random pattern pass path. Since it can shorten, pattern dependent jitter can be reduced. The data holding circuit is a circuit for holding input data up to an arbitrary timing and then outputting the data. The circuit includes a latch circuit or the like in addition to a flip-flop.

Further, the semiconductor test apparatus of the present invention includes a pattern generator for generating a test pattern and an expected value pattern, a waveform shaper for waveform shaping the test pattern and supplying the test pattern to a device under test, and a test result and a pattern generator from the device under test. A semiconductor test apparatus comprising a pattern comparator for comparing the expected value pattern of the device under test and determining the quality of the device under test, and a timing generator for supplying a timing pulse signal to the waveform shaper to take a test timing. It is set as the structure which consists of a timing generator described in the claim.

With such a configuration, the semiconductor test apparatus can reduce the pattern dependency jitter, thereby reducing the timing error of the timing pulse signal in the timing generator, thereby suppressing the occurrence of the deviation of the test timing in the semiconductor test apparatus. have.

According to the present invention as described above, the phase shift circuit using the delay circuit or the PLL circuit is connected to the input terminal side to which the clock signal is input, not the output terminal side of the data holding circuit (for example, flip-flop). Therefore, the delay circuit of the random pattern pass path can be eliminated, and the pattern dependency jitter can be reduced.

As a result, in the timing generator, the timing error of the timing pulse signal can be reduced, and in the semiconductor test apparatus, the occurrence of the deviation of the test timing can be suppressed.

1 is a circuit configuration diagram showing a configuration of a timing generator of the present invention.

Fig. 2 is a circuit diagram showing the construction of the signal input / output circuit of the present invention.

3 is a circuit diagram showing another configuration of the signal input / output circuit of the present invention.

4 is a circuit diagram illustrating the configuration of a phase shift circuit using a PLL circuit.

5 is a circuit diagram illustrating a schematic configuration of a general semiconductor test apparatus.

6 is a circuit configuration diagram showing a configuration of a conventional timing generator.

7 is a circuit configuration diagram showing a configuration of a conventional signal input / output circuit.

FIG. 8A is a waveform diagram showing how an edge of interest is affected by another edge when pulse waves are continuously generated, and FIG. 8B is a case where pulse waves are generated by a single shot. Fig. 8C is a waveform diagram showing how the edge of attention is affected by another edge, and Fig. 8C is a waveform diagram showing how the edge of interest is greatly affected by another edge. Waveform diagram showing how an edge is not affected by other edges.

9 is a circuit diagram showing a circuit configuration of an inverter provided in a delay circuit.

<Best mode for carrying out the invention>

EMBODIMENT OF THE INVENTION Hereinafter, preferred embodiment of the timing generator and semiconductor test apparatus which concern on this invention is described with reference to drawings.

First, an embodiment of a timing generator and a semiconductor test apparatus of the present invention will be described with reference to FIGS. 1 and 2.

1 is an electronic circuit diagram showing a circuit configuration of a timing generator of the present invention, and FIG. 2 is a circuit configuration of a signal input / output circuit.

The timing generator 20 shown in FIG. 1 is provided in the semiconductor test apparatus 1 similar to the conventional one shown in FIG.

The semiconductor test apparatus 1 is a test apparatus that determines whether the device under test 10 (DUT) is passed or not, and as shown in FIG. 5, the main components include a pattern generator 11 and a waveform shaper 12. And the pattern comparator 13, the driver 14, the comparator 15, the fail analysis memory 16, the input voltage generator 17, the device power supply 18, and the comparison voltage generator 19 ) And a timing generator 20.

Here, as shown in FIG. 1, the timing generator 20 includes a cycle generator 21 and delay generators 22-1 to 22-n, and a delay generator 22-1. 22-n includes a cycle calculating means 23, a delay calculating means 24, and a signal input / output circuit 30a.

In addition, in FIG. 1, although the period calculating means 23 and the delay calculating means 24 are provided in delay generation parts 22-1 to 22-n, these period calculating means 23 and the delay calculating means 24 are shown. Is not limited to the delay generators 22-1 to 22-n, but may be provided to the cycle generator 21.

In addition, in this embodiment, as shown in FIG. 1, it is called delay time calculation means A including the period calculation means 23 and the delay calculation means 24. As shown in FIG.

As shown in FIG. 1, the signal input / output circuit 30a includes a reference signal delay means 31a, a variable delay means 32a, and a data delay means 33a.

Although the signal input / output circuit 30a having such a structure is a circuit which outputs the reference signal by delaying the predetermined time, the signal input / output circuit 30 which makes this signal input / output circuit 30a one embodiment is shown in FIG. As described above, the flip-flop 31, the clock signal delay circuit 32, and the data delay circuit 33 are provided.

The flip-flop (data retention circuit) 31 outputs the input data signal Data in accordance with the input timing of the clock signal Clock. This flip-flop 31 corresponds to the reference signal delay means 31a in FIG.

The clock signal delay circuit 32 is connected to the input terminal side of the clock signal in the flip-flop 31 and delays the clock signal.

The path to which the clock signal delay circuit 32 is connected is a continuous clock pass path through which a clock signal composed of pulse waves continuously generated at a predetermined cycle passes. Thus, by connecting the delay circuit for delaying the output signal of the flip-flop 31 to the input terminal side of the clock signal instead of the output terminal side of the flip-flop 31, pattern-dependent jitter can be reduced. The clock signal delay circuit 32 corresponds to the variable delay means 32a in FIG. 1.

The data delay circuit 33 is a delay circuit requiring connection by moving the clock signal delay circuit 32 from the output terminal side in the flip-flop 31 to the input terminal side of the clock signal. That is, since the clock signal input timing of the clock signal is delayed minutely by the clock signal delay circuit 32, it is for fitting the data signal to the input timing of the clock signal. This data delay circuit 33 corresponds to data delay means 33a in FIG. 1.

When the signal input / output circuit 30 is configured in such a manner, the clock signal delay circuit 32 is not an output terminal side (random pattern pass path) on the flip-flop 31, but an input terminal side of the clock signal (continuous clock). Since it is connected to the pass path), it is not necessary to provide a delay circuit for timing setting in the random pattern pass path (C of FIG. 2), and the pattern dependency jitter can be reduced.

Thereby, in the timing generator provided with this signal input / output circuit, the timing error of a timing pulse signal can be reduced, and the semiconductor test apparatus provided with this timing generator can suppress generation | occurrence | production of a test timing shift.

Incidentally, in the above-described signal input / output circuit 30, the clock signal delay circuit 32 is used as a means for delaying the clock signal. As shown in FIG. 3, instead of the clock signal delay circuit 32, A phase shift circuit 34 using a phase locked loop circuit (PLL (Phase Locked Loop) circuit) may be provided.

The PLL circuit is an electronic circuit that matches the frequency of the input signal or the reference frequency and the output signal. The PLL circuit is provided with a phase shift circuit 34 using the PLL circuit to detect a phase difference between the input signal and the output signal, and By controlling the loop of the control oscillator or the circuit, it is possible to transmit a signal of exactly synchronized frequency.

The internal structure of this phase shift circuit 34 is shown in FIG.

As shown in FIG. 4, the phase shift circuit 34 includes a phase detector 34-1, a voltage controlled oscillator 34-2, and a phase shift amount generator 34-3.

The phase detector (PD) 34-1 outputs the phase difference between the reference frequency signal and the output signal of the voltage controlled oscillator 34-3 in the form of a voltage (or current).

The voltage controlled oscillator (VCO) 34-2 is an oscillator that changes frequency by voltage.

The phase shift amount generator 34-3 generates a voltage (or current) for generating a predetermined amount of clock delay in the voltage (or current) output from the phase detector 34-1.

By connecting the phase shift circuit 34 having such a configuration to the input terminal side of the clock signal of the flip-flop 31, the delay circuit of the random pattern pass path can be eliminated, and the output is generated without generating pattern dependency jitter. A predetermined delay amount can be given to the signal.

As mentioned above, although preferred embodiment of the signal input / output circuit, the timing generator, and the semiconductor test apparatus was demonstrated, the signal input / output circuit, the timing generator, and the semiconductor test apparatus which concern on this invention are not limited only to embodiment mentioned above, It goes without saying that various modifications can be made within the scope of the invention.

For example, in the above embodiment, the signal input / output circuit has a circuit configuration having a flip-flop and a delay circuit. However, the signal input / output circuit is not limited to the case where the flip-flop and the delay circuit are provided, and other circuit elements are provided. It may be.

In addition, although the flip-flop provided in the signal input / output circuit is only one in FIG. 2 etc., it is not limited to one but can be provided in multiple numbers. In this case, the clock signal delay circuit may be connected to the clock input terminal of one flip-flop or may be connected to the clock input terminals of two or more flip-flops.

Since this invention is invention regarding the timing generator which can reduce the timing error of a timing pulse wave, it can be used suitably for the apparatus, apparatus, etc. which perform predetermined | prescribed operation | movement using a timing pulse wave.

Claims (5)

A timing generator for delaying a reference signal for a predetermined time and outputting the same as a timing pulse signal, Delay time calculating means for calculating a delay time given to said reference signal; A signal input / output circuit for delaying the reference signal in accordance with the delay time calculated by the delay time calculating means, The signal input / output circuit, A data holding circuit which inputs the reference signal and outputs the reference signal based on an input timing of a clock signal; A clock signal delay circuit for delaying the input timing of the clock signal in the data retention circuit based on the delay time A timing generator, characterized in that having a. The method of claim 1, And a data delay circuit for giving a delay to the reference signal input to the data holding circuit. The method according to claim 1 or 2, And a phase shift circuit in place of the clock signal delay circuit. The method according to claim 1 or 2, And the data retention circuit comprises a flip-flop. A pattern generator for generating a test pattern and an expected value pattern, a waveform shaper for waveform shaping the test pattern and supplying the test pattern to a device under test, a test result from the device under test and an expected value pattern from the pattern generator A semiconductor test apparatus comprising: a pattern comparator for determining whether the device under test is passed; and a timing generator for supplying a timing pulse signal to the waveform shaper to take test timing; The said timing generator consists of the timing generator of Claim 1 or Claim 2 characterized by the above-mentioned.

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