JP2001111415A - Pll circuit and semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a PLL circuit capable of improving the accuracy of phase synchronization of a PLL and suppressing the reduction of phase comparison accuracy due to the dispersion of manufacture and a wiring state in an LSI. SOLUTION: The PLL circuit is provided with 1st and 2nd variable delay elements whose delay time can be variably set and which are inserted into a route 1 from a reference clock input terminal up to the input terminal of a phase comparator in the PLL circuit and a route 2 from an input terminal for feedback inputting a clock outputted from the PLL circuit up to the input terminal of the phase comparator respectively, and with an automatic phase error correction means which sets the delay time of the 1st and 2nd variable delay elements on the basis of the measured result of a delay time difference between routes 3, 4 equivalent to the routes 1, 2 and sets the delay time of the 1st and 2nd routes to a mutually equal value.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a clock control circuit for a semiconductor integrated circuit, and more particularly to a circuit for automatically correcting a phase error of a phase comparator of a PLL circuit.

[0002]

2. Description of the Related Art A PLL (Phase Locked Loop) circuit is used as one of clock synchronizing circuits for synchronizing the phases of a clock supplied from the outside and an internal clock. FIG. 3 is a diagram schematically showing a configuration of a conventional PLL circuit provided in a semiconductor integrated circuit. Referring to FIG. 3, a PLL circuit 30 in each LSI
2 is a clock from the outside of the LSI 301 and the LSI 301
Internal Clock Tree Synth
(hereinafter, abbreviated as “CTS”) by synchronizing the phases of the clocks of the flip-flops 313 to 315, etc., thereby realizing clock synchronization among a plurality of LSIs arranged on a board (not shown). Have been.

The flip-flop 315 in the LSI 301
The determination as to whether or not the phase of the internal clock supplied to the clock input terminal FFCLK is synchronized with the phase of the clock external to the LSI 301 is made by the phase comparator 30 of the PLL circuit 302.
In step 3, the phase of the external clock is compared with the phase of the internal clock, and the internal clock output from the voltage controlled oscillator (VCO) is fed back to the phase comparator 303 via a loop filter provided at the subsequent stage of the phase comparator 303. By inputting, a phase synchronization operation is performed.

In order to accurately determine the phase comparison, two paths to the phase comparator 303, that is, from the external input terminal RCLK of the LSI 301 to the PLL 302 through the interface (I / F) buffer 304.
The delay time of the path 1 of the reference clock reaching the first input terminal of the phase comparator 303 and the delay time of the path 2 of the feedback clock from the input terminal CLKI of the PLL 302 to the second input terminal of the phase comparator 303 of the PLL 302 It is assumed that they are the same, and matching is performed so that they are the same when designing the PLL circuit.

[0005]

However, this 2
Since the adjustment of the delay values of the two paths 1 and 2 is performed at the time of PLL design, the delays of the paths 1 and 2 may deviate from the same value due to manufacturing variations during mass production of the LSI.

When designing the LSI at the chip level, the delay value from the outside of the LSI 301 to the phase comparator 303 may fluctuate depending on the wiring state of the LSI 301.

At present, no measures have been taken in the input path of the phase comparator of the PLL to correct manufacturing variations of LSIs and deviations of delay values due to wiring conditions inside the LSI. It is a fact. For this reason,
It also causes malfunctions and failures of electrical equipment.

As a prior art of the PLL circuit, for example, Japanese Patent Application Laid-Open No. Hei 10-093429 proposes a circuit configuration for controlling a delay circuit in a PLL to reduce a phase error when an internal clock and an external clock match. ing. FIG. 4 is a diagram showing a configuration of a PLL circuit described in Japanese Patent Application Laid-Open No. 10-093429. Referring to FIG. 4, an external clock CLKSYS becomes an internal clock CLKB via a delay circuit 21 and a clock buffer 22, and a phase comparator 23 detects a phase difference between the two clocks. The counter 24 changes the count value based on the comparison result of the phase comparator 23, and the least significant bit of the count value controls on / off of the transmission gates 27-0 and 27-1 and the least significant bit of the count value. The other bits are input to the decoder 25, and the output of the decoder 25 controls on / off of the transmission gates 26-0 to 26- (N-1).

Comparing the configuration shown in FIG. 4 with the circuit configuration shown in FIG. 3, the path from the external terminal CLKSYS to the phase comparator 23 corresponds to the path 1, and the path from the terminal CLKI to the phase comparator 23 is the path 2 Is equivalent to With respect to the path 1 and the path 2, no means is provided for correcting deviations in delay values due to variations in the manufacture of individual LSIs and wiring conditions inside the LSIs.

[0010] In designing the PLL, matching the delay values of these two paths requires enormous energy such as securing simulation resources, which leads to an increase in design cost.

[0011] For example, Japanese Patent Laid-Open No. 2-105910 discloses a plurality of clock adjusting means for forming clocks coincident with each other based on frequency information and phase information supplied from a clock generation source. A comparison clock (RE) having phase information from a clock source
F) and a phase comparison means for detecting a phase difference between the feedback signal (FB) and a clock (MC) according to the phase difference.
A configuration having a variable delay means for delaying K) is disclosed. In this Japanese Patent Laid-Open Publication No. 2-105910, the comparison clock (REF) input to the phase comparison means is also disclosed.
No consideration is given to the adjustment of the delay time between the feedback signal (FB) and the feedback signal (FB).

Accordingly, the present invention has been made in view of the above-mentioned problems, and an object of the present invention is to improve the phase synchronization accuracy of a PLL and to improve the phase comparison accuracy due to manufacturing variations and wiring conditions inside an LSI. And a semiconductor integrated circuit device including the PLL circuit.

[0013]

In order to achieve the above object, the present invention provides a first path from a reference clock input terminal to a first input terminal of a phase comparator of a PLL circuit, and an output from the PLL circuit. The PL for feeding back a clock
First and second variable delay elements each having a variably set delay time are inserted into a second path from an input terminal of an L circuit to a second input terminal of the phase comparator, and And the delay time of the first and second variable delay elements based on the measurement result of the difference between the delay times of the third and fourth paths for measuring the delay time including the paths equivalent to the second path and the second path, respectively. A phase error automatic correcting means for setting the delay time of the first path and the delay time of the second path to be equal to each other.

[0014]

Embodiments of the present invention will be described. The present invention, in one of its preferred embodiments,
PL with reference clock input from external terminal as input
In a semiconductor integrated circuit device for generating an internal clock by an L circuit, a first signal from the external terminal for inputting the reference clock to a first input terminal of a phase comparator of the PLL circuit.
And a second path from an input terminal of the PLL circuit, which inputs a clock output from the PLL circuit as a feedback clock (feedback signal), to a second input terminal of the phase comparator, respectively. First and second variable delay elements whose time can be set variably are inserted, and delay times in third and fourth paths for delay time measurement including paths equivalent to the first and second paths, respectively. Phase error automatic correcting means for setting the delay times of the first and second variable delay elements based on the measurement result of the difference between the first and second variable delay elements and making the delay times of the first and second paths equal. The phase error automatic correction means includes: a multiplied clock generator for generating a clock obtained by multiplying the reference clock input from the external terminal; and a delay time of the third path by the multiplied clock output from the multiplied clock generator. And a counter that counts the difference between the delay times of the fourth path, and sets the delay times of the first and second variable delay elements based on the count value of the counter. The delay time of the second path is made equal.

In one embodiment of the present invention, in the first path, the reference clock input terminal is connected to an interface buffer and a first variable delay element of the PLL circuit via the first variable delay element. And an input terminal of the PLL circuit for feedback-inputting a clock output from the PLL circuit through the second variable delay element in the second path. The third path is connected to a second input terminal of the device and outputs the clock output from the multiplied clock generator from the first delay element and the first interface buffer to the outside of the semiconductor integrated circuit device. The output path and the output clock are looped back, fetched into the semiconductor integrated circuit device via the second interface buffer, and Through element consists feedback path to be input to the multiplication clock generator, the fourth path, the clock output from the multiplied clock generator, the third
A transmission path wired to the end of the PLL circuit via the delay element of the above, and a feedback path which is turned back at the end and input to the multiplied clock generator via the fourth delay element. And a clock output from the multiplied clock generator to the fourth path, and based on a time difference between the clocks returned to the feedback path of the third path and the fourth path, the third and fourth clocks are output. The difference in delay time of the path is measured by the counter, and based on the count value of the counter,
The delay time of the first and second variable delay elements is set.

In one embodiment of the present invention, the automatic phase error correcting means is configured to detect the phase error based on a measurement result of the delay time of the first path and the second path at power-on or at reset. A correction process for equalizing the delay times of the first and second paths is performed.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing the configuration of one embodiment of the present invention. The present invention suppresses a reduction in phase comparison accuracy due to manufacturing variations and wiring conditions inside an LSI.

Referring to FIG. 1, when the power of the LSI 101 is turned on or when the reset is executed, the clock multiplied by the multiplied clock generator 105 in the PLL 102 is used.
Two paths to the phase comparator 103, ie, LSI1
02 to the I / F buffer 112 from the external input terminal RCLK
Path 1 of the reference clock reaching the phase comparator 103 in the PLL 102 through the input terminal CLK of the PLL 102
Path 2 of feedback clock from I to phase comparator 103
The difference between the delay times of the path 3 and the path 4 corresponding to the difference of the delay values is measured by counting with the counter 104 of the PLL 102, and the variable delay elements 106 and 107 on the path 1 and the path 2 To make the delay values of the path 1 and the path 2 the same.

The LSI 101 has interface buffers 112, 113, 114, a PLL 102, and a CTS (Clock Tree Synthesis) buffer 120 comprising buffer groups 121 to 127 arranged and wired in a tree for equalizing clock delay. And flip flips 128, 129, 130. PLL102
Are phase comparators 103 for inputting the reference clock from the terminal RCLK and the internal clock from the terminal CLKI, and first and second buffers inserted between the interface buffer 112 and the terminal CLKI and the input terminal of the phase comparator 103, respectively.
Second variable delay elements 106 and 107 and a multiplied clock generator 1 that receives a reference clock and generates a multiplied clock
05, the counter 104, and the first to fourth delay elements 10
8 to 111. A low-pass filter receiving an output of the phase comparator in the PLL circuit, and a voltage-controlled oscillator (VCO) that inputs an output voltage of the low-pass filter as a control voltage and outputs an internal clock are not illustrated.

The path 1 has a reference clock input terminal RCLK
To I / F buffer 112, first variable delay element 106
, The path of the reference clock from the input terminal CLKI of the PLL 102 to the second input terminal of the phase comparator 103 through the second variable delay element 107. This is the path of the feedback clock to the end.

The path 3 is looped back from the multiplied clock generator 105 to the input end of the I / F buffer 114 via the first delay element 108 and the output end of the I / F buffer 113, and the second delay element 109 The path returns to the multiplied clock generator 105 again through

The path 4 is a path from the multiplied clock generator 105 to the end of the PLL 102 through the third delay element 110, and returns to the multiplied clock 105 via the fourth delay element 111 again.

The delay values of the paths 3 and 4 are counted by the counter 104 using the multiplied clock of the multiplied clock generator 105, and the delays of the first and second variable delay elements 106 and 107 are determined based on the count values. Control the time.

The operation of the embodiment of the present invention will be described.

When the power of the LSI 101 is turned on or a reset is performed, a multiplied clock is generated from the multiplied clock generator 105 with the reference clock input from the external input terminal RCLK of the LSI 101 as an input, and the delay value of the clock of the path 3 and the path 4 Is measured by the counter 104, and the first and second variable delay elements 106, 10
7 is controlled so that the delay values of the path 1 and the path 2 are the same.

When measuring the delay time of the path 3 and the path 4, the multiplied clock generator 105 sends the delay element 10 of the path 3
8, and simultaneously outputs a clock pulse to the delay circuit 110 in the path 4. For example, when the clock pulse is fed back from the delay circuit 111 in the path 4,
04 is started, and the counter 104 is stopped when the clock pulse is fed back from the delay circuit 109 of the path 3. As the count value of the counter 104, the delay amount of the path 3 and the path 4 is set. It is assumed that the path 4 has a shorter delay time than the path 3.

The delay times of the first and second delay elements 108 and 109 and the third and fourth delay elements 110 and 111 are made equal, and the delay characteristics of the I / F buffers 113 and 114 are set to I.
When the delay time is equal to the / F buffer 112, the difference between the delay times of the path 3 and the path 4 is equal to twice the difference between the delay times of the paths 1 and 2 as the count value of the counter 104.

Therefore, whether the delay time of the second variable delay element 107 is set to be longer than the delay time of the first variable delay element 106 by a delay amount corresponding to カ ウ ン ト of the count value of the counter 104. By setting the delay time of the first variable delay element 106 smaller than the delay time of the second variable delay element 107 by a delay amount corresponding to カ ウ ン ト of the count value of the counter 104, the path 1 Thus, even if the delay time of the path 2 and the delay time of the path 2 coincide with each other, the phase comparison with high accuracy can always be performed even if the manufacturing variation or the wiring condition inside the LSI changes.

The first and second variable delay elements 106,
Reference numeral 107 denotes a group of P-channel MOS transistors connected in parallel between the source of a P-channel MOS transistor constituting a CMOS inverter and a high potential power supply, for example, and CM
An inverter including a source of an N-channel MOS transistor constituting an OS inverter and an N-channel MOS transistor group connected in parallel between a low potential power supply is provided as a unit delay circuit, and a gate of the N-channel MOS transistor group and a P-channel MOS transistor are provided. At the gate of the transistor group,
The count output of the counter 104 and its inverted signal may be connected to each other to vary the current driving capability, so that the delay amount may be variably set.

FIG. 2 is a diagram showing the configuration of the second embodiment of the present invention. Referring to FIG. 2, in the second embodiment of the present invention, unlike the embodiment shown in FIG. 1, the counter 104A is configured as a counter to which an initial value is loaded. A terminal 115 for setting is provided.

By changing the initial value of the counter 104 from the terminal 115, the path 1 from the reference clock terminal RCLK of the LSI 101 to the input terminal of the phase comparator 102 is changed.
An arbitrary delay time difference (phase difference) can be provided between the path and the path 2.

[0032]

As described above, according to the present invention,
The following effects are obtained.

A first effect of the present invention is that the accuracy of PLL phase synchronization can be improved.

The reason is that, in the present invention, the delay value of the two paths whose phases are compared by the phase comparator in the PLL is automatically corrected.

According to the present invention, a highly accurate phase comparison can always be performed even when manufacturing variations or wiring conditions inside the LSI change.

The second effect of the present invention is that the stability of the circuit operation of the LSI is improved by improving the accuracy of the phase synchronization by the PLL.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of an embodiment of the present invention.

FIG. 3 is a diagram showing an example of a conventional circuit configuration.

FIG. 4 is a diagram showing another example of a conventional circuit configuration.

[Explanation of symbols]

21, 29 Delay element 22 Buffer 24 Up / down counter 25 Decoder 26, 27 Transfer gate 101, 201, 301 LSI 102 PLL 23, 103, 302 Phase comparator 104 Counter 105 Multiplied clock generator 106, 107 Variable delay element 108, 109 , 110, 111 Delay element 112, 113, 114, 212, 304 Interface buffer 120 CTS buffer 121-127, 306-312 Buffer 128-130, 313-315 Flip-flop

Claims (11)

[Claims] A first path from a reference clock input terminal to a first input terminal of a phase comparator of a PLL circuit;
The delay circuit is inserted in a second path from an input terminal of the PLL circuit to a second input terminal of the phase comparator for inputting a clock output from an output terminal of the L circuit as a feedback clock, and has a variable delay time. By adjusting the delay times of the first and second variable delay elements based on the settable first and second variable delay elements and the difference between the delay times of the first path and the second path. And a phase error automatic correcting means for controlling the delay time of the first path and the delay time of the second path to be equal to each other. A first path from a reference clock input terminal to a first input terminal of a phase comparator of a PLL circuit;
The delay time can be variably set by being inserted in a second path from an input terminal of the PLL circuit to input a clock output from the L circuit as a feedback clock to a second input terminal of the phase comparator. First and second variable delay elements, and based on a measurement result of a difference between delay times in third and fourth paths for delay time measurement including paths equivalent to the first and second paths, respectively, A phase error automatic correcting means for setting the delay times of the first and second variable delay elements and making the delay times of the first path and the second path equal to each other. . 3. A multiplied clock generator for generating a clock obtained by multiplying an input reference clock by the phase error automatic correction means, and a third clock generated by the multiplied clock output from the multiplied clock generator. A counter for counting the difference between the delay times of the fourth path, and setting the delay times of the first and second variable delay elements based on the count value of the counter,
3. The PLL circuit according to claim 2, wherein the delay time of the second path is equal to the delay time of the second path. 4. In the first path, a reference clock input from the reference clock input terminal is supplied to a first input of a phase comparator of the PLL circuit via an interface buffer and the first variable delay element. In the second path, the feedback clock input from the input terminal of the PLL circuit is supplied to the second input terminal of the phase comparator of the PLL circuit via the second variable delay element. The third path is turned back after the clock output from the multiplied clock generator is output from the output terminal via the first delay element and the first interface buffer. And a path that is fed back to the multiplied clock generator through a second interface buffer and a second delay element. The fourth path A path in which the clock output from the multiplied clock generator is sent to the end of the area of the PLL circuit via the third delay element, turned back, and fed back to the multiplied clock generator via the fourth delay element. The third path and the fourth path from the multiplied clock generator.
The counter measures the difference in delay time until the clock transmitted to the path returns to the multiplied clock generator. Based on the count value of the counter, the first and second clocks are measured.
4. The PLL circuit according to claim 2, wherein a delay time of said variable delay element is set. 5. The phase error automatic correction means, when power is turned on or reset, based on a measurement result of a delay time of the third path and the fourth path, wherein the first path and the second path are corrected. Perform the adjustment process to equalize the delay time of the route,
The PLL circuit according to any one of claims 2 to 4, wherein: 6. The PLL circuit according to claim 3, wherein an initial value of said counter is set freely from outside. 7. A semiconductor integrated circuit device provided with a PLL circuit for generating and outputting an internal clock from a reference clock input from an external terminal, wherein said PLL circuit is provided from said external terminal receiving said reference clock.
A first path to a first input terminal of a phase comparator of an L circuit, and an input terminal of the PLL circuit for inputting an internal clock as a feedback clock to an internal circuit of the semiconductor integrated circuit supplied from the PLL circuit. First and second variable delay elements each having a variably set delay time are inserted into a second path to a second input terminal of the phase comparator, and the first and second paths are The delay time of the first and second variable delay elements is set based on the measurement result of the difference between the delay times in the third and fourth paths for delay time measurement, each including an equivalent path, and the first and second variable delay elements are set. A semiconductor integrated circuit device comprising automatic phase error correction means for making a delay time of a path equal to a delay time of the second path. 8. A multiplied clock generator for generating a clock obtained by multiplying the reference clock input from the external terminal, wherein the phase error automatic correcting means includes: a multiplied clock output from the multiplied clock generator; A counter that counts the difference between the delay time of the third path and the delay time of the fourth path, and sets the delay times of the first and second variable delay elements based on the count value of the counter. 8. The semiconductor integrated circuit device according to claim 7, wherein delay times of said first path and said second path are equalized. 9. In the first path, a reference clock input from the reference clock input terminal is supplied to an interface buffer and a first variable delay element, and the first clock of the phase comparator of the PLL circuit is passed through the first variable delay element. The feedback clock input to the input terminal of the phase comparator is input to the second input terminal of the phase comparator via the second variable delay element. A transmission path for outputting a clock output from the multiplied clock generator to outside of the semiconductor integrated circuit device via a first delay element and a first interface buffer. And returning the output clock to the semiconductor integrated circuit device via a second interface buffer as it is and returning the clock to a second delay element. And a fourth path for transmitting a clock output from the multiplied clock generator to an end of the PLL circuit via a third delay element. A transmission path and a feedback path for returning the clock transmitted to the end to the multiplied clock generator via a fourth delay element, and providing a third path from the multiplied clock generator to the fourth path.
The counter measures the difference in delay time until the clock transmitted to the path returns to the multiplied clock generator, and sets the delay time of the first and second variable delay elements based on the count value of the counter. 9. The semiconductor integrated circuit device according to claim 8, wherein 10. The phase error automatic correction means, when power is turned on or reset, based on a measurement result of a delay time of the third path and the fourth path, wherein the first path and the second path are measured. 10. The semiconductor integrated circuit device according to claim 7, wherein a correction process for equalizing delay times of the paths is performed. 11. An apparatus according to claim 8, wherein an initial value of said counter is settable from an external terminal.
0. The semiconductor integrated circuit device according to any one of 0.