KR20060042334A - Thin film transistor array panel using organic semiconductor and manufacturing method thereof - Google Patents

Abstract

First, a gate line is formed on an insulating substrate, and a gate insulating layer covering the gate line is formed. Subsequently, a data line and a drain electrode including a lower layer and an upper layer patterned by a photolithography process using different exposure amounts are formed on the gate insulating layer to form an organic semiconductor. Subsequently, a passivation layer having a contact hole exposing the drain electrode is formed on the organic semiconductor, the data line, and the drain electrode, and a pixel electrode connected to the drain electrode is formed through the contact hole.

Semiconductor, Organic, Thin Film Transistor

Description

Thin film transistor array panel using organic semiconductor and manufacturing method thereof

1 is a layout view illustrating a structure of an organic semiconductor thin film transistor array panel according to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view of the organic semiconductor thin film transistor array panel of FIG. 1 taken along a line II-II '.

3, 5, 7, 9, 11, and 13 are layout views showing the steps of manufacturing the organic semiconductor thin film transistor array panel of FIGS.

4 is a cross-sectional view of the organic semiconductor thin film transistor array panel of FIG. 3 taken along a line IV-IV '.

FIG. 6 is a cross-sectional view of the organic semiconductor thin film transistor array panel of FIG. 5 taken along the line VI-VI ′.

FIG. 8 is a cross-sectional view of the organic semiconductor thin film transistor array panel of FIG. 7 taken along the line VIII-VIII ′.

FIG. 10 is a cross-sectional view of the organic semiconductor thin film transistor array panel of FIG. 9 taken along the line X-X '.

FIG. 12 is a cross-sectional view of the organic semiconductor thin film transistor array panel of FIG. 11 taken along the line XII-XII ′,

14 is a cross-sectional view taken along the line XIV-XIV ′ of the organic semiconductor thin film transistor array panel of FIG. 13.

<Description of the symbols for the main parts of the drawings>

121; Gate line 124; Gate electrode

140; Gate insulating layer 154; Organic semiconductor layer 164; Insulating layer 173; Source electrode

171; Data line 175; Drain electrode

180; Protective films 181, 182, and 185; Contact

190; Pixel electrodes 81 and 82; Contact aids

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an organic semiconductor thin film transistor array panel and a method of manufacturing the same. More particularly, the present invention relates to an organic semiconductor thin film transistor array panel and a method of manufacturing the same.

Research into field effect transistors using organic semiconductors as driving devices for next generation displays is being actively conducted. In general, organic semiconductors are largely divided into low molecular materials such as oligothiophene, pentacene, phthalocyanine, and C60, and polymer materials such as polythiophene and polythienylenevinylene. The low molecular organic semiconductor has excellent charge mobility (Mobility) of 0.05 to 1.5, and also has excellent characteristics such as a flashing ratio. However, since the organic semiconductor must be laminated and patterned by vacuum deposition using a shadow mask, the process is complicated and productivity is low, resulting in problems in mass production. On the other hand, the polymer organic semiconductor has a low charge mobility of 0.001 to 0.1, but can be coated or printed on a substrate by dissolving in a solvent, which is advantageous for large area display panels and has high mass productivity. The thin film transistor using such an organic semiconductor is light and thin, and is being evaluated as a driving element of a next generation display device that can be produced in a large area and in large quantities.

However, the organic semiconductor has a weak film quality, so that the thin film properties easily change or the thin film is damaged under the deposition conditions or the etching conditions according to the subsequent processes, which causes the characteristics of the thin film transistor. In order to solve this problem, it is preferable to first stack and pattern signal lines connected to the organic semiconductor, and then form the organic semiconductor thereon.

In this case, the conductive material constituting the signal line should be selected in consideration of the electrical characteristics with the organic semiconductor and the adhesion characteristics with the gate insulating layer underneath. Among the conductive materials constituting the signal line, gold (Au) or gold alloy (Au alloy) has a low resistance and has the advantage of stably securing the characteristics of the thin film transistor in contact with the organic semiconductor.                         

However, gold or a gold alloy has a poor contact property with an insulating film made of an organic material or an inorganic material, and thus has difficulty in being applied as a conductive material forming a signal line in a large display device.

An object of the present invention is to provide an organic semiconductor thin film transistor array panel including a signal line having stable contact characteristics and a method of manufacturing the same.

In order to achieve the above object, in the present invention, the signal line connected to the organic semiconductor is formed in a double structure, but the signal line is patterned by adjusting the exposure amount with only one mask.

The thin film transistor array panel according to the present exemplary embodiment is formed on an insulating substrate and an insulating substrate, and includes a gate line having a gate electrode, a gate insulating layer covering the gate line, and a double conductive film having different widths on the gate insulating layer. And a drain electrode facing the data line centering on the data line and the gate electrode intersecting the gate line, and formed on the gate insulating layer and overlapping the gate electrode, and formed on the source electrode and the drain electrode as part of the data line. A semiconductor, a protective film formed on the organic semiconductor, and a pixel electrode connected to the drain electrode.

The data line and the drain electrode may include a lower layer and an upper layer positioned on the lower layer, and the upper layer may have a wider width than the lower layer.                     

The boundary of the lower layer is located within the boundary of the upper layer, the lower layer preferably contains chromium, and the upper layer preferably contains gold.

In the method of manufacturing the thin film transistor array panel according to the exemplary embodiment of the present invention, a gate line is formed on an insulating substrate, and a gate insulating layer covering the gate line is formed. The data line and the drain electrode having the source electrode on the gate insulating layer are formed in a double structure by a photolithography process using different exposure amounts. Next, an organic semiconductor layer is formed and then patterned to form an organic semiconductor, and a protective film is formed on the organic semiconductor, the data line, and the drain electrode. Next, a pixel electrode connected to the drain electrode is formed.

In the data line and drain electrode forming step, the first conductive film is stacked, a first photosensitive film pattern is formed on the first conductive film, and the first conductive film is etched using the first photosensitive film pattern as an etching mask. Subsequently, after the first photoresist layer pattern is removed, a second conductive layer is formed on the first conductive layer, a second photoresist layer pattern is formed on the second conductive layer, and the second conductive layer is etched using the second photoresist pattern as an etching mask. It includes a step.

The first photoresist pattern and the second photoresist pattern may be formed by exposing and developing with the same mask, and the first photoresist pattern may be formed by exposing at a higher exposure amount than the second photoresist pattern.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right on" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

An organic semiconductor thin film transistor array panel and a method of manufacturing the same according to an embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

First, an organic thin film transistor array panel structure according to an exemplary embodiment of the present invention will be described with reference to FIGS. 1 and 2.

1 is a layout view illustrating a structure of an organic thin film transistor array panel according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view illustrating a structure of an organic thin film transistor array panel according to an exemplary embodiment of the present invention. It is sectional drawing cut along the -II 'line | wire.

In the organic thin film transistor array panel according to the exemplary embodiment of the present invention, a plurality of gate lines 121 for transmitting a gate signal are formed on the transparent insulating substrate 110.

The gate line 121 mainly extends in the horizontal direction, and a portion of each gate line 121 protrudes to form a plurality of gate electrodes 124. In this case, one end 129 of the gate line 121 is extended in width for connection with an external circuit or another layer.

The gate line 121 includes a conductive film made of a metal having low resistivity, such as gold, silver, aluminum (Al), or an aluminum alloy, so as to reduce a delay or voltage drop of the gate signal. It is preferable. In addition, it may include two or more conductive films having different physical properties, that is, one conductive film is made of a low-resistance conductive material, and the other conductive film is made of another material, in particular with indium zinc oxide (IZO) or indium tin oxide (ITO). It is preferable that the material is excellent in physical, chemical, and electrical contact properties, such as molybdenum (Mo), molybdenum alloy (eg, molybdenum-tungsten (MoW) alloy), chromium (Cr), and the like.

Sides of the gate lines 121 are inclined, respectively, and the inclination angle thereof is about 30 to 80 degrees with respect to the surface of the substrate 110.

A gate insulating layer 140 made of an organic insulating material or an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx) is formed on the gate line 121. Here, the gate insulating layer 140 may be formed of a SiO ₂ film surface-treated with octadecyl-trichloro-silane (octadecyl trichloro silane).

A plurality of data lines 171 and a plurality of drain electrodes 175 are formed on the gate insulating layer 140, respectively.                     

The data line 171 mainly extends in the vertical direction to cross the gate line 121 and transmit a data voltage. A plurality of branches extending from the data line 171 toward the drain electrode 175 forms a source electrode 173. The pair of source electrode 173 and the drain electrode 175 are separated from each other and positioned opposite to the gate electrode 124. Each data line 171 includes an extension 179 that is widened for contact with an external circuit or another layer.

In this case, the data line 171 and the drain electrode 175 may be formed of a material having excellent physical, chemical, and electrical contact properties with other materials, particularly the gate insulating layer 140, for example, a lower layer 171p made of chromium (Cr) or the like. Metals having low resistivity and excellent contact characteristics with organic semiconductors such as copper (Cu), silver (Ag), aluminum (Al), nickel ( Ni), an upper layer 171q made of a metal-based, most preferably a gold-based metal including gold (Au). In FIG. 2, lower and upper layers of the end portion 179, the source electrode 173, and the drain electrode 175 of the data line 171 are denoted by reference numerals 179p, 179q, 173p, 173q, and 175p, 175q, respectively. . In this case, the boundary lines of the lower layers 171p and 175p are positioned within the boundary lines of the upper layers 171q and 175q, and the lower layers 171p and 175p have a narrower width than the upper layers 171q and 175q. Further, the thicknesses of the lower films 171p and 175q are in the range of 50-80 GPa, and the thicknesses of the upper films 171q and 175q are preferably in the range of 300-1,000 GPa. As described above, the data line 171 and the drain electrode 175 are in contact with the gate insulating layer 140 by the lower layers 171p and 175p of chromium having excellent contact characteristics with the organic insulating material or the inorganic insulating material. In the large thin film transistor array panel, the data line 171 and the drain electrode 175 may be prevented from being lost or damaged. In addition, it is possible to stably secure the characteristics of the thin film transistor including the upper layers 171q and 175q including gold having low resistance while having excellent contact characteristics with the organic semiconductor.

Next, an organic semiconductor 154 is formed on the gate insulating layer 140 on which the data line 171 and the drain electrode 175 are formed. In this case, the organic semiconductor 154 has an island shape and completely covers the gate insulating layer 140 between the source electrode 173 and the drain electrode 175.

The organic semiconductor 154 uses a high molecular material or a low molecular material dissolved in an aqueous solution or an organic solvent. Polymeric organic semiconductors are generally well soluble in solvents and are suitable for printing processes. In addition, there is a material that is well dissolved in an organic solvent even in a low molecular organic semiconductor is used.

The organic semiconductor 154 is a derivative including a substituent of tetratracene or pentacene, or an oligothiophene in which 4 to 8 are linked through 2 and 5 positions of a thiophene ring. Can be.

In addition, the organic semiconductor 154 may be perylenetetracarboxylic dianhydride (PTDA) or an imide derivative thereof or naphthalenetetracarboxylic dianhydride (NTCDA) or an imide thereof. (imide) derivatives.

In addition, the organic semiconductor 154 may be a metallized pthalocyanine or a halogenated derivative thereof or a derivative including perylene or coroene and substituents thereof. The metal added to metallized pthalocyanine is preferably copper, cobalt, zinc, or the like.

In addition, the organic semiconductor 154 may be a co-oligomer or a co-polymer of thienylene and vinylene. In addition, the organic semiconductor 150 may be thiophene.

In addition, the organic semiconductor 154 may be a derivative including perylene or coroene and substituents thereof.

In addition, the organic semiconductor 154 may be a derivative including one or more hydrocarbon chains having 1 to 30 carbon atoms in the aromatic or heteroaromatic ring of the derivatives.

The gate electrode 124, the source electrode 173, and the drain electrode 175 form a thin film transistor (TFT) together with the organic semiconductor 154, and a channel of the thin film transistor is a source electrode 173. And an organic semiconductor 154 between the drain electrode and the drain electrode 175.

An insulator 164 made of an insulating material capable of performing a dry low temperature film forming process is formed on the organic semiconductor 154, and the insulator 164 completely covers the organic semiconductor 154. The insulator 164 is made of an insulating material such as parylene, which can be formed at room temperature or low temperature in a dry process, and thus, a subsequent film formation process, that is, the insulator 164 or the protective layer 190. The organic semiconductor 154 is prevented from being damaged in the process of forming the film. Therefore, the characteristics of the organic semiconductor thin film transistor can be secured stably.

On the gate insulating layer 140, the organic semiconductor 154, and the insulator 164, an a-Si formed of an organic material or plasma enhanced chemical vapor deposition (PECVD) having excellent planarization characteristics and photosensitivity is formed. A passivation layer 180 made of a low dielectric constant insulating material such as: C: O, a-Si: O: F, or silicon nitride, silicon oxide, or the like is formed.

The passivation layer 180 includes a gate line 121 together with a plurality of contact holes 185 and 182 and a gate insulating layer 140 exposing the drain electrode 175 and the end portion 179 of the data line 171, respectively. The contact hole 181 which exposes the end part 129 of the () is formed. As described above, the embodiment in which the passivation layer 180 has contact holes 181 and 182 exposing the gate lines 121 and the end portions 129 and 179 of the data line 171 uses an anisotropic conductive film as an external driving circuit. In order to connect the gate line 121 and the data line 171, the gate line 121 and the data line 171 have a contact portion. Unlike the present embodiment, the gate line 121 or the data line 171 may not have a contact portion at an end thereof. In this structure, the gate driving circuit is formed on the substrate 110 in the same layer as the organic thin film transistor. The ends of the gate line 121 and the data line 171 are electrically connected directly to the output terminal of the driving circuit.

The contact holes 185, 181, and 182 expose the drain electrode 175, the end portion 129 of the gate line, and the end portion 179 of the data line, and the contact holes 185, 181, and 182 are formed later in the ITO. Alternatively, the conductive film may be exposed to secure contact characteristics with the conductive film of the IZO, and the contact holes 185, 181, and 182 may have end portions of the drain electrode 175, the gate line 121, and the data line 171. The boundary of 179 may be revealed.

A plurality of pixel electrodes 190 and a plurality of contact assistants 81 and 82 made of a transparent conductive material such as IZO or ITO, or a conductive material having reflectivity are formed on the passivation layer 180. have.

The pixel electrode 190 is physically and electrically connected to the drain electrode 175 through the contact hole 185 to receive a data signal from the drain electrode 175.

The pixel electrode 190 also overlaps the neighboring gate line 121 and the data line 171 to increase the aperture ratio, but may not overlap.

The contact auxiliary members 81 and 82 are connected to the end portions 129 and 179 of the gate line and the data line, respectively, through the contact holes 181 and 182. The contact auxiliary members 81 and 82 serve to protect and protect the adhesion between the end portions 129 and 179 of the gate line 121 and the data line 171 and an external device such as a driving integrated circuit. It is not essential that the application is optional.

Referring to the operation of the organic thin film transistor array panel according to the present invention configured as described above are as follows.

For example, in the case of a P-type semiconductor, if no voltage is applied to the gate electrode 124, the source electrode 173, and the drain electrode 175, all the charges in the organic semiconductor layer 154 are evenly distributed in the organic semiconductor layer 154. It spreads. When a voltage is applied between the source electrode 173 and the drain electrode 175, current flows in proportion to the voltage under the low voltage. At this time, when a positive voltage is applied to the gate electrode 124, the holes are all pushed up by the electric field by the applied voltage. Therefore, a layer free of conductive charges is formed in a portion close to the gate insulating layer 140, and this layer is called a depletion layer. In this case, when a voltage is applied to the source electrode 173 and the drain electrode 175, since the conduction charge carriers are reduced, less current flows than when no voltage is applied to the gate electrode 124. On the contrary, when the negative electrode of the gate electrode 124 is applied, a positive charge is induced between the organic semiconductor layer 154 and the gate insulating layer 140 by the electric field by the applied voltage, and thus, the gate insulating layer ( In the region close to 140), a large amount of charge is formed. This layer is called an accumulation layer. In this case, when a voltage is applied to the source electrode 173 and the drain electrode 175, more current flows. Accordingly, the source electrode 173 and the drain electrode 175 are alternately applied by applying a positive voltage and a negative voltage to the gate electrode 124 while a voltage is applied between the source electrode 173 and the drain electrode 175. You can control the amount of current flowing between them. This ratio of the amount of current is called an on / off ratio. The larger the flashing ratio, the better the transistor.

Next, a method of manufacturing the thin film transistor array panel for the liquid crystal display device illustrated in FIGS. 1 and 2 according to an embodiment of the present invention will be described in detail with reference to FIGS. 3 to 14 and FIGS. 1 and 2.

3, 5, 7, 9, 11, and 13 are layout views illustrating the steps of manufacturing the organic semiconductor thin film transistor array panel of FIGS. 1 and 2 according to the process sequence of FIG. 3 is a cross-sectional view of the organic semiconductor thin film transistor array panel of FIG. 3 taken along the line IV-IV ', and FIG. 6 is a cross-sectional view of the organic semiconductor thin film transistor array panel of FIG. 5 taken along the line VI-VI'. 7 is a cross-sectional view of the organic semiconductor thin film transistor array panel of FIG. 7 taken along the line VIII-VIII ', and FIG. 10 is a cross-sectional view of the organic semiconductor thin film transistor array panel of FIG. 9 taken along the line XX', and FIG. Is a cross-sectional view of the organic semiconductor thin film transistor array panel of FIG. 13 taken along the line XII-XII ', and FIG. 14 is a cross-sectional view of the organic semiconductor thin film transistor array panel of FIG. 13 taken along the line XIV-XIV'.

First, as shown in FIGS. 3 and 4, the gate line 121 including the gate electrode 124 is formed on the transparent insulating substrate 110. In this case, the transparent insulating substrate 110 used may be glass, silicon, or plastic. The gate line 121 includes a gate line 121 including a gate electrode 124 by depositing a conductive layer of gold, aluminum, gold, or an alloy including the same on the insulating substrate 110 and patterning the same. To form.

Next, as shown in FIGS. 5 and 6, the gate insulating layer 140 covering the gate line 121 is formed on the insulating substrate 110. The gate insulating layer 140 is formed by depositing an insulating material such as silicon nitride (SiNx) or silicon oxide (SiO ₂ ) to a thickness of 500 to 3000 by chemical vapor deposition (CVD) and immersing it in an OTS. Can be surface treated. In addition, the gate insulating layer 140 may be formed of one of maleimide-styrene, polyvinylphenol (PVP), and modified cyanoethylpullulan (m-CEP). .

Subsequently, chromium (Cr) is deposited on the gate insulating layer 140 to a thickness of about 50 kV by sputtering to form a chromium film, and a photoresist film is coated on the upper part, and the photoresist film is exposed and developed by a photo process using a data mask. The first photosensitive film pattern 72 is formed. Subsequently, the chromium layer is etched using the first photoresist layer pattern 72 as an etch mask to form lower layers 171p and 175p of the data line and the drain electrode.

Subsequently, as shown in FIGS. 7 and 8, after the first photoresist layer pattern 72 is removed, a low-resistance conductive layer of gold is laminated to a thickness of about 500 kV by vacuum thermal evaporation, and then a photoresist layer is applied thereon. Subsequently, using the data mask used to form the first photoresist layer pattern 72, the photoresist layer is exposed and developed again by a photographic process to form a second photoresist layer pattern 82, and then the lower conductive layer is formed as an etching mask. Etch is formed to form upper layers 171q and 175q of the data line 171 and the drain electrode 175 to complete the data line 171 and the drain electrode 175 including the source electrode 173. At this time, when exposing the photoresist film to form the first photoresist pattern 72 (see FIG. 6), the first photoresist pattern 72 is exposed to the second photoresist by sufficiently exposing the photoresist for a longer time than when forming the photoresist pattern 82 of FIG. 2. It has a narrower width than the pattern 82. Therefore, the lower layers 171p and 175p have a narrow width than the upper layers 171q and 175q, and the upper layers 171q and 175q completely cover the lower layers 171p and 175p. In the manufacturing method of the present application, only one mask is formed by forming the data lines 171 and 175 in a dual structure of the lower layers 171p and 175p and the upper layers 171q and 175q having different widths by adjusting only the exposure amount. As a result, the manufacturing cost does not increase.

Next, as shown in FIGS. 9 and 10, the organic semiconductor layer is formed and then patterned by a photolithography process using a mask to form the organic semiconductor 154 on the gate electrode 124. At this time, the lower layers 171p and 175p of the data line 171 and the drain electrode 175 are completely covered with the upper layers 171q and 175q so that the lower layers 171p and 175p do not contact the organic semiconductor 154. Do not.

Next, as shown in FIGS. 11 and 12, an insulating material such as parylene is formed in a dry process at room temperature or low temperature on the substrate 110 on which the organic semiconductor 154 is formed. The insulator 164 covering the organic semiconductor 154 is formed by patterning the photolithography process. Through the dry film forming process at room temperature, the organic semiconductor 154 may be prevented from being damaged, and thus, the characteristics of the organic semiconductor thin film transistor may be stably secured.

Next, as shown in FIGS. 13 and 14, a passivation layer covering the organic semiconductor 154 and the insulator 164 on the substrate 110 on which the data line 171 and the drain electrode 175 are formed. 180 are stacked and patterned by a photolithography process using a mask to form contact holes 185, 181, and 182 to expose the drain electrode 175, the end portion 129 of the gate line, and the end portion 179 of the data line. do. In this case, the organic semiconductor 154 may be prevented from being damaged in the film forming process of the protective film 180 by completely covering the organic semiconductor 164 with the insulator 164 and then laminating the protective film 180.                     

Next, as shown in FIGS. 1 and 2, the pixel electrode 190, the contact members 81 and 82, and the like, which are connected to the drain electrode 175 and the contact hole 185, are formed on the passivation layer 180. .

According to the exemplary embodiment of the present invention, the signal line is formed of a double conductive layer capable of securing excellent contact characteristics with the gate insulating layer and the organic semiconductor, thereby preventing the signal line from being lost or damaged even in a large display device.

In addition, the manufacturing cost can be prevented from increasing by patterning the double conductive film by adjusting only the exposure amount.

Further, by completely covering the organic semiconductor using an insulator that does not damage the organic semiconductor, and then performing a film forming process, the organic semiconductor thin film transistor can be easily carried out in a manufacturing process while securing the characteristics of the organic semiconductor thin film transistor.

Although the present invention has been described with reference to one embodiment shown in the accompanying drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Could be. Accordingly, the true scope of protection of the invention should be defined only by the appended claims.

Claims (9)

Insulating substrate; A gate line formed on the insulating substrate and having a gate electrode; A gate insulating layer covering the gate line; A double conductive layer having a different width on the gate insulating layer, the data line crossing the gate line, and the drain electrode facing the data line around the gate electrode; An organic semiconductor formed on the gate insulating layer and overlapping the gate electrode and formed on the source electrode and the drain electrode which are part of the data line; A protective film formed on the organic semiconductor; A pixel electrode connected to the drain electrode Organic semiconductor thin film transistor array panel comprising a. In claim 1, The data line and the drain electrode may include a lower layer and an upper layer positioned on the lower layer. The upper layer has a wider width than the lower layer. In claim 2, The boundary line of the lower layer is positioned within the boundary line of the upper layer. In claim 2, The lower layer includes chromium. In claim 2, The upper layer includes a gold thin film transistor array panel. Forming a gate line on the insulating substrate; Forming a gate insulating layer covering the gate line; Forming a data line and a drain electrode having a source electrode on the gate insulating layer in a dual structure by a photolithography process using different exposure amounts; Forming an organic semiconductor layer and then patterning to form an organic semiconductor; Forming a passivation layer on the organic semiconductor, the data line and the drain electrode; Forming a pixel electrode connected to the drain electrode Method of manufacturing an organic semiconductor thin film transistor array panel comprising a. In claim 6, The data line and drain electrode forming step, Stacking a first conductive film, Forming a first photoresist pattern on the first conductive layer; Etching the first conductive layer using the first photoresist pattern as an etching mask; Removing the first photoresist pattern and then forming a second conductive layer on the first conductive layer; Forming a second photoresist pattern on the second conductive layer; And etching the second conductive layer using the second photoresist pattern as an etch mask. In claim 7, The first photoresist pattern and the second photoresist pattern are formed by exposing and developing with the same mask. In claim 7, The first photoresist pattern is exposed by a greater exposure amount than the second photoresist pattern.

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