KR20060028705A - Readdressable virtual dma control and status registers - Google Patents

Abstract

Apparatus and method for carrying out a DMA transfer wherein an address is written into a DMA register of a DMA controller specifying a memory location within a memory device at which either the parameters for a transfer of a block of data are provided or the status of the transfer of a block of data is to be written by the DMA controller.

Description

READDRESSABLE VIRTUAL DMA CONTROL AND STATUS REGISTERS}

The present invention relates to defining virtual DMA registers in a memory address space for controlling and monitoring the status of DMA transfers.

Virtual computer system architectures have used a number of approaches that attempt to efficiently transfer data blocks between devices (memory devices, I / O devices, etc.) across buses within a computer system. One of the simplest approaches was to allow the CPU (Central Processing Unit) to read a block of data from one device and then write the block of data to another device. However, such tasks are often considered to be more suitable tasks that are delegated to other alternative mechanisms so that the CPU can be more fully dedicated to performing more complex computations and other computational tasks.

One widely used alternative mechanism is to add a direct memory access (DMA) controller to the computer system that replaces the movement of data blocks between the system memory and other devices of the computer system. Typically, such DMA controllers are programmed to perform specific transfer of data blocks by the CPU, which writes transfer parameters directly into registers within the DMA controller. Thereafter, as the transfer of the data block is performed, the CPU is typically programmed to poll one or more registers in the DMA controller to query the transfer status.

However, the use of DMA controllers has its drawbacks. Although the burden on the CPU to actually perform the transfer of data blocks has diminished, it is still considered inefficient to poll the registers in the DMA controller to query the transfer status. Also, in many implementations of computer systems, a write operation performed by the CPU to program the registers in the DMA controller and a read operation performed by the CPU to query the status from the registers in the DMA controller may take more time than desired. This can take

Another widely used alternative mechanism is to integrate bus mastering capabilities into various I / O devices in a computer system, which can voluntarily perform the transfer of data blocks on their own. Typically, this transfer is programmed to take place by the CPU writing the transfer parameters directly into the registers within this bus mastering device. Thereafter, as the transfer of the data block is performed, the CPU polls one or more registers in the bus mastering device to query the transfer status.

However, the use of such bus mastering devices has its drawbacks. Although the burden on the CPU to actually perform the transfer of data blocks is reduced, a write operation performed by the CPU to program a register in the DMA controller and a read operation performed by the CPU to query status from a register in the DMA controller May take more time than would be desirable. In addition, the read operation performed by the bus mastering device, in particular the reading of data blocks from the system memory, may take more time than would be desirable.

The objects, features, and advantages of the present invention will be apparent to those skilled in the art through the following detailed description.

1 is a block diagram of embodiments using a computer system.

2 is another block diagram of other embodiments using a computer system.

3 is a block diagram of embodiments of interaction between devices reserved to transmit a block of data.

4 is a block diagram of embodiments of interaction between devices reserved to transmit multiple data blocks.

5 is another block diagram of embodiments of interaction between devices reserved to transmit multiple data blocks.

6 is another block diagram of embodiments of interaction between devices reserved to transmit multiple data blocks.

7 is another block diagram of other embodiments using a computer system.

8 is a flowchart of one embodiment.

9 is a flowchart of another embodiment.

10 is a flow chart of another embodiment.

In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that these details are not required to practice the invention as claimed below.

The present invention as claimed below relates to an incorporating support for maintaining virtual registers for a DMA controller at storage locations in other devices of a computer system or other similar electronic system. The following discussion focuses on DMA controllers within a computer system, but one of ordinary skill in the art, as claimed below, may implement and support other similar dedicated logic for the movement of data blocks between electronic systems or devices having a DMA controller. Will understand.

1 is a block diagram of embodiments using a computer system. Computer system 100 comprises at least a portion of CPU 110, bus 119, logic 120, bus 149, system memory 140, bus 159, and device 150. The CPU 110, bus 119, logic 120, bus 149 and system memory 140 may be stored in the system memory 140 and / or in other devices of the computer system 100. Configure the form of a core of computer system 100 capable of executing readable instructions. However, as those skilled in the art will readily appreciate, this is only one example of the core forms of many possible computer systems 100, which may also further configure other buses and devices not shown. Can be.

In various embodiments, the CPU 110 is one of several types of CPU including a CPU capable of executing at least a portion of the "x86" instruction set invented by Intel Corporation of Santa Clara, Calif. It can be of any type. In addition, various possible embodiments may have one or more CPUs with additional buses and / or devices to support one or more CPUs (not shown). Logic 120 is coupled to CPU 110 via bus 119 and supports execution of instructions by CPU 110 such that logic 120 is further coupled via bus 149 to system memory 140. And provide access to the CPU 110 and control the CPU 110. Logic 120 also provides access to other devices that make up computer system 100, such as device 150 to which logic 120 is connected via bus 159.

In connection with the buses 119, 149, and 159, and in the CPU 110, the system memory 140 and the device 150, respectively, to enable a transaction in which addresses, instructions, and data are transmitted. In providing access to the logic 120, the logic 120 generally serves as a "bridge" between these buses. In its role as a bridge, logic 120 may also include a memory controller 122 to support performing transactions on bus 149 and a bus interface 127 to support performing transactions on bus 159. To the computer system 100. In order to relieve some of the burden of the CPU performing significant transfer of data blocks, logic 120 further provides DMA controller 130.

In various embodiments, system memory 140 includes a fast page mode (FPM), extended data out (EDO), single data rate (SDR), or double data rate (DDR) form of synchronous dynamic DRAM (SDRAM). RAM, or any of various types of RAM using a RAMBUS ™ interface or other interface. Memory controller 122 and bus 149 are configured to support timing and / or protocol requirements of one or more types of memory and / or memory interface.

In various embodiments, the bus 159 and / or other buses that may make up the computer system 100 are, for example, extended industry standard architecture (EISA), Micro Channel ™ architecture (MCA), peripheral (PCI). component interconnect), PCI-X, PCI Express, etc., in accordance with the characteristics and / or design of any of the various well-known forms of "standardized" buses in the field of computer design. Bus interfaces 127 and 157 are configured to support timing and / or protocol requirements of bus 159.

In one embodiment, the CPU 110 causes the CPU 110 to program the DMA controller 130 to perform the transfer of a data block between the data storage locations 146 and 148 in the system memory 140. Run the commands in. CPU 110 includes, but is not limited to, starting addresses of data storage locations 146 and 148, values specifying various transfer parameters that occur, values indicating the amount of data to be transferred (i.e. the size of the data block). One or more parameter registers 133 with a value indicating that the transfer status is to be provided at the state store location 144 allocated within the system memory 140, and a value to one or more control bits at which the transfer occurs. Fill in. The DMA controller 130 then performs the transfer. While executing this transfer, the CPU 110 writes the state store location 144 once to determine whether the DMA controller 130 writes a value to the state store location 144 indicating that the transfer is complete. The abnormality can be read. Assuming that creating a very low latency path between the CPU and the system memory is the norm in the design of computer systems, such as computer system 100, the CPU 110 may not be able to access the conventional registers from the registers in the DMA controller 130. By reading the state store location 144 in the system memory 140 much faster than the read method of s.

In yet another embodiment, the CPU 110 writes the various transmission parameters that occur to the alternate parameter storage location 143 allocated in the system memory 140 to the data storage locations 146 and 148 in the system memory 140. It executes a series of instructions that cause the CPU 110 to program the DMA controller 130 to perform the transfer of data blocks therebetween. Such parameters may include, but are not limited to, starting addresses of data store locations 146 and 148, a value indicating the amount of data to be transferred, and a value indicating that a transmission status will be provided at state store location 144. It may not be. The CPU 110 also causes the one or more parameter registers 133 to be written with a value specifying the start address of the alternate parameter storage location 143 and a value in one or more control bits as a trigger to cause the transfer. In response to this trigger, DMA controller 130 then executes the transfer. While executing this transfer, the CPU 110 writes the state store location 144 once to determine whether the DMA controller 130 writes a value to the state store location 144 indicating that the transfer is complete. The abnormality can be read.

In one variation of this embodiment, the state store location 144 is part of the alternate parameter store location 143 or at an address in the system memory 140 that is a predetermined offset from the base address of the alternative parameter store location 143. Is assigned. In another variation of this embodiment, DMA controller 130 is individually programmed (via parameter registers 133 or alternate parameter storage location 143) with an address for state storage location 144.

In another variation of this embodiment, the transfer state is written to an alternate state store location 164 in the device store 160 of the device 150, and the DMA controller 130 enters an address for the alternate state store location 164. Are programmed (via parameter registers 133 or alternate parameter storage location 143). Alternate state store location 164 may include one or more memory locations allocated within device store 160 and a device that may be used for any of a number of possible purposes, depending on the nature of device 150. Memory buffer within 150), which will be apparent to those skilled in the art. The benefit of writing the transfer status to the alternate state store location 164 in the device store 160 of the device 150 can wait for this state, provided the device 150 performs some other task, and this state Unwanted write delays can be avoided by not writing a state to the state store location 144 in system memory 140 that should actually be transmitted to device 150. This advantage is that a device using the bus mastering capability that the transfer of the substantial state from the state store location 144 to the alternate state store location 164 may have for the device 150 to read the state store location 144. If you need it will be larger. As will be appreciated by those skilled in the art, performing a read operation over a bus, such as bus 159, may take longer to complete than a write operation and may also momentarily lock up the bus. This is a read operation that first requires a request for data made over a bus to read a piece of data, for example the transfer status, and then the next data needed until the requested data can be provided. This is due to the waiting period. Depending on the bus 159 design, the coherency and ordering rules of the read and write operations may be defined such that at least the device 150 is responsible for other transmissions across the bus 159 until the bus 159 is unused or a condition is received. May require that at least not a subset be performed. Therefore, depending on the environment at the time the read operation begins, the buses 149 and 159 as well as the system memory 140 and device 150 respond to a read operation that reads the status from the state store location 144. And can be instantaneously monopolized while completing a read operation. Conversely, if the state is written directly to the device 150 by the DMA controller 130, the write operation is performed by the bus interface 127 using the less stringent requirements generally given to the write operation to maintain consistency and ordering. After being posted in the write buffer 128, the bus 159 may be allowed to be sent to the device 150 over the bus 159 when it is less likely to be locked.

2 is another block diagram of embodiments using a computer system. The numbered items in FIG. 2 are somewhat different from the computer system 100 of FIG. 1, and generally correspond to the numbered items in FIG. 1, where the computer system 200 is at least in part, a CPU 210, a bus 219. ), Logic 220, bus 249, system memory 240, bus 259, and device 250. As in the case of computer system 100, this is just one example of the core forms of many possible computer systems 200, which also further configure other buses and devices not shown. It will be readily apparent to those skilled in the art that they may. The logic 220 is connected to the CPU 210 via the bus 219 and supports execution of instructions by the CPU 210 such that the logic 220 is connected to the memory controller 222 and the bus in the logic 220. 249 to provide the CPU 210 with access to the system memory 240 further connected and to control the CPU 110. The logic 220 may also be connected to other devices that make up the computer system 200, such as the device 250 in which the logic 220 is connected via the bus interface 227 and the bus 259 within the logic 220. Provide access to

In one embodiment, the CPU 210 causes the CPU 210 to perform a transfer of data blocks between the data storage location 246 in the system memory 240 and the data storage location 266 in the device 250. Executes a series of instructions (perhaps stored in system memory 240) that causes the controller 230 to be programmed. CPU 210 writes the various parameters of the transfer that occur in memory locations in parameter storage location 243 allocated in system memory 240. These parameters indicate the starting addresses of the data store locations 246 and 266, a value indicating the amount of data to be transferred, and that the transfer status will be provided at the state store location 244 allocated within the system memory 240. It may include a value, but may not be limited thereto. CPU 210 also allows writing one or more parameter registers 233 with a value specifying the starting address of parameter storage location 243 and a value in one or more control bits as a trigger to cause the transfer. In response to this trigger, DMA controller 230 subsequently executes the transfer. While executing this transfer, the CPU 210 writes the state store location 244 once to determine whether the DMA controller 230 writes a value to the state store location 244 indicating that the transfer is complete. The abnormality can be read.

In one variation of this embodiment, the state store location 244 is part of the parameter store location 243 or assigned at an address in the system memory 240 at a predetermined offset from the base address of the parameter store location 243. do. In another variation of this embodiment, the DMA controller 230 is individually programmed (within the parameter registers 233 or the parameter store location 243) with an address for the state store location 244. In another variation of this embodiment, the transfer state is written to an alternate state store location 264 in the device store 260 of the device 250, and the DMA controller 230 sets the address for the alternate state store location 264. Programmed with the device 250, if desired, the device 250 is allowed to provide the transmission status faster.

In yet another embodiment, the CPU 210 writes the various transfer parameters that occur between the data storage locations 246 and 266 by writing to the alternate parameter storage location 263 assigned within the device storage 260 of the device 250. Executes a series of instructions that causes the CPU 210 to program the DMA controller 230 to perform the transfer of the data block. As before, these parameters may include starting addresses of the data store locations 246 and 266, a value indicating the amount of data to be transmitted, and a value indicating that the transmission status will be provided to the state store location 264. However, this may not be limited. The CPU 210 also causes the one or more parameter registers 233 to be written with a value specifying the starting address of the alternate parameter storage location 263 and a value in one or more control bits as a trigger to cause the transfer to occur. In response to this trigger, DMA controller 230 subsequently executes the transfer. While executing this transfer, device 250 or CPU 210 may determine whether or not state DMA controller 230 writes a value to state store location 264 indicating that the transfer is complete. 264) can be read more than once.

3 is a block diagram of embodiments of a transaction between devices reserved to transmit a data block. Specifically, FIG. 3 illustrates the transfer of a block of data from control device 310, DMA controller 330, and one or more memory devices and / or source data storage location 346 to destination data storage location 348. Depicts the interaction of the devices that provide the storage. The control device 310 may execute a CPU (computer system or other) that may execute instructions 312 to cause the control device 310 to program the registers in the DMA controller 330 connected thereto to cause the transfer of the data block. Electronic system), microcontroller, sequencer, and the like. The addressable space 340 is a map of address locations that are both accessible from the control device 310 and the DMA controller 330.

In some embodiments, the addressable space 340 may consist entirely of a single system memory device (not shown) to which both the control device 310 and the DMA controller 330 are connected. These embodiments are both somewhat different from data store locations 146 and 148, where both source data store location 346 and destination data store location 348 are system memory devices, eg, system memory 140. It may be largely similar to the embodiments of FIG. 1 within. In other embodiments, the addressable space 340 may consist of a combination of buffers in memory devices and / or other devices to which both the control device 310 and the DMA controller 330 are connected. These embodiments are somewhat different from the data storage location 246 assigned within the system memory 240 and the data storage location 266 assigned within the device storage 260 of the device 250. ) And destination data storage location 348 may be largely similar to the embodiments of FIG. 2 in which other devices are allocated. More precisely, for example, source data store location 346 may be located in system memory, and destination data store location 348 may be located in a buffer in another device.

The control device 310 writes to the parameter storage location 343 the base addresses of the source data storage location 346 and the destination data storage location 348 together with the amount of data to be transmitted and the address of the state storage location 344. This prepares the transfer execution of the data block from the source data store location 346 to the destination data store location 348. The control device 310 also writes the base address of the parameter storage location 343 into the parameter registers 333 in the DMA controller 330 along with one or more bits that trigger the DMA controller 330 to perform data transfer. do.

In response to this trigger, the DMA controller 330 acquires the base address of both the source data store location 346 and the destination data store location 348, the amount of data to be transferred, and the base address of the state store location 344. To access the parameter storage location 343 at the base address programmed in the parameter registers 333. DMA controller 330 performs the transfer of the data block from source data store location 346 to destination data store location 348 and writes the transfer status to state store location 344. The control device 310 reads the state store location 344 to determine whether the DMA controller 330 writes a value to the state store location 344 indicating that the data transfer is complete.

4 is a block diagram of an embodiment of interaction between devices reserved to transmit multiple data blocks. Specifically, FIG. 4 shows the source after the transfer of the data block from the control device 410, the DMA controller 430, and the one or more memory devices and / or the source data storage location 446a to the destination data storage location 448a. Depicts the interaction of devices providing storage in performing the transfer of another data block from data storage location 446b to destination data storage location 448b. The items numbered in FIG. 4 generally correspond to the number items in FIG. 3, meaning that they are not different from the control device 310 in FIG. 3, wherein the control device 410 is a CPU (of a computer system or other electronic system), Microcontroller, sequencer, or the like, and may execute instructions 412 to cause a data block transfer by programming the registers in the DMA controller 430 to which the control device 410 is connected. Addressable space 440 is a map of address locations accessible to both control device 410 and DMA controller 430.

In some embodiments, the addressable space 440 may be entirely comprised of a single system memory device (not shown) to which both the control device 410 and the DMA controller 430 are connected. In other embodiments, the addressable space 440 may be comprised of a combination of memory devices and / or buffers in other devices to which both the control device 410 and the DMA controller 430 are connected. For example, both the source data store location 446a and the destination data store location 448b can be located in system memory, and the source data store location 446b and the destination data store location 448a are in a buffer within another device. Can be located.

The control device 410 stores the source data store locations 446a and 446b and the destination data store locations 448a, with corresponding amounts of data to be transmitted and corresponding addresses of the state store locations 444a and 444b. And writing the base addresses of 448b to the corresponding parameter storage locations 443a and 443b to prepare for the multiple transfer execution of the data block. The control device 410 also sends the base address of the parameter storage location 443a to the parameter registers 433 in the DMA controller 430 together with one or more bits that trigger the DMA controller 430 to initiate the data block transfer. Fill in.

In response to this trigger, the DMA controller 430 obtains the base address of both the source data store location 446a and the destination data store location 448a, the amount of data to be transferred, and the base address of the state store location 444a. To access the parameter storage location 443a at the base address programmed into the parameter registers 433. The DMA controller 430 performs the transfer of the data block from the source data store location 446a to the destination data store location 448a and writes the transfer status to the state store location 444a. The DMA controller 430 then stores the parameter storage location to obtain the base address of both the source data store location 446b and the destination data store location 448b, the amount of data to be transferred, and the base address of the state store location 444b. Access 443b. DMA controller 430 then performs the transfer of the data block from source data store location 446b to destination data store location 448b and writes the transfer status to state store location 444b. The control device 410 reads the state store locations 444a and 444b to determine whether the DMA controller 430 writes values to the state store locations 444a and 444b that indicate that the data transfer is complete.

In one embodiment, the base address of the parameter storage location 443a written in the parameter registers 433 is located at a predetermined interval in the chain (the length of the interval programmed or hardwired to the DMA controller 430). Serving as a pointer to the base of one or more parameter storage locations (such as parameter storage location 443a), DMA controller 430 only requires the base address of the initial parameter storage location of this chain, 430 may be repeated throughout this chain until it encounters this final parameter storage location with parameters for data block transmission. In this embodiment, control device 410 may also write a value in parameter registers 433 indicating the amount of parameter storage locations in this chain. However, in another embodiment, each parameter store location may provide the base address of the next parameter store location in the chain of parameter store locations, whereby the parameters to be located at predetermined intervals in the addressable space 440. The need for each parameter storage location in the chain of storage locations can be eliminated. In such an embodiment, the last parameter store location in this chain may provide a value instead of a base address indicating that the last parameter store location in this chain has been reached.

5 is another block diagram of embodiments of interaction between devices reserved to transmit multi-block data. Specifically, FIG. 5 depicts the interaction of a DMA controller with one or more memory devices and / or devices that provide storage in performing the transfer of multiple data blocks. The items numbered in FIG. 5 generally correspond to the number items in FIG. 4, and to some extent not different from FIG. 4, wherein the addressable space 540 includes both a control device (not shown) and the DMA controller 530. Is a map of address locations accessible to.

To some extent similar to FIG. 4, multi-parameter storage locations 543a to 543d are allocated within addressable space 540, and similar to what has been fully discussed in FIG. 4, the DMA controller 530 is responsible for the amount of data to be transferred. And respective parameter storage locations 543a through 543d to obtain base addresses for source data and destination data storage locations along with corresponding base addresses for a state storage location that writes a value indicating a respective transfer status. To access it. However, unlike the embodiments discussed in FIG. 4, FIG. 5 shows that each transfer state is the same location as the single common location to be written by the DMA controller 530, that is, the state store location 544 is stored in the parameter store locations 543a through 553a. Depicts embodiments to be pointed to from 543d). This use of a single state store location allows the control device to monitor multiple transmission states by repeating access to only one location with addressable space 540. In this embodiment, the values written to the state store location 544 by the DMA controller 530 are some form of identification value that allows the control device to distinguish which transfer is completed and / or which transfer is currently in progress. It may further include.

FIG. 5 is also a parameter register 533 which supplies both the base address of the initial and final parameter storage location as a method for triggering both the start of one or more transfers of a data block and a count of how many transfers are in the transport chain. ) Describes the use of. As discussed above, some embodiments may use a predetermined spacing of address spaces between base addresses where each parameter store location is located within an addressable space 540, while other embodiments may use corresponding multiple transmissions to be performed. Pointers can be used within each parameter storage location providing the base address of the next parameter storage location in the chain of parameter storage locations.

6 is another block diagram of embodiments of interaction between devices reserved to transmit multiple data blocks. Specifically, FIG. 6 depicts the interaction of a DMA controller with one or more memory devices and / or devices providing storage in performing the transfer of multiple data blocks (data blocks that are not actually shown for clarity). do. The items numbered in FIG. 6 generally correspond to the number items in FIG. 5, and to some extent not different from FIG. 5, wherein the addressable space 640 is both a control device (not shown) and the DMA controller 630. Is a map of address locations accessible to. To some extent similar to FIG. 5, the multi-parameter storage locations 643a to 643c are allocated within the addressable space 640, and similar to what has been fully discussed in FIG. 5, the DMA controller 630 is responsible for the amount of data to be transferred. And respective parameter storage locations 643a through 643c to obtain base addresses for source data and destination data storage locations along with corresponding base addresses for a state storage location that writes a value indicating a respective transfer status. To access it. However, unlike the embodiments discussed in FIG. 5, FIG. 6 depicts the parameter store locations 643a through 643c allocated within the addressable space 640 at somewhat constant intervals, with pointers to the next parameter store location It is provided within each parameter store location. In performing each transfer, the DMA controller 630 accesses a pointer in the parameter store location 643c to obtain a base address of another parameter store location in which parameter store locations with parameters for the data block transfer. Access the pointer to the next parameter storage location to obtain the base address of the next parameter storage location until a pointer is provided indicating no degrees, at which point the DMA controller 630 stops performing the data block transfer. do.

6 also provides a data transfer state corresponding to parameter store locations 643a and 643c to a common state store location (ie, state store location 644ac), and data transfer corresponding to parameter store location 643b. It illustrates the use of pointers to state store locations to provide state to another state store location (ie, state store location 644b). The use of these separate and common state store locations may prove advantageous in areas where multiple transmissions are involved in the performance of one function by a computer system in which the DMA controller 630 is part, while other transmissions may be within the same computer system. It involves the performance of other functions. In particular, state store locations 644ac and 644b are allocated within devices with other memory devices and / or memory buffers. For example, state store location 644ac may be allocated in system memory to allow the CPU to efficiently monitor the status of corresponding transfers, and state store location 644b may be allocated in a memory buffer provided to another device to Ensure efficient monitoring of the status of the corresponding transmission.

7 is another block diagram of embodiments employing a computer system. Items numbered in FIG. 7 are generally intended to correspond to items numbered in FIG. 2, and in a manner not different from computer system 200 of FIG. 2, computer system 700 may, at least in part, include a CPU ( 710, bus 719, logic 720, bus 749, system memory 740, bus 759, and device 750. As in the case of computer system 200, one of ordinary skill in the art is one of many possible forms of core of computer system 200, and computer system 200 is further comprised of other buses and devices not shown. It will be well understood. Logic 720 is coupled to CPU 710 via bus 719, including providing access to system memory 740 to CPU 710 and controlling CPU 710 in connection with this access. Performing various functions in support of the CPU 710, the logic 720 is also coupled to the system memory 740 via a bus 749 and a memory controller 722 in the logic 720. In addition, logic 720 provides access to other devices that make up computer system 700, such as device 750, which may include bus interface 727 and logic within logic 720. It is connected to the computer system 700 via a bus 759 and a bus interface 757 in the device 750.

The CPU 710 may transmit a block of data from the data storage location 746 allocated in the system memory 740 to the data storage location 766 assigned in the device storage 760 of the device 750. Executes a series of instructions 712 stored in system memory 740 to program 730. The CPU 710 records various parameters of the transfer that will occur at the memory location in the DMA transfer parameter storage location 743 allocated in the system memory 740. Such parameters include data storage locations 746, 766, a value indicating the amount of data to be transferred, and a value indicating that a transmission status will be provided to the DMA transfer status storage location 764 assigned within device storage 760. Although it can do it, it is not limited only to these. The CPU 710 also controls one or more parameter registers 733 in the DMA controller controller 730 as a value specifying the start address of the DMA transfer parameter storage location 743 and as one or more triggers for the transfer to occur. Allows writing to the value in bits. DMA controller 730 then executes the transfer. During the execution of this transfer, the CPU 710 and / or device 750 may determine whether the DMA controller 730 has written a value to the DMA transfer status storage location 764 indicating that the transfer is complete. The storage location 764 can be read one or more times.

The CPU 710 also transfers the data block from the data storage location 768 assigned within the device storage 760 within the device 750 to the data storage location 748 assigned within the system memory 740. Executes a series of instructions 712, etc. The CPU 710 writes various parameters of the transfer to occur in the device transfer parameter registers 768. Such parameters may include, but are not limited to, starting addresses of data storage locations 768 and 748 and values indicative of the amount of data to be transmitted. Device 750 then executes the transmission.

Use DMA controller 730 to transfer data from system memory 740 to device 750, and bus mastering of device 750 to transfer data from device 750 to system memory 740. Using the functionality may provide greater efficiency in the movement of data blocks than would be possible by using only either the DMA controller 730 or the device 750 to perform these two transfers. In this manner, each transfer is performed as one or more write operations via bus 759, using write buffers 728, 758 that the corresponding bus interface 727, 757 can provide. Use of write buffer 728 allows data writes to device storage 760 via bus 759 by DMA controller 730 to be buffered or " posted, " When a portion of the data propagates through device storage 760 via DMA controller 730 may read another portion of data from system memory 740. Thus, use of the write buffer 758 by the bus mastering functions of the device 750 allows data writes to the system memory 740 via the bus 759 by the device 750 to also be “posted”. Thus, when a portion of the data propagates from the write buffer 758 through the bus 759 toward the system memory 740, the device 750 may read another portion of the data from the device storage 760.

In certain embodiments, this use of the combination of the DMA controller 730 and the bus mastering function of the device 750 may result in the CPU 710 executing a series of instructions provided by the device driver corresponding to the device 750. Will be caused by Such a device driver avoids the use of bus mastering functions of device 750 to read data from system memory 740 and avoids the use of DMA controller 730 to read data from device storage 760. Thereby interacting with an operating system that is also executed by the CPU 710 during normal operation of the computer 700 to increase the efficiency of data transfer between the device storage 760 and the system memory 740 in the device 750. have.

8 is a flowchart of an embodiment. At 810, the base address of the source and destination locations of the data to be transferred, the amount of data to be transferred, and the base address of the status location to which the transfer status is to be written are all provided to the DMA controller via DMA registers or other mechanism. The DMA controller is signaled to begin DMA transfer execution and executes the transfer at 820. At 830, when the transfer is executed, the CPU or other device reads the state of the transfer from the state location where the DMA controller will write the state. At 840, another status readout occurs at 830 if the DMA controller has not yet recorded a value at the status location where the status indicating that the transfer has completed has been recorded. Otherwise, if the DMA controller has recorded a value in the status position where the status indicating that the transfer is completed is to be recorded, it ends.

9 is a flowchart of another example of transmission of a data block. At 910, the transfer parameter is the base address of the source and destination locations of the data to be transferred, the amount of data to be transferred, and the base address of the status location to which the transfer status is to be written are all addressable memory, such as system memory or another memory device or buffer. The parameter position is written to the parameter position in the parameter position. At 920, the base address of the parameter location at which the transmission parameters are written is provided to the DMA controller via a DMA register or other mechanism at 910. The DMA controller is signaled to start the transfer execution and executes the transfer at 930. At 940, when the transfer is performed, the CPU or other device reads the state of the transfer from the addressable state location where the DMA controller will write the state. At 950, another status readout occurs at 940 if the DMA controller has not yet recorded a value at the status location where the status indicating that the transfer has completed has been recorded. Otherwise, if the DMA controller has recorded a value in the status position where the status indicating that the transfer is completed is to be recorded, it ends.

10 is a flowchart of an embodiment. At 1010, a set of parameters, such as the base address of the source and destination locations of the data, the amount of data, and the base address of the status locations, is written to the multiple parameter locations for multiple transmissions, each of the multiple transmission locations. Corresponds to each of the plurality of transmissions to be performed. At 1020, the base address of the first of the plurality of parameter positions for which transmission parameters have been written is provided to the DMA controller via DMA registers or other mechanism. The DMA controller is signaled to start execution of the DMA transfer, starts transfer at 1030, and at 1030 a state indicating completion of the DMA transfer is written to the state location corresponding to that transfer at 1030. At 750, if there is an indication of another parameter location as parameters for other transmissions that have not yet been performed, at 1030 the transmission is performed. Otherwise, if there are no more parameter positions corresponding to transmissions that have not yet been performed, it is terminated.

In each of the preceding embodiments, where multiple transmission parameter locations are assigned to support the execution of multiple transmissions, the transmission parameter locations can be used in a circular or "FIFO-like" manner so that the parameter locations are reused repeatedly for new transmissions. There may be variations of the embodiments used as a loop if possible. If the transmission parameter locations employ pointers to point the DMA controller to the base address where a new transmission parameter location can be found, then those pointers point to the point at which the "final" transmission parameter location was the "first" transmission parameter location. Can be used. If the transmission parameter locations do not employ pointers and rely on being located within the addressable space of the memory device (or another device providing storage locations) at predetermined intervals, the DMA controller determines that which transmission parameter location is the An indication of whether it is final in the chain may be provided so that the DMA controller can "loop back" to the first one.

The present invention has been described in connection with preferred embodiments. Those skilled in the art will recognize that many other alternative embodiments, modifications, variations, and uses are possible in light of the above description. Those skilled in the art will appreciate that the present invention may be practiced in support of electronic devices other than a computer system such as audio / video entertainment devices, controller devices in a vehicle, appliances controlled by electronic circuitry.

Claims (15)

A first memory device assigned a source data location having a block of data to be transferred; A second memory device assigned a destination data location for the block of data to be transmitted; A control device coupled to the first and second memory devices and capable of executing machine readable instructions; A DMA controller coupled to the control device and both the first and second devices, the DMA controller writing a value in which the control device indicates a transfer status of a data block from the source data location to the destination data location Has at least one transfer status location base address register which writes a value specifying the base address of the status location Device comprising a. 2. The apparatus of claim 1, wherein the DMA controller writes a parameter in which the control device writes at least a base address of the source data location, a base address of the destination data location, and a data quantity constituting the data block to be transferred. Device with registers. 2. The apparatus of claim 1, wherein the DMA controller has at least one transfer parameter position base address register that writes a value specifying the base address of a parameter position at which the control device obtains a transfer parameter of the data block. 4. The apparatus of claim 3, wherein the parameter location at which the DMA controller obtains the transmission parameter comprises at least the base address of the source data location, the base address of the destination data location, and the data constituting the block of data to be transferred. Device for storing quantities. A first memory device assigned a source data location having a data block to be transmitted in a first transmission; A second memory device assigned a destination data location for the block of data to be transmitted in a first transmission; A control device coupled to the first and second memory devices and capable of executing machine readable instructions; A DMA controller coupled to the control device and both the first and second devices, the DMA controller writing a value specifying a base address of a first parameter location from which the control device obtains a parameter of the first transfer; With transfer parameter position base address register- Device comprising a. 6. The method of claim 5, wherein the first parameter location at which the DMA controller obtains the first transmission parameter is at least a base address of the source data location, a base address of the destination data location, and the And storing the amount of data constituting a data block. 7. The method of claim 6, wherein the first parameter position at which the DMA controller obtains the first transfer parameter further comprises a base address of a first transfer state position at which the control device writes a value indicating the first transfer state. Device for storing. 7. The apparatus of claim 6, wherein the first parameter location from which the DMA controller obtains the first transmission parameter further stores a base address of a second parameter location from which the DMA controller obtains a second transmission parameter. 9. The method of claim 8, wherein the second parameter position at which the DMA controller obtains the second transfer parameter further comprises a base address of a second transfer state position at which the control device writes a value indicating the second transfer state. Device for storing. Writing a first set of parameters for a transfer of a first block of data to be performed by a DMA controller at a first transfer parameter position assigned in a memory device, wherein the parameters for transfer of the first block of data are in a first transfer state. Includes the base address of the location; Writing a base address of the first transfer parameter location into a register of the DMA controller; Triggering the DMA controller to start performing the transfer of the first data block by accessing the first transfer parameter location to obtain the transfer parameter of the data block to be performed; And Accessing the first transfer state location by a DMA controller to determine whether or not a value indicating within the first transfer state location has written a value indicating that the transfer of the first data block is complete; How to include. The method of claim 10, wherein triggering the DMA controller to start performing the transfer of the first data block comprises: Obtaining a base address of a first data source location from which the first data block is read during the transfer of the first data block from the first transfer parameter, wherein the first data source location is assigned in a first memory device; ; Obtaining from the first transfer parameter a base address of a first data destination location to which the first data block is written during the transmission of the first data block, the first data destination location being assigned in a second memory device; ; And Obtaining a value from the first transmission parameter that specifies a data amount consisting of the first data block to be transmitted How to include. 12. The method of claim 10, further comprising accessing the first transmission parameter location to obtain a base address of a second transmission parameter location having a second parameter set for transmission of a second data block. When performed by a processor within an electronic device, causes the electronic device to: Write a first set of parameters for the transfer of a first block of data to be performed by the DMA controller at a first transfer parameter position assigned in the memory device Write a base address of the first transfer parameter position into a register of the DMA controller, wherein the parameter for the transfer of the first data block consists of a base address of a first transfer state position; Triggering the DMA controller to start performing the transfer of the first data block by accessing the first transfer parameter location to obtain the transfer parameter of the data block to be performed, Code for causing a DMA controller to access the first transfer state to determine whether a value indicating within the first transfer state location that the transfer of the first data block has completed is written. The device of claim 13, wherein the electronic device is further: Obtain a base address of a first data source location from which the first data block is read during the transfer of the first data block from the first transmission parameter location, wherein the first data source location is allocated within a first memory device -, Obtain a base address of a first data destination location from which the first data block is written during the transmission of the first data block from the first transmission parameter, wherein the first data destination location is assigned in a second memory device -, Machine-readable medium for obtaining a value from said first transmission parameter that specifies the amount of data for which said first block of data to be transmitted is comprised. 14. The machine-readable medium of claim 13, further comprising accessing the first transmission parameter to obtain a base address of a second transmission parameter location having a second parameter set for transmission of a second data block.

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