JPH06214939A - Dma controller - Google Patents

Abstract

PURPOSE:To attain the coexisting of read/write and to attain transfer by DMA transfer at a time by controlling an input/output bus in accordance with the setting of DMA operation by an operation definition storing means control means. CONSTITUTION:This DMA controller is provided with an operation definition table 1 which is an operation definition storing means, an operation definition table control part 2 which is also the operation definition storing means, and a DMA transfer control part 3. Then, the operation definition table 1 stores DMA operation data such as the source/destination, the read/write, etc., of each transfer by DMA transfer. When the operation definition table control part 2 receives a DMA requirement from CPU, the part 2 temporarily stores DMA operation data by reading the contents of the operation definition table 1 so as to set DMA operation. Furthermore, the DMA transfer control part 3 controls the input/output bus (I/O bus) in accordance with the setting of DMA operation by the operation definition table control part 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used in a system in which, for example, a microcomputer is combined, and controls a DMA transfer between memories in response to a DMA request from a central processing unit (hereinafter referred to as CPU). In particular, the present invention relates to a DMA controller capable of arbitrarily setting a DMA operation.

[0002]

2. Description of the Related Art Conventionally, DMA in this type of system is used.
For the transfer, the data length can be programmed for each DMA channel, the source and destination to which the data is to be read (collected) or written (distributed) are specified by the DMA transfer, and continuous transfer processing using the address automatic increment is performed. It is configured so that the addresses of the memories storing the source / destination are connected on the memory by using the address pointer and the transfer processing is performed in a chained manner.

However, in this case, only the address is operated, and only one read or write of data is performed in one DMA transfer for one channel. Therefore, read and write must be performed in different DMA transfers. Also, since the data length is determined for each DMA channel, it is not possible to perform DMA transfer for different data lengths together.

[0004]

As described above, in the conventional DMA transfer, the read and the write must be performed by different DMA transfers, and the DMA transfer cannot be performed together if the data length is not constant. There was a problem.

An object of the present invention is to set D for one channel.
Enables mixed read / write in MA transfer,
Another object of the present invention is to provide an extremely reliable DMA controller capable of performing a single DMA transfer even if the data length is not constant.

[0006]

In order to achieve the above object, according to the present invention, in a DMA controller for controlling DMA transfer between memories in response to a DMA request from a central processing unit, each transfer is performed by DMA transfer. Operation definition storage means for storing DMA operation data such as source / destination and read / write for each, and D from the central processing unit
When the MA request is received, the contents of the operation definition storage means are read to temporarily store the DMA operation data, and the operation definition storage means control means for setting the DMA operation and the DMA operation setting by the operation definition storage means control means And DMA transfer control means for controlling the input / output bus.

[0007]

Therefore, in the DMA controller of the present invention, when the DMA request from the central processing unit is received, the operation definition storage means control means describes and initializes the source / destination and the DMA operation for each transfer. The DMA operation data is read from the operation definition storage means and temporarily stored therein, and the DMA operation setting of the DMA transfer control means is performed, and the DMA transfer operation control means controls the input / output bus in accordance therewith.

While the DMA transfer control means controls the input / output bus transfer, the operation definition storage means control means reads the next DMA operation data from the operation definition storage means and stores it. Then, when the previous transfer operation in the DMA transfer control means is completed, the operation definition storage means control means sets the stored next DMA operation setting to D.
Similarly to the MA transfer control means, the DMA transfer control means controls the input / output bus, and the operation definition storage means control means reads the next DMA operation data, and sequentially performs DMA transfer.

As described above, DMA for one channel
Since it is possible to arbitrarily set the memory address to be accessed during transfer, read / write can be mixed, and even if the data length is not constant, D
Transfer can be performed by MA transfer.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing a configuration example of a DMA controller according to the present invention. That is, as shown in FIG. 1, the DMA controller of the present embodiment has an operation definition table 1 which is an operation definition storage means, an operation definition table control section 2 which is an operation definition storage means control means, and a DMA.
It is composed of the transfer control unit 3. Here, the operation definition table 1 stores DMA operation data such as source / destination and read / write for each transfer in the DMA transfer.

When the operation definition table controller 2 receives a DMA request from a CPU (not shown), it reads the contents of the operation definition table 1 to temporarily store the DMA operation data and sets the DMA operation. Is.

Further, the DMA transfer control unit 3 inputs / outputs according to the DMA operation setting by the operation definition table control unit 2.
The output bus (hereinafter referred to as I / O bus) is controlled.

FIG. 2 is a block diagram showing a detailed configuration example of the operation definition table control unit 2 in the DMA controller. That is, the operation definition table control unit 2
As shown in FIG. 2, it comprises a table access control unit 5, a table address counter 6, and an internal register 7.

Here, the table access control unit 5 uses C
When a DMA request from the PU is received, a count-up start request is issued to the table address counter 6, and the DMA of the address indicated by the table address counter 6 is issued.
The operation data is read from the operation definition table 4, and the read DMA operation data is stored / stored in the internal register 7. Also, the table address counter 6
When a count-up start request is received from the table access control unit 5, the count-up operation is performed. Further, the internal register 7 is for storing and storing DMA operation data. Next, the operation of the DMA controller of this embodiment configured as described above will be described.

In FIGS. 1 and 2, first, at the time of initialization of a channel, D such as source / destination address for performing DMA transfer, read / write, and data length.
The MA operation data is written in the operation definition table 4.

Next, when the initialization of the channel is completed and a DMA request from a CPU (not shown) is received, the table access control unit 5 causes the table address counter 6 to operate.
A count-up start request is issued to the DMA operation data of the address indicated by the table address counter 6 from the operation definition table 4. Then, the read DMA operation data is stored / stored in the internal register 7, and the I / O bus control operation of the DMA transfer control unit 3 is set according to this data. Upon receiving this setting, the DMA transfer control unit 3 controls the sending of source / destination addresses to the I / O bus and the output of read / write commands.

Also, during this transfer control, the table access control unit 5 causes the table to be transferred to the next DMA from the operation definition table 4.
The operation data is read, and the read DMA operation data is stored / stored in the internal register 7. And
When the previous I / O bus control operation in the DMA transfer control unit 3 ends, the next DMA stored in the internal register 7
The control operation is set and the I / O bus is controlled according to the operation data. A series of these operations are repeated, and at the end of the DMA transfer, the table address counter 6 which has continued counting up returns to the initial state.

As described above, the DMA controller of this embodiment has the operation definition table 1 for storing the DMA operation data such as the source / destination and the read / write for each transfer in the DMA transfer, and the DMA request from the CPU. When the operation is received, the contents of the operation definition table 1 are read and DM
From the operation definition table control unit 2 which temporarily stores the A operation data and sets the DMA operation, and the DMA transfer control unit 3 which controls the I / O bus according to the DMA operation setting by the operation definition table control unit 2. It is composed.

Therefore, since the DMA operation and data length can be set for each transfer, the DMA for one channel can be set.
In the transfer, read / write can be mixed. Further, since the transfer data length can be set for each transfer destination, even if the data length is not constant, it is possible to perform transfer by one DMA transfer.

Further, since the next DMA operation is pre-read from the operation definition table 1 and temporarily stored, the DMA
Since the operation setting time during the transfer time can be almost ignored, it is possible to speed up the DMA transfer.

[0022]

As described above, according to the present invention, D
In the MA transfer, the operation definition storing means for storing the DMA operation data such as the source / destination and the read / write for each transfer, and the DMA request from the central processing unit, the contents of the operation definition storing means are read to perform the DMA. An operation definition storage means control means for temporarily storing operation data and setting a DMA operation, and a DMA transfer control means for controlling the input / output bus according to the DMA operation setting by the operation definition storage means control means are provided. Since it is configured, it is possible to provide a highly reliable DMA controller that enables mixed read / write in DMA transfer for one channel and can perform transfer in one DMA transfer even when the data length is not constant. .

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a DMA controller according to the present invention.

FIG. 2 is a block diagram showing a detailed configuration example of an operation definition table control unit in the embodiment.

[Explanation of symbols]

1 ... motion definition table, 2 ... motion definition table control unit,
3 ... DMA transfer control unit, 5 ... table access control unit,
6 ... table address counter, 7 ... internal register.

Claims (1)

[Claims] 1. A DMA controller for controlling DMA transfer between memories in response to a DMA request from a central processing unit, wherein DMA operation data such as source / destination and read / write for each transfer is transferred by DMA transfer. Operation definition storage means for storing the operation definition storage means for receiving the DMA request from the central processing unit, reading the contents of the operation definition storage means, temporarily storing the DMA operation data, and setting the DMA operation. A DMA controller comprising: control means; and DMA transfer control means for controlling the input / output bus according to the DMA operation setting by the operation definition storage means control means.