KR20050078064A - Time delaying buffer control device for multi path signal combining on a receiver of a base transceiver station and the method thereof - Google Patents

Abstract

A read pointer buffer for storing read pointer information for reading data of a FIFO time adjustment buffer divided into block memories capable of processing data having a minimum spreading coefficient using a single port memory; A write pointer buffer for storing write pointer information for writing data to the time adjustment buffer; A chain list buffer for storing a chain list usable by circularly connecting each block memory of the time adjustment buffer; A base station comprising a time adjusting buffer control unit for changing the chain list allocating the block memory of the FIFO time adjusting buffer so as to efficiently use the memory when switching to or decompressing the compression mode due to the reduction of the spreading coefficient. An apparatus for controlling time adjustment buffer for multipath signal combining in a receiver and a control method using the same.

Description

Time delaying buffer control device for multi path signal combining on a receiver of a Base Transceiver Station and the method

The present invention relates to a control apparatus and a control method of a time adjustment buffer for multipath signal combining in a base station receiver. More particularly, the memory can be efficiently used and the spreading coefficient in the compression mode can be reduced by reducing the spreading coefficient. The present invention relates to a control apparatus and a control method capable of efficiently processing a change in the amount of data due to a change in the amount of data.

The FIFO memory required for combining demodulated symbols of a multipath signal in a third generation mobile communication system or a mobile communication system for a different high data rate is implemented with independent timing adjustment buffers of the same size at each finger. Thus, the number of time adjustment buffers increases with the increase of fingers to increase the effectiveness of efficient soft handoff and multipath diversity. In particular, in the asynchronous WCDMA communication system, the amount of data received during a predetermined period of time in the compression mode due to the spreading factor decreases, so that the memory of the FIFO time adjustment buffer must be variable according to the user.

In general, a rake receiver combines the received signals using a path diversity effect to increase the reception performance of signals received at different times through different paths from the transmitter on a wireless channel. The rake receiver has a structure in which the respective fingers assigned by the multipath positions are connected in parallel and combined. Each finger serves to independently demodulate different multipath signals of the direct sequence signal. This independently received signal MRC (Maximum Ratio Combining) to maximize the signal-to-noise ratio of the receiver.

In third generation mobile communication schemes such as UMTS (Universal Mobile Telecommunications System) or mobile communication systems for other high data rates, there are more symbols to be stored for the high data rates. Thus, the size of the time adjustment buffer, which is a kind of FIFO memory for combining, is significantly increased. In addition, the number of fingers is increased to increase the effectiveness of efficient soft handoff and multipath diversity. For this purpose, since the same size of time adjustment buffers are independently implemented in each finger, the size of the FIFO memory and the number of time adjustment buffers according to the increase of the finger increase, thereby increasing the size of the rake receiver and the structure.

In addition, in the asynchronous WCDMA system, the amount of data to be transmitted is increased up to twice in frame units compared to the amount of data normally transmitted in the compressed mode due to the reduction of the spreading factor. For this purpose, the size of the allocated FIFO memory for each user having a plurality of paths should be variable.

Therefore, in order to implement the rake receiver in an efficient hardware, an efficient structure and a control method of a time adjustment buffer that can be applied constantly regardless of the compression mode due to the reduction of the spreading coefficient are required.

A base station receiver in a WCDMA system receives spread signals in multiple paths. Among them, the data symbol of the received signal that arrives first must be stored in a buffer in the receiver for a predetermined time to be combined with the received signals that arrive later.

The time adjustment buffer is a space for storing data for a predetermined time for combining. In addition to the basic storage space for this purpose is configured with additional free space to prevent over-run in the compression mode by the reduction of the diffusion coefficient.

In the normal case, the amount of data is determined depending on the spreading factor. Therefore, only the fixed buffer size is allocated and used. However, in the compression mode due to the reduction of the spreading factor, twice as much buffer is allocated to the user as in the normal case. Therefore, efficient use of the time adjustment buffer is not possible. That is, the user who supports the compression mode by reducing the spreading coefficient increases the hardware size of the Rake receiver by continuing to use the time adjustment buffer twice as large as the original required data amount even when the mode is released.

As such, in the case of independently implementing time-adjusting buffers of the same size in each finger, the size of the buffer is greatly increased, thereby increasing the size of hardware. In addition, even when the time adjustment buffer is divided into several block memories, the memory is inefficiently used in the compression mode due to the reduction of the spreading factor.

It is an object of the present invention to provide a control apparatus and a control method capable of efficiently using a time adjustment buffer required for combining in a compression mode and a normal mode due to a reduction of the spreading coefficient.

It is another object of the present invention to provide a time adjustment buffer control apparatus and a control method capable of reducing the overhead of the time adjustment buffer and enabling a simple user interface.

Time adjustment buffer control apparatus according to the present invention for achieving the above object is conceptually controlled by controlling the FIFO time adjustment buffer of the base station receiver into a plurality of memories, and through the corresponding flag and register even in the compression mode by reducing the spreading factor It is characterized by optimal control.

The apparatus for controlling time adjustment buffer according to the present invention is a read pointer buffer in which read pointer information for storing data of a FIFO time adjustment buffer divided into block memories capable of processing data having a minimum spreading coefficient using a single port memory is stored. Wow; A write pointer buffer for storing write pointer information for writing data to the time adjustment buffer; A chain list buffer for storing a chain list usable by circularly connecting each block memory of the time adjustment buffer; When switching to compression mode or decompression by reducing the spreading coefficient, the time adjustment buffer control unit controls the efficient use of memory by changing the chain list allocating the block memory of the FIFO time adjustment buffer. It is characterized by.

A feature of the detailed configuration of the time adjustment buffer control apparatus according to the present invention is that the time adjustment buffer control unit uses the position register of the start block memory to determine the initial position of the block memory to first read / write data for any one path. A path checking unit; A read / write pointer controller configured to read a value stored in a read / write pointer buffer for the initial path identified through the initial path checker or to store changed pointer information; A chain list read control unit for reading information related to the block memory from the chain list buffer or storing a changed chain list according to the information read by the read / write pointer control unit; A pointer calculator for calculating a next pointer according to values provided from an initial path checker, a read / write pointer control unit and a chain list read control unit; And an overflag control unit that receives a processing result from the pointer calculator and outputs a signal for controlling the over flag.

Hereinafter, a time adjustment buffer control apparatus and a control method thereof according to the present invention will be described with reference to the accompanying drawings.

1 is a block diagram showing the configuration of a time adjustment buffer control apparatus according to the present invention. A read pointer buffer 31 for storing read pointer information for reading data of a FIFO time adjustment buffer divided into a block memory capable of processing data having a minimum spreading coefficient using a single port memory; A write pointer buffer 32 for storing write pointer information for writing data to the time adjustment buffer 10; A chain list buffer 33 for storing a chain list which can be cyclically connected to each block memory of the time adjustment buffer 10; When switching to a compression mode or decompressing by reducing a spreading coefficient, the time adjusting buffer control unit 20 controls to change the chain list allocating the block memory of the FIFO time adjusting buffer so that the memory can be used efficiently. It is made to include.

The time adjustment buffer control unit 20 includes: an initial path checking unit 21 for determining a location of the block memory to first read / write data for any one path using a location register of the start block memory; A read / write pointer controller 22 for reading a value stored in the read / write pointer buffers 31 and 32 for the initial path identified through the initial path checker 21 or storing changed pointer information; A chain list read control unit 23 for reading information related to the block memory from the chain list buffer 33 or storing the changed chain list according to the information read by the read / write pointer control unit 22; A pointer calculator 24 for calculating the next pointer according to values provided from the initial path checking unit 21, the read / write pointer control unit 22 and the chain list reading control unit 23; The overflag control unit 25 receives the processing result from the pointer calculator 24 and outputs a signal for controlling the over flag.

In the present invention, the FIFO time adjustment buffer is divided into a certain unit called a block memory to process all users in order to efficiently change the storage space in the compression mode by reducing the spreading coefficient. That is, one block memory is a storage space in which a user can use data required to use the minimum spreading coefficient having the smallest amount of data. Accordingly, the number of block memories to which one path is allocated depends on the minimum spreading coefficient. For example, in an asynchronous wideband code division multiple access (WCDMA) system, one block memory is space for storing data with a minimum spreading factor of 64. If the minimum spreading factor is 4, 16 block memories are allocated for a user. It is possible. When the minimum spreading factor is less than 64 or in the compression mode due to the spreading factor reduction, several block memories are allocated to one path, and these block memories are connected to each other in a circular structure. The allocated block memory for each path remains unchanged except for the case in which additional block memory is allocated in the compression mode due to the spreading factor reduction.

2 is a flowchart illustrating a process of a time adjustment buffer control method according to the present invention. It is a feature of the present invention to enable optimal control of memory even in compression mode. Therefore, for convenience of operation, a description is made using one flowchart, but whether or not the compression mode is generated in the form of an interrupt, and progress is not necessarily performed in the order of the flowchart.

The location of the block memory to first read / write the data for any one path is determined using the location register of the starting block memory (S44), and the corresponding block memory chain is reached until the end of the corresponding block memory is reached (S6). The next block memory pointed to by the list (Chain List) is moved (S7) to read / write data (S5).

The compression mode flag due to the spreading factor reduction can be cleared in hardware when the data is first written to the block memory, and the flag is set separately for IN / OUT. In compression mode due to the reduction of the spreading factor (S1), the corresponding flag is set at the position corresponding to the end block memory (S2), and at the same time, the chain list is changed so that the allocated block memory can be doubled. (S3). At this time, the hardware reads and writes data while moving the block memory with reference to the changed chain list and the start / end / reference block memory.

In the case of the reference block memory, it should point to the starting block memory before the block memory is expanded at the IN point of the compression mode due to the spreading factor reduction. At the time point S8 at which the compression is released, the first block memory among the extended block memories, that is, the block memory indicated by the initial end block memory during the compression mode, must be included. Therefore, the FIFO memory is always located in a fixed position, that is, in the end block memory before expansion, and the flag is also set in the position of the initial end block memory in the compression mode due to the spreading factor reduction. ). In other words, when released from the compression mode due to the reduction of the spreading factor, the block list is newly released and the chain list is changed to use the first used block memory as is (S10), thereby efficiently managing each block memory resource. You can do it.

3 is an embodiment of the allocation of the multi-block memory in the compression mode by reducing the spreading coefficient for one path. An example of the change of the chain list and the setting position of the flag for one path at the time of IN / OUT of the compression mode due to the spreading coefficient reduction is shown.

To read / write data to the FIFO time adjustment buffer, the start block memory position, end block memory position for one path, and the compression mode flag due to the spreading factor reduction at read / write time are set. In this case, information about a location of a reference block memory to be referred to is needed. The following is a list of chains used for cyclic linking of multi-block memory and the flags used in IN / OUT of compression mode due to the reduction of spreading factor. When the minimum spreading factor is 16 in the base station receiver of the asynchronous WCDMA system, four block memories are allocated as shown in FIG. 3. If the four block memories are # 0, # 2, # 4, and # 5, the chain list of the four block memories has # 2, # 4, # 5 and # 0, respectively, to have a ring-shaped circular structure. . Looking at the cycle, the chain list assigned to memory # 0 points to # 2 and moves to block memory # 2. After that, the chain list specified in # 2 points to # 4, and the block list moves to block memory # 4. In this manner, the circulation is performed as # 0 → # 2 → # 4 → # 5 → # 0. In addition, the positions of the start / end / reference block memories have # 0 / # 5 / # 0, respectively.

When the compression mode is IN with the spreading factor decreasing to 8, the amount of data is further doubled. Therefore, four more blocks # 1, # 3, # 6, and # 7 should be allocated. As a result, the position (# 0 / # 3 / # 0) of each end / reference block memory is also changed. The compression mode IN flag by reducing the spreading coefficient may configure a circular connection of the extended block memory by setting the existing end block memory location # 5.

In case of the compression mode OUT in which the spreading factor is reduced back to 16, the additionally allocated block memories of # 1, # 3, # 6, and # 7 are released. The location of the reference block memory points to # 1, which is the first of the extended block memory. In addition, the position of the flag at the time of compression mode IN / OUT is the same as block memory # 5 which is an initial end block memory.

In the present invention, the FIFO time adjustment buffer can be implemented using a single port memory that is about half the size of the dual port memory. Accordingly, the clock used is divided into clock 0 / clock 1. That is, clock 0 performs operations related to reading and controlling the buffer, and clock 1 performs writing and control related to the buffer. Each user has a buffer that manages the read and write pointers of the time adjustment buffer used, and a chain list buffer associated with each block memory. The FIFO time adjustment buffer control verifies that it is the initial path for that path, determines whether to get its value from the read / write pointer buffer, simultaneously reads the read and write pointers and the chain list, and reads and writes the FIFO time adjustment buffer. do. Based on each data read, the next pointer value is stored in the read and write pointer buffers.

By using this FIFO time adjustment buffer, the time adjustment buffer can be used efficiently without wasting according to the amount of data due to the spreading factor change. Therefore, the size of the buffer can be greatly reduced, and it is convenient to use by checking and using an empty block memory in terms of user interface, and storing and storing data necessary for control.

As described above, the time adjustment buffer control apparatus and the control method according to the present invention can use the memory efficiently by using an indirect memory indexing method. In addition, in the compression mode due to the reduction of the diffusion coefficient, it is possible to efficiently process the variation of the data amount due to the change of the diffusion coefficient.

1 is a block diagram showing the configuration of a time adjustment buffer control unit according to the present invention.

2 is a flowchart illustrating a process of a time adjustment buffer control method according to the present invention.

3 is an exemplary memory allocation diagram according to an implementation of the present invention.

Claims (4)

A read pointer buffer for storing read pointer information for reading data of a FIFO time adjustment buffer divided into block memories capable of processing data having a minimum spreading coefficient using a single port memory; A write pointer buffer for storing write pointer information for writing data to the time adjustment buffer; A chain list buffer for storing a chain list usable by circularly connecting each block memory of the time adjustment buffer; And a time adjustment buffer control unit for changing the chain list for allocating the block memory of the FIFO time adjustment buffer so that the memory can be used efficiently when switching to compression mode or decompression by reducing the spreading coefficient. A time adjustment buffer control device for multipath signal combining in a base station receiver. The method of claim 1, wherein the time adjustment buffer control unit, An initial path checking unit for determining a location of a block memory in which data is first read / written for any one path using a location register of a start block memory; A read / write pointer controller configured to read a value stored in a read / write pointer buffer for the initial path identified through the initial path checker or to store changed pointer information; A chain list reading controller for reading information related to the block memory from a chain list buffer or storing a changed chain list according to the information read by the read / write pointer controller; A pointer calculator for calculating a next pointer according to values provided from the initial path checker, the read / write pointer control unit and the chain list read control unit; And an overflag control unit for receiving a processing result from the pointer calculator and outputting a signal for controlling the over flag. Setting a flag according to compression mode and changing a chain list; determining a location of a block memory to first read and / or write data to a path using a location register of a starting block memory; ; A method of controlling time adjustment buffers for multipath signal combining in a base station receiver comprising moving a block memory with reference to a chain list until a corresponding block is completed, and performing data reading and / or writing. The method of claim 3, wherein In the compression mode, a time adjustment buffer control method for multipath signal combining in a base station receiver, characterized in that a flag is set to extend a block memory and a chain list is changed.