KR20040049516A - Apparatus for detecting synchronous signal - Google Patents

Abstract

PURPOSE: A device for detecting a synchronous signal is provided to reduce a synchronous detecting error by considering a specialized bit field, which is restricted by a characteristic of the DAB(Digital Audio Broadcasting) audio, as well as a synchronous-word of a header on a DAB audio frame. CONSTITUTION: A shift register(610) shifts/stores the bit-word received from a viterbi decoder(550). A counter(620) generates a cyclic signal of a bit or a word cycle by accumulating the bit-word inputted from the shift register. A synchronous detector(630) detects the sync-word by examining a plurality of bit fields inputted from the shift register depending on the cyclic signal inputted from the counter.

Description

Synchronization signal detection device {APPARATUS FOR DETECTING SYNCHRONOUS SIGNAL}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for detecting synchronization signals, and more particularly, to detecting synchronization of digital audio broadcasting (DAB) audio data, as well as a sync bit string of a DAB audio bitstream. A synchronization signal detection apparatus having improved detection performance by detecting synchronization in consideration of the bits of a specific field.

1 is a diagram illustrating a structure of a general DAB audio bitstream. Referring to this description, a structure of a DAB audio bitstream includes a header field indicating information for controlling decoding of a DAB audio bitstream; Cyclic Redundancy Check (CRC) fields for checking errors in DAB audio bitstreams, bit allocation fields for variable allocation of bits depending on importance on frequency bands, and audio signals in the time domain A scale factor field for limiting a dynamic range of the subband, a subband sample field for storing a sample value of a subband obtained by dividing a frequency band according to a sampling frequency, and a scale Program management that records information about the cyclic redundancy check field for factors and information directly related to audio data (such as song information such as singers and titles) Data (Program Associated Data; PAD) field, and consists of a cyclic redundancy check field for the scale factor.

The structure of the above-described DAB header field will be described in more detail as follows.

Firstly, the sync bit string field contains a sync signal indicating the start of a DAB audio frame and is composed of twelve '1' bits. A 1-bit identifier (ID) field is used to identify the MPEG algorithm in which the audio signal is encoded, where 1 indicates that the MPEG-1 algorithm is used, and 0 indicates lower sampling frequency extension of the MPEG-2 algorithm. ) Is used. The 2-bit Layer field is a field indicating an MPEG layer used for encoding, and only 10 corresponding to layer 2 is used in DAB audio. The 1-bit protection bit field indicates whether additional information to be used for error detection and error concealment is included. In DAB audio, additional information is included and fixed to 0. The 4-bit bitrate index field indicates the bit rate used under each sampling frequency. As shown in FIG. 2, 0000 and 1111 are not used for the sampling frequencies of 24 kHz and 48 kHz. The two-bit sampling frequency field, combined with the ID field, represents the sampling rate of the audio sample. In DAB audio, the sampling frequency field is fixed to 01 equally at the 24 kHz and 48 kHz sampling frequencies. One-bit padding bit indicates whether additional slots are used to adjust the average bit rate. In the case of DAB audio, the additional slots are not required and are fixed to zero. The 1-bit private bit field is a bit for personal use and is not used for DAB audio. A mode field of 1 bit represents a channel used for encoding, as shown in FIG. 3. A 2-bit mode extension field indicates from which subband the joint stereo mode is used. A 1-bit copyright field indicates whether or not DAB audio is protected. An original / copy field of 1 bit indicates whether or not the DAB audio is original. Finally, the 1-bit emphasis field indicates the type of de-emphasis used for MPEG audio decoding, and is fixed to 00 since no emphasis is used in DAB audio.

FIG. 4 is a diagram illustrating a conventional method for detecting synchronous MPEG audio data, and accordingly, detection is performed by using a fact that intervals between frames are constant under a fixed sampling frequency. When the synchronization is detected three or more times at regular intervals, the general MPEG audio synchronization signal detecting device determines that the synchronization is correctly set and starts decoding. Since a general MPEG audio sync signal detecting apparatus determines that a sync signal is detected when 12 bits of '1' are detected, an error of detecting the same bit pattern in the MPEG audio bit stream as a sync signal may occur, which causes MPEG audio. There is a problem that the decoding process of the decoder is delayed.

In addition, to solve this problem, as disclosed in Korean Patent Application No. 87128, an MPEG audio frame synchronization detection method using a sync bit string in a header of an MPEG audio frame and information characteristics of a specific field has been proposed. However, there is a problem that it is inefficient to apply to the synchronization detection of DAB audio frames.

The present invention devised to solve the above problems, in detecting the synchronization of the DAB audio frame, the existing synchronization by considering not only the synchronization bit string of the header of the DAB audio frame but also a specific bit field limited by the characteristics of the DAB audio frame It is an object of the present invention to provide a synchronization signal detection apparatus for reducing a synchronization detection error compared to a detection method.

1 is a diagram illustrating a structure of a general DAB audio bitstream;

2 is a table showing values of a bitrate index field according to a 24 kHz / 48 kHz sampling frequency.

3 is a table showing a value of a mode field in a DAB audio frame header,

4 is a diagram illustrating a conventional method of detecting synchronization of MPEG audio data;

5 is a block diagram showing a general digital audio broadcasting receiver to which the synchronization signal detecting apparatus of the present invention is applied.

6 is a block diagram showing a synchronization signal detection apparatus according to an embodiment of the present invention;

7 is an exemplary view showing a sync detector mounted in a sync signal detecting apparatus according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

510: ADC520: digital front-end

530: converter / demodulator 540: time deinterleaver

550: Viterbi decoder 560: MPEG audio decoder

In order to achieve the above object, the synchronization signal detecting apparatus of the present invention comprises an analog-to-digital converter, a digital front-end, a converter / demodulator, a time deinterleaver, a Viterbi decoder, and an MPEG audio decoder. A shift register configured to receive and shift a bit string from a Viterbi decoder; A counter for accumulating a bit string input to the shift register to generate a periodic signal in a byte or word period; And a synchronization detector for detecting a synchronization bit string by examining a plurality of bit fields input from the shift register according to the period signal input from the counter.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

First, FIG. 5 is a block diagram showing a general digital audio broadcast receiver to which a synchronization signal detection apparatus of the present invention is applied. The digital audio broadcast receiver of the present invention is an analog-to-digital converter (ADC). 510, digital front-end 520, converter / demodulator 530, time deinterleaver 540, Viterbi decoder 550, and MPEG audio decoder 560.

The ADC 510 converts a signal received from an antenna (not shown) into a digital signal and outputs the digital signal to the digital front-end 520 described later.

In addition, the digital front-end 520 is responsible for tuning the digital signal input from the ADC 510 and outputting the converted / demodulator 530 to be described later.

The transform / demodulator 530 receives the output signal of the digital front-end 520 and demodulates the signal through a fast Fourier transform (FFT) and differential demodulation process, and describes a demodulated signal later. It serves to output to the deinterleaver (540).

In addition, the time deinterleaver 540 receives the output signal of the converter / demodulator 530 and performs a deinterleaving process, and then outputs it to the Viterbi decoder 550 described later.

On the other hand, the Viterbi decoder 550 receives the output signal of the time deinterleaver 540 and performs channel decoding, and then outputs it to the MPEG audio decoder 560 which will be described later.

In addition, the MPEG audio decoder 560 receives the output signal of the Viterbi decoder 550 and restores the output signal to the PCM signal.

Referring to the operation of the above-described digital audio broadcasting receiver, first, a signal received from an antenna is converted into a digital signal by the ADC 510 and separated into an I / Q signal of a baseband. Subsequently, the demodulated signal through fast Fourier transform (FFT) and differential demodulation in the converter / demodulator 530 is restored to an audio signal through a DAB audio decoder after channel decoding. In this process, a synchronization signal is required to synchronize.

6 is a block diagram illustrating a synchronization signal detection apparatus according to an embodiment of the present invention. The synchronization signal detection apparatus of the present invention includes a shift register 610, a counter 620, and a synchronization detector 630. .

The shift register 610 receives and shifts and stores a bit string from the Viterbi decoder 550, and outputs the stored bit string to the sync detector 630 which will be described later.

In addition, the counter 620 accumulates a bit string input to the shift register 610 to generate a periodic signal in a byte or word period, and then to the sync detector 630 which describes the periodic signal. It plays a role of outputting.

On the other hand, the sync detector 630 detects a sync bit string by checking a plurality of bit fields input from the shift register 610 according to the periodic signal input from the counter 620, and detects a sync detection result. It plays a role of outputting.

FIG. 7 is an exemplary view illustrating a sync detector 630 mounted in a sync signal detecting apparatus according to an embodiment of the present invention.

The first inverter 701 receives the second bit of the layer field among the plurality of bit fields input from the shift register 610, inverts the second bit, and outputs the result value. Here, the second bit of the layer field refers to the lower bit of the layer field of the MPEG audio frame header.

In addition, the second inverter 702 receives a protection bit (protection_bit) among the plurality of bit fields input from the shift register 610, inverts the result, and outputs the result value.

Meanwhile, the XOR gate 703 receives a plurality of bits of a bit_rate index field among the plurality of bit fields input from the shift register 610, performs an XOR operation, and then outputs the result value. It plays a role.

In addition, the third inverter 704 receives the first bit of the sampling frequency field among the plurality of bit fields input from the shift register 610, inverts the result, and outputs the result value. do.

Meanwhile, the fourth inverter 705 receives and inverts a padding bit (padding_bit) of the plurality of bit fields input from the shift register 610, and outputs the result value.

In addition, the fifth inverter 706 receives the first bit of the emphasis field from among the plurality of bit fields input from the shift register 610, inverts it, and outputs the result value. .

Meanwhile, the sixth inverter 707 receives the second bit of the emphasis field from among the plurality of bit fields input from the shift register 610, inverts the second bit, and outputs the result value. .

In addition, the AND gate 708 may include two bits of a synchronization bit string (DAB syncword), a first bit of a layer field, and a sampling frequency field among a plurality of bit fields input from the shift register 610. The first bit, an output signal of the first inverter 701, an output signal of the second inverter 702, an output signal of the XOR gate 703, an output signal of the third inverter 704, the first signal 4 An output signal of the inverter 705, an output signal of the fifth inverter 706, and an output signal of the sixth inverter 707 are input, and a Viterbi sync signal is received from the counter 620. It receives an input, performs an AND operation with a plurality of input signals, and outputs the result as the sync detection signal.

The operation of the synchronization signal detection apparatus of the present invention described above is as follows.

First, the sync bit string (syncword) in the header of the MPEG audio frame is composed of 12 bit strings. In the case of a DAB audio frame, the layer field of the header field is always fixed to a value of 10, and the protection field is limited to zero. And since the MPEG algorithm to be used for decoding the audio data is already determined by the ID field, the sampling frequency field is always fixed to a value of 01. In addition, in the case of DAB audio frames, the padding bit field value is fixed to 0 because only sampling frequencies of 24 kHz and 48 kHz are used. Since the DAB audio decoder does not use de-emphasis, the emphasis field is also fixed to a value of 00, and the bitrate index field cannot have values of 1111 and 0000.

Bits fixed to a value of 1 in the bit field of the shift register 610 shown in FIG. 7 are input to an AND gate 708, and bits fixed to a value of 0 are assigned to a plurality of inverters 701. And input to the AND gate 708 via 702,704-707. In addition, four bits are input to the AND gate 708 via the XOR gate 703 by the exception rule of the bit rate index field. The AND gate 708 is activated by a Viterbi sync signal periodically generated from the counter 620 to output a sync bit string detection result.

The additional regularity of the DAB audio frame header field as described above is additionally reflected in the sync bit string detection to increase the success rate of the sync signal detection, thus reducing the delay of the decoding process due to the frame sync detection delay error. Can be.

As described above, the present invention described above can be substituted, changed, and changed in various ways without departing from the technical spirit of the present invention by those skilled in the art. It is not limited to the drawings shown.

In the synchronization detection of a DAB audio frame, the present invention reduces the frame synchronization detection error of a DAB audio decoder by considering not only the synchronization bit string in the DAB audio frame header but also a specific bit field fixed due to the characteristics of the DAB audio bit string. There is an advantage of reducing the decoding delay of the DAB audio decoder due to the synchronization detection error.

Claims (5)

A digital audio broadcast receiver comprising an analog to digital converter, a digital front-end, a conversion / demodulator, a time deinterleaver, a Viterbi decoder, and an MPEG audio decoder, A shift register configured to receive and shift a bit string from the Viterbi decoder; A counter for accumulating a bit string input to the shift register to generate a periodic signal in a byte or word period; And A synchronization detector for detecting a synchronization bit string by examining a plurality of bit fields input from the shift register in accordance with the period signal input from the counter Synchronization signal detection apparatus comprising a. The method of claim 1, wherein the sync detector, A first inverter that receives and inverts a second bit of a hierarchical field among a plurality of bit fields input from the shift register; A second inverter configured to receive a protection bit from among the plurality of bit fields input from the shift register and to invert it; A third inverter that receives and inverts a first bit of a sampling frequency field among a plurality of bit fields input from the shift register; A fourth inverter that receives and inverts padding bits among a plurality of bit fields input from the shift register; A fifth inverter that receives and inverts the first bit of an emphasis field among the plurality of bit fields input from the shift register; And A sixth inverter that receives and inverts the second bit of the emphasis field among the plurality of bit fields input from the shift register and outputs a result value; Synchronization signal detection apparatus comprising a. The method of claim 1, wherein the sync detector, An XOR gate that receives a plurality of bits of a bit rate index field among a plurality of bit fields input from the shift register and performs an XOR operation Synchronization signal detection apparatus comprising a. The method of claim 2, wherein the sync detector, An XOR gate that receives a plurality of bits of a bit rate index field among a plurality of bit fields input from the shift register and performs an XOR operation Synchronization signal detection apparatus comprising a. The method of claim 4, wherein the sync detector, A sync bit string, a first bit of a hierarchical field, and a second bit of a sampling frequency field are input from a plurality of bit fields input from the shift register, and an output signal of the first inverter, an output signal of the second inverter, and an XOR are input. Receiving an output signal of a gate, an output signal of the third inverter, an output signal of the fourth inverter, an output signal of the fifth inverter, and an output signal of the sixth inverter, and receiving a Viterbi synchronization signal from the counter. And an AND gate having a plurality of input signals and performing an AND operation, and outputting the result as the synchronization signal. Synchronization signal detection apparatus comprising a.