KR20040009187A - Method of manufacturing microchip - Google Patents

Method of manufacturing microchip Download PDF

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Publication number
KR20040009187A
KR20040009187A KR1020020043033A KR20020043033A KR20040009187A KR 20040009187 A KR20040009187 A KR 20040009187A KR 1020020043033 A KR1020020043033 A KR 1020020043033A KR 20020043033 A KR20020043033 A KR 20020043033A KR 20040009187 A KR20040009187 A KR 20040009187A
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South Korea
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microchip
pdms
micro chip
sio
deposited
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KR1020020043033A
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Korean (ko)
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KR100492284B1 (en
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공진
강충무
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주식회사 옵트론-텍
김용성
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274Photolithographic processes
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/004Photosensitive materials
    • G03F7/038Macromolecular compounds which are rendered insoluble or differentially wettable
    • G03F7/0382Macromolecular compounds which are rendered insoluble or differentially wettable the macromolecular compound being present in a chemically amplified negative photoresist composition
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Micromachines (AREA)

Abstract

PURPOSE: A method for fabricating a micro chip is provided to eliminate difficulties in a fabricating process such as etching junction by using a molding method, and to remove bad influence upon a flow of fluid by performing silanol group replacement if a KOH solution passes through a fine flow path. CONSTITUTION: A wafer(1) is coated with negative photoresist and a soft baking process is performed. A photomask(5) is disposed on the wafer coated with the negative photoresist and the photomask is exposed to ultraviolet(7) for a predetermined interval of time. Photoresist of a substrate is developed to complete an embossment mold(9) by using developer. Polydimethlysiloxane(PDMS)(11) is injected to the embossment mold so as to be solidified. The solidified PDMS is released to obtain the upper portion(17) of a micro chip. A SiO2 thin film is deposited on the PDMS plate to form the lower portion of the micro chip. SiO2 is deposited in the intagliated part(13) of the upper portion of the micro chip. The upper portion of the micro chip having the deposited SiO2 is attached to the lower portion of the micro chip to complete the micro chip.

Description

마이크로칩 제조방법.{METHOD OF MANUFACTURING MICROCHIP}Microchip manufacturing method. {METHOD OF MANUFACTURING MICROCHIP}

본 발명은 마이크로칩의 제조방법에 관한 것으로, 특히 반도체공정 중 사진공정을 이용하여 미세유로를 제작하는 단계와 PECVD법을 이용하여 SiO2박막을 증착하여 접합하는 단계로 이루어진 마이크로칩의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a microchip, and more particularly, to a method for manufacturing a microchip, comprising the steps of fabricating a microchannel using a photolithography process in a semiconductor process and depositing and bonding a SiO 2 thin film using a PECVD method. It is about.

최근 합성화학과 생명과학의 발전으로 신약개발이나 진단 등의 분야에서 분석해야 하는 표적물질의 증가를 가져오게 되었고, 이에 따라 고가의 시약이나 시료가 다량으로 필요하게 되어 극미량 분석을 통한 비용 절감의 필요성이 높아지고 있다.Recent advances in synthetic chemistry and life sciences have led to an increase in target materials that need to be analyzed in new drug development and diagnostics, and as a result, expensive reagents and samples are required in large quantities, which leads to the need for cost reduction through trace analysis. It is rising.

극미량의 시료나 시약을 다루는 일의 비중이 증가하면서 각광받게 된 것이 실험실칩(lab-on-a-chip) 기술이다. 실험실칩은 반도체 분야에서 널리 사용되는 사진식각인쇄(photolithography)기술이나 미세 가공 기술(micromachining)을 이용하여 유리, 실리콘 또는 플라스틱으로 된 수 ㎠ 크기의 칩 위에 여러 가지 장치들을 집적시킨 화학 마이크로 프로세서로서, 고속, 고효율 및 저비용의 자동화된 실험이 가능하다.Lab-on-a-chip technology has come to the fore in the face of the increasing proportion of working with very small amounts of samples or reagents. Laboratory chips are chemical microprocessors that integrate various devices on a few cm 2 chip made of glass, silicon, or plastic using photolithography or micromachining techniques widely used in the semiconductor field. High speed, high efficiency and low cost automated experiments are possible.

실험실칩 내에서 극미량 유체를 이송하는 방법은 시료의 양이 매우 작고, 대부분의 경우 유체의 이송이 매우 작은 크기의 미세 채널에서 이루어지므로 기존의 유체 이송방법과는 전혀 다르다.The method of transporting trace fluid in the lab chip is very different from the existing fluid transport method because the amount of sample is very small and in most cases the fluid is transported in a very small microchannel.

모세관 전기이동장치를 구현한 모세관 전기영동 마이크로칩은 펌프나 밸브등의 유체 제어장치 없이 전기장만으로 유체의 흐름을 조절할 수 있어 장치가 매우간단하며, 운용이 용이하고, 고속 분석이 가능하다.Capillary electrophoresis microchip that implements capillary electrophoresis device can control the flow of fluid through electric field only without fluid control device such as pump or valve.

상기 마이크로칩 모세관 전기영동 장치의 핵심은 분리분석이 일어나는 미세유로가 새겨진 마이크로칩으로써 상기 마이크로 칩의 최근 제작동향은 네 가지가 주류를 이루고 있다. 실리콘, 유리, 폴리머 형 그리고 두 가지 이상의 조합으로 이루어진 조합형이 있다.The core of the microchip capillary electrophoresis device is a microchip engraved with a microchannel in which a separation analysis takes place, and four recent trends of manufacturing the microchip are mainstream. There are silicone, glass, polymer types and combinations of two or more combinations.

실리콘 타입의 경우는 복잡한 3차원 구조의 제작이 용이하며, 각 공정의 노하우가 많이 알려져 있다. 뿐만 아니라 MOS 트랜지스터를 비롯한 각종 소자들을 칩 안에 집어 넣을 수가 있어서 진정한 의미의 Lab-on-a-chip을 구현할 수 있다.In the case of the silicon type, a complicated three-dimensional structure can be easily manufactured, and a lot of know-how of each process is known. In addition, MOS transistors and other devices can be housed in a chip, creating a true lab-on-a-chip.

그러나 상기 실리콘타입은 실리콘 위에 금속막 히터를 구현하거나 DNA분리를 위한 전기영동시 전극간 절연파괴가 일어나기 쉬운 단점이 있다. 또한 실리콘은 불투명하기 때문에 DNA나 단백질 분석에 통상적으로 사용되는 자외선-가시광선 분광광도법이나 형광 검출법을 사용하기가 용이하지 않다.However, the silicon type has a disadvantage in that the breakdown between the electrodes is likely to occur when the metal film heater is implemented on the silicon or electrophoresis for DNA separation. In addition, since silicon is opaque, it is not easy to use ultraviolet-visible spectrophotometry or fluorescence detection method commonly used for DNA or protein analysis.

유리형 칩의 경우는 절연성 및 열적 안정성이 뛰어나고 광학적 검출방법을 사용할 경우 아주 유리하다. 하지만 에칭이나 접합과 같은 제조공정상에서 발생하는 다수의 기술적인 어려움이 단점으로 대두되고 있다.Glass chips have excellent insulation and thermal stability and are very advantageous when using optical detection methods. However, a number of technical difficulties that arise in the manufacturing process, such as etching or bonding has emerged as a disadvantage.

최근 들어 가장 각광을 받고 있는 것이 폴리머형칩이다. 폴리머형 칩은 주로 PMMA(polymethylmethacrylate),PDMS(polydimethlysiloxane),폴리탄산에스테르(Polycarbonate),폴리프로필렌(Polypropylene)등 MEMS (Micro-Electric-Mechanical Sys tem)분야에서 많이 사용하는 고분자 재료를 이용한다. 이와 같은 재료를 이용한 폴리머형칩은 제조단가가 매우 저렴하고 대량생산이 용이하며 다양한 구조를 용이하게 형성하는 장점을 구비한다.In recent years, the most popular type is the polymer chip. Polymer type chips mainly use polymer materials commonly used in the field of micro-electric-mechanical systems (MEMS) such as polymethylmethacrylate (PMMA), polydimethlysiloxane (PDMS), polycarbonate, and polypropylene. Polymeric chips using such materials have the advantages of very low manufacturing cost, easy mass production, and easy formation of various structures.

그러나 폴리머칩은 열적 안정성에 문제가 있을 수 있고 재질에 따라서는 소수성을 구비하고 있어 유체의 흐름에 악영향을 미칠 수 있으므로 친수성 표면처리가 필요한 경우도 있다.However, the polymer chip may have a problem in thermal stability and may have a hydrophobicity depending on the material, which may adversely affect the flow of the fluid, thus requiring a hydrophilic surface treatment.

기존의 마이크로 칩 모세관 전기영동 시스템에서의 마이크로 칩은 주로 유리형 칩과 폴리머 칩을 사용했다. 상기한 바와 같이 유리형 칩은 에칭과 접합등 제조공정상 어려움이 많고 폴리머 칩의 경우 열적 안정성의 문제와 재질에 따라 친수성 표면처리가 필요하다는 단점들이 있다.In conventional microchip capillary electrophoresis system, the microchip mainly uses glass chips and polymer chips. As described above, glass chips have many disadvantages in manufacturing processes such as etching and bonding, and polymer chips require hydrophilic surface treatment depending on thermal stability and materials.

이에 본 발명은 상기와 같은 문제점들을 해소하기 위해 발명된 것으로써, 본 발명의 목적은 기존의 마이크로 칩 모세관 전기영동 시스템에서 사용된 유리형 칩과 폴리머 칩의 단점은 보완하고 두 칩의 장점을 통합한 마이크로 칩의 제조방법을 제공하는 것이다. 이와 동시에 상기 마이크로칩을 이용하여 기존의 모세관 전기영동 장치의 분리분석을 위한 최적의 조건을 제공하고 기존의 대표적인 5가지 분리모드인 모세관구역 전기영동법, 마이셀 동전기 크로마토그래피법, 모세관 겔 전기영동법, 모세관 등전집중법, 모세관 등속전기영동법 의 수행을 가능하게 함으로써 다양한 시료의 분리 및 분석을 가능하게 하고 분리분석 조건 결정을 보다 용이하게 하며 기존의 시스템보다 분리분석 시간을 10배 이상 단축시킨다. 또한 초고속, 초소형 진단 시스템에도 응용이 가능하고 특정 시료 연구, 실험용 마이크로 칩 모세관 전기영동 시스템 제작에도 많은 장점을 제공하고자 고안되었다.Therefore, the present invention has been invented to solve the above problems, the object of the present invention is to complement the disadvantages of the glass chip and polymer chip used in the conventional microchip capillary electrophoresis system and to integrate the advantages of both chips It is to provide a method for manufacturing a microchip. At the same time, the microchip is used to provide optimal conditions for the separation and analysis of existing capillary electrophoresis devices, and five representative separation modes are capillary zone electrophoresis, micelle electrokinetic chromatography, capillary gel electrophoresis, Capillary isoelectric focusing and capillary isoelectric electrophoresis enable the separation and analysis of a variety of samples, making it easier to determine separation assay conditions, and reducing separation analysis time by more than 10 times compared to conventional systems. It is also designed to be applied to ultra-fast and ultra-small diagnostic systems and to provide many advantages for specific sample research and experimental microchip capillary electrophoresis systems.

도 1은 본 발명에 따른 일실시예의 마이크로칩상부의 제작순서도이다.1 is a manufacturing flowchart of the upper part of the microchip of one embodiment according to the present invention.

도 2는 본 발명에 따른 일실시예의 마이크로칩하부의 제작 순서도이다.2 is a manufacturing flowchart of the microchip lower portion of an embodiment according to the present invention.

도 3은 본 발명에 따른 마이크로칩의 단면도이다.3 is a cross-sectional view of a microchip according to the present invention.

*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *

1 : 실리콘 웨이퍼 3 : SU-81: Silicon Wafer 3: SU-8

5 : 포토마스크 7 : 자외선5: photomask 7: ultraviolet

9 : 양각주형틀 11 : PDMS9: embossed mold 11: PDMS

13 : 음각부 15 : SiO2 13: engraved part 15: SiO 2

17 : 마이크로칩상부 21 : 천공판17: upper microchip 21: perforated plate

23 : PDMS플레이트 25 : SiO2 23: PDMS plate 25: SiO 2

30 : 마이크로칩30 microchip

상기와 같은 목적을 달성하기 위한 본 발명은 웨이퍼 상부에 네가티브 포토레지스트를 코팅하여 소프트 베이킹하는 제 1 단계와; 상기 네가티브 포토레지스트가 코팅된 웨이퍼 상부에 포토마스크를 배열하고 자외선에 일정시간 노출시키는 제 2 단계와; 상기 자외선을 일정시간 노출시킨 후 현상액으로 기판의 포토레지스트를 현상하여 양각틀을 완성하는 제 3 단계와; 상기 양각틀에 PDMS를 주입하고 고형화 시킨 후, 고형화된 PDMS를 이형하여 마이크로칩상부를 얻는 제 4 단계와; PDMS플레이트 상면에 SiO2박막을 증착하여 마이크로칩하부를 형성하는 제 5 단계와; 상기 마이크로칩상부의 음각부에 SiO2를 증착하고, SiO2를 증착한 상기 마이크로칩상부와 상기 마이크로칩하부를 접착하여 마이크로칩을 형성하는 제 6 단계로 이루어진다.The present invention for achieving the above object comprises a first step of soft baking by coating a negative photoresist on the wafer; Arranging a photomask on the negative photoresist-coated wafer and exposing it to ultraviolet light for a predetermined time; A third step of completing the relief frame by exposing the ultraviolet light for a predetermined time and developing the photoresist of the substrate with a developer; Injecting the PDMS into the relief frame and solidifying the mold, and releasing the solidified PDMS to obtain an upper portion of the microchip; Depositing a SiO 2 thin film on the PDMS plate to form a lower microchip; Depositing SiO 2 on the concave portion of the microchip, and the upper, made of a sixth step of bonding the SiO 2 by the microchip and the microchip upper lower-deposited to form a microchip.

이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 설명한다. 또한 본 실시예는 본 발명의 권리범위를 한정하는 것은 아니고, 단지 예시로 제시된 것이다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, this embodiment is not intended to limit the scope of the present invention, but is presented by way of example only.

이하에서는 본 발명의 일실시예의 마이크로칩상부의 제작방법에 대하여 설명한다.Hereinafter, a manufacturing method of the upper part of the microchip of one embodiment of the present invention will be described.

도 1은 본 발명에 따른 일실시예의 마이크로칩상부의 제작순서도이다. 도시한 바와 같이 원하는 분리분석용 미세유로 패턴을 포토마스크로 제작(미도시)한후, 실리콘 웨이퍼(1)에 네가티브 포토레지스트인 SU-8(3)을 스핀코팅한 후 소프트 베이킹한다. 그 후 포토레지스트가 코팅된 포토레지스트가 코팅된 실리콘 웨이퍼 (1)의 상면에 상기 포토마스크(5)를 정렬하고, 자외선(7)에 일정시간 노출한다.1 is a manufacturing flowchart of the upper part of the microchip of one embodiment according to the present invention. As shown in the drawing, a desired microanalysis pattern for separation analysis is manufactured (not shown), followed by spin coating of SU-8 (3), which is a negative photoresist, on the silicon wafer 1, followed by soft baking. Thereafter, the photomask 5 is aligned on the top surface of the photoresist coated silicon wafer 1 and exposed to ultraviolet light 7 for a predetermined time.

자외선(7) 노출 후 현상액으로 기판의 포토레지스트를 현상하면 플라스틱 마이크로칩용 양각주형틀(9)이 완성된다. 상기 양각주형틀(9)에 PDMS(11)를 주입하고, 진공을 걸어 PDMS(11) 주입시 발생한 기포를 모두 제거한 후 70℃오븐에서 2시간 정도 두어 고형화시킨 후 주형틀(9)과 고형화된 PDMS(11)를 이형한다. 상기 이형된 PDMS(11)의 음각부(13)에 PECVD법를 이용하여 SiO2(15)를 증착하여 마이크로칩상부(17)를 형성한다.When the photoresist of the substrate is developed with a developer after exposure to ultraviolet light 7, the relief mold 9 for plastic microchips is completed. Inject the PDMS (11) into the embossed mold (9), remove all the bubbles generated during the injection of the PDMS (11) by placing in a 70 ℃ oven for 2 hours to solidify and then the mold (9) and solidified The PDMS 11 is released. SiO 2 (15) is deposited on the recess 13 of the deformed PDMS 11 by PECVD to form an upper portion of the microchip 17.

이하에서는 본 발명의 일실시예의 마이크로칩하부의 제작방법에 대하여 설명한다.Hereinafter, a method of manufacturing the microchip lower part of the embodiment of the present invention will be described.

도 2 는 본 발명의 일실시예에 따른 마이크로칩하부의 제작 순서도이다. 도시한 바와 같이 PDMS플레이트(23)의 상면 중 미세유로에 해당하는 일부분에 PECVD법를 이용하여 SiO2(25)를 증착한다.2 is a manufacturing flowchart of the lower part of the microchip according to an embodiment of the present invention. As shown in the figure, SiO 2 25 is deposited on the portion of the upper surface of the PDMS plate 23 corresponding to the microchannel by PECVD.

상세히 설명하면 최초에 PDMS플레이트(23)의 상면부에 원하는 형상의 천공판 (21)을 정열한다. 상기 천공판(21)은 미세유로부분을 천공시킨 형상이다. 상기 천공판(21)은 SiO2(25)가 불필요한 부분에 코팅되는 것을 막기 위해 정열하는 것으로 SiO2(25)가 코팅되는 부분에 홀을 뚫은 것이다. 상기 천공판을 정열한 후 PECVD(Plasma Enhanced Chamical Vapor Deposition)법으로 SiO2(25)를 증착하고 그 후 천공판을 떼어내어 마이크로칩하부를 형성한다.In detail, first, the perforated plate 21 having a desired shape is arranged on the upper surface of the PDMS plate 23. The perforated plate 21 has a shape in which the micro channel portion is perforated. The perforated plate 21 is drilled a hole portion in which the coated SiO 2 (25) that align to prevent the coating in unwanted parts SiO 2 (25). After aligning the perforated plate, SiO 2 (25) is deposited by Plasma Enhanced Chemical Vapor Deposition (PECVD), and then the perforated plate is removed to form a lower microchip.

상기한 제법으로 제조된 마이크로칩상부와 마이크로칩하부는 코로나방전을 이용해 접합되어 마이크로칩을 형성한다.The upper part of the microchip and the lower part of the microchip manufactured by the above-described manufacturing method are joined by corona discharge to form a microchip.

본 발명은 상기한 열적안정성의 문제와 재질에 따라 친수성처리를 하여야하는 문제를 구비하는 폴리머마이크로칩의 단점과 제조공정상 다수의 어려움을 구비하는 유리형마이크로칩의 단점을 보완하고 두 칩의 장점을 통합할 수 있는 마이크로칩이다.The present invention complements the disadvantages of the polymer microchip having the problems of the above-mentioned thermal stability and the hydrophilic treatment according to the material and the disadvantages of the glass type microchip having a number of difficulties in the manufacturing process and the advantages of the two chips. It's an integrated microchip.

본 발명은 제작시 주조방법을 이용하기 때문에 기존의 유리형마이크로칩의 단점인 에칭접합과 같은 제조공정상의 어려움을 해소하고, 수산화칼륨(KOH)용액을 미세유로에 흘려주면 실라놀기(silanol group) 치환하여 친수성 표면으로 변환이 가능하기 때문에 유체의 흐름에 악영향을 미칠 요인을 해소할 수 있다.The present invention eliminates difficulties in the manufacturing process, such as etching, which is a disadvantage of conventional glass type microchips because of the casting method used in fabrication, and when a potassium hydroxide (KOH) solution is poured into the microchannel, silanol groups It can be converted to a hydrophilic surface to eliminate factors that adversely affect the flow of the fluid.

또한 상기 마이크로 칩은 초고속, 초소형 진단 시스템에도 응용이 가능하고 특정 시료를 위한 연구, 실험용 마이크로 칩 모세관 전기영동 시스템제작에도 많은 장점을 제공할 것이다.In addition, the microchip may be applied to an ultra-fast and ultra-small diagnostic system and may provide many advantages in the manufacture of a microchip capillary electrophoresis system for research and experimentation for a specific sample.

상기 마이크로 칩이 내장된 모세관 전기영동 시스템은 자외선-가시광선 분광광도법과 레이저 유발 형광검출법을 동시 수행이 가능하게 하여 다양한 시료들을검출할 수 있다.The microchip-embedded capillary electrophoresis system can simultaneously perform ultraviolet-visible spectrophotometry and laser-induced fluorescence detection to detect various samples.

Claims (3)

웨이퍼 상부에 네가티브 포토레지스트를 코팅하여 소프트 베이킹하는 제 1단계와;Coating a negative photoresist on the wafer to soft bake; 상기 네가티브 포토레지스트가 코팅된 웨이퍼 상부에 포토마스크를 배열하고 자외선에 일정시간 노출시키는 제 2 단계와;Arranging a photomask on the negative photoresist-coated wafer and exposing it to ultraviolet light for a predetermined time; 상기 자외선을 일정시간 노출시킨 후 현상액으로 기판의 포토레지스트를 현상하여 양각틀을 완성하는 제 3 단계와;A third step of completing the relief frame by exposing the ultraviolet light for a predetermined time and developing the photoresist of the substrate with a developer; 상기 양각틀에 PDMS를 주입하고 고형화 시킨 후, 고형화된 PDMS를 이형하여 마이크로칩상부를 얻는 제 4 단계와;Injecting the PDMS into the relief frame and solidifying the mold, and releasing the solidified PDMS to obtain an upper portion of the microchip; PDMS플레이트 상면에 SiO2박막을 증착하여 마이크로칩하부를 형성하는 제 5 단계와;Depositing a SiO 2 thin film on the PDMS plate to form a lower microchip; 상기 마이크로칩상부의 음각부에 SiO2를 증착하고, SiO2를 증착한 상기 마이크로칩상부와 상기 마이크로칩하부를 접착하여 마이크로칩을 형성하는 제 6 단계로 이루어지는 마이크로칩 제조방법.And depositing SiO 2 in the intaglio portion of the microchip and attaching the microchip upper portion and the microchip lower portion to which SiO 2 is deposited to form a microchip. 제 1 항에 있어서,The method of claim 1, 상기 SiO2박막 증착은 PECVD법으로 실행되는 것을 특징으로 하는 마이크로칩 제조방법.And depositing the SiO 2 thin film by PECVD. 제 1 항에 있어서,The method of claim 1, 상기 마이크로칩상부와 마이크로칩하부의 접착은 코로나방전을 이용하여 실행되는 것을 특징으로 하는 마이크로칩 제조방법.The microchip manufacturing method, characterized in that the adhesion of the upper and lower microchip is performed using a corona discharge.
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KR20040009779A (en) * 2002-07-25 2004-01-31 주식회사 옵트론-텍 Method of manufacturing sample storage for microchip
KR100644861B1 (en) * 2005-04-20 2006-11-14 한국과학기술연구원 A method of fabricating microchannel using surface tension and the microchannel
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CN108597335A (en) * 2018-06-15 2018-09-28 安徽中医药高等专科学校 A kind of preparation method of green multifunctional teaching microchip
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KR20040009779A (en) * 2002-07-25 2004-01-31 주식회사 옵트론-텍 Method of manufacturing sample storage for microchip
KR100644861B1 (en) * 2005-04-20 2006-11-14 한국과학기술연구원 A method of fabricating microchannel using surface tension and the microchannel
KR100965399B1 (en) * 2008-02-14 2010-06-24 연세대학교 산학협력단 An used of the Joule heating to make biocompatible heat condition in fully integrated micromachined magnetic cell sorting system
KR20180030205A (en) * 2015-08-24 2018-03-21 미츠비시 쥬코 메이키 엔진 가부시키가이샤 Recoil starter and engine
CN107176588A (en) * 2017-06-19 2017-09-19 鲁东大学 A kind of preparation method of hollow MCA
CN107176588B (en) * 2017-06-19 2018-08-14 鲁东大学 A kind of preparation method of hollow microchannel structure
CN108597335A (en) * 2018-06-15 2018-09-28 安徽中医药高等专科学校 A kind of preparation method of green multifunctional teaching microchip
CN111924799A (en) * 2020-07-02 2020-11-13 天津大学 Preparation method of metal oxide nanowire array and nanowire array prepared by same

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