KR20010053365A - Improved inter-device serial bus protocol - Google Patents

Abstract

The device-to-device serial bus protocol facilitates the interconnection and communication between multiple devices over a serial bus. The bus 48 includes a clock wire, a data wire and a start / stop wire. The master serial bus interface connects the master device to the serial bus. The slave serial bus interface connects slave devices to the serial bus. The master serial bus interface 180 may include a transaction initiator, a denter write mechanism, a data read mechanism, and a clock driver. The transaction initiator initiates a transaction by pulling the signal level of the start / stop wire low. The data recording mechanism controls the signal level on the data wire in accordance with the data written to the slave device. The data read mechanism reads the data by monitoring the signal level on the data wire. The clock driver controls the signal level on the clock wires depending on the specified clock signal.

Description

Device-to-device serial bus protocol {IMPROVED INTER-DEVICE SERIAL BUS PROTOCOL}

Electronic devices (portable cell phones, electronic calculators, CD players, camcorders, etc.) include several internal devices (ICs or chips) controlled by a single chip microprocessor. Frequently, such devices include an inter-device serial bus to link their internal components together. The chips communicate with the internal microprocessor, sending data to and from the microprocessor via a device-to-device serial bus.

The microprocessor has some control on the chip. For example, a microprocessor can configure the chip to use no power, and can interact with the chip to change functionality or otherwise change performance. Communication from a microprocessor to a particular chip without serialization, i.e. without the use of a serial bus between devices, must be individually routed to the appropriate register on the chip using more pins and potentially containing more power. However, using a device-to-device serial bus, fewer pins can be used to facilitate control of hundreds of functions of the various chips by the microprocessor.

Philips' I ² C bus typically uses a device-to-device serial bus protocol. According to the I ² C bus protocol, slave chips are connected to the bus and respond to them by collecting the appropriate messages, internally decoding the address information and drawing data accordingly when addressing by the processor acting as the master. .

It is desirable to fabricate such multichip devices in smaller sizes and to reduce the costs associated with design and manufacturing. Thus, there is a need for a mechanism for facilitating the exchange of chips already fabricated in many multichip devices and providing an optional but compatible serial bus protocol. This increases the options available to IC suppliers and producers of end product multichip devices. If the chips incorporate common serial interfaces, the configuration and use of the chips become standardized and economical at the board or system level.

Thus, there is a need for an improved inter-device serial bus protocol that can operate over a wide range of clock speeds and can coexist with the 2-wire Philips I ² C bus protocol. The above protocol should accommodate the transmission of clock information, data information and information controlling the start and stop of transactions between interconnected chips. In some cases, the protocol should include mechanisms for indicating when data should be read or written from the slave device, for addressing the slave devices, for arbitration between multiple masters accessing the serial bus. Communication between devices over the improved serial bus protocol preferably relates to synchronous operation.

Definition of Terms

The following term definitions are provided to assist in understanding the embodiments and features shown herein.

Control information

Information for controlling the flow of information through the bus. The information may include a start transaction indication and a stop transaction indication.

master

A device connected to a bus that can initiate transactions with other devices connected to the same bus.

Parity

This term designates the same or equivalent quality between devices in communication with each other. This may include, for example, an error checking procedure that causes the transmission data to be checked to determine if the information to be transmitted is transmitted without error.

receiving set

Any device that receives data from a data line provided on a bus.

Serial communication

Transmission of information between computers or other devices is done one bit at a time over a single line. Serial communication can be synchronous (controlled by a time standard such as clock) or asynchronous (processed by the exchange of control signals that govern the flow of information). In serial communication, the transmitter and receiver use the same parity and control information.

Slave

A device that can be written or read but does not initiate a transaction.

Synchronous operation

Operation controlled by clock or timing mechanism. In the case of synchronous bus operation, data is transmitted in accordance with clock pulses directed to the data stream or provided simultaneously on a separate line.

transaction

A transaction includes a data transmission between a master and a slave for a period of time that extends between the time that data transmission is initiated by the master up to that time and the time that the data transmitter master or other device is blocked.

transmitter

Any device connected to a bus that transmits information over data lines provided on the bus.

The present invention relates to an inter-device serial bus. More specifically, the present invention relates to a device-to-device serial bus that uses a protocol to facilitate a simple master / slave relationship between devices having a small number of lines and some connected to a bus that may use other protocols.

1 shows a connection of devices to an I ² C bus.

2 is a waveform diagram illustrating bit transmission on an I ² C bus.

3 is a waveform diagram illustrating start and stop instructions on an I ² C bus.

4 is a schematic representation of the basic data format of the I ² C bus protocol.

5 is a schematic diagram of a serial bus structure according to the illustrated embodiment of the present invention.

6 shows a serial bus connected to devices using the I ² C bus protocol as well as to devices using the new protocol.

7 shows an Interrupt Transmission Mode (ITM) message format.

8 illustrates a fast transmission mode (FTM) message format.

9 illustrates a bulk transmission mode (BTM) message format.

10 is a block diagram of a master device.

FIG. 11 is a more detailed block diagram of the master SBI controller shown in FIG. 10.

12 is a block diagram of a data path block.

FIG. 13 is a flow diagram illustrating operation of the master SBI controller of FIG. 10 performing a transaction.

14 is a block diagram of a slave device.

The present invention is provided to improve existing serial interface protocols for linking master and slave devices in small multichip devices. The present invention generally provides mechanisms for installing a synchronous protocol between devices via a bus interface. The mechanism facilitates efficient communication between various devices using fewer lines and otherwise facilitates the design and installation of multiple chip devices and systems. The protocol mechanisms presented here should further assist in diagnosing and correcting errors in the various devices of a multichip system.

Thus, the present invention is directed to one or more portions of a device-to-device serial bus protocol to facilitate interconnection and communication between multiple devices over a serial bus. The serial bus may include clock wires, data wires, and start / stop wires. The master serial bus interface may be provided for connecting the master device to the serial bus. Slave serial bus interfaces may be provided for connecting slave devices to the serial bus. In some aspects of the invention, the master serial bus interface includes a transaction initiator, a data write mechanism, a data read mechanism and a clock driver. The transaction initiator initiates the transaction by raising the low signal level of the start / stop wire. The data recording mechanism controls the signal level on the data wire in accordance with the data written to the slave device. The data read mechanism reads the data by monitoring the signal level on the data wire. The clock driver controls the signal level on the clock wire in accordance with the specified clock signal.

The objects, features and advantages of the present invention are described in detail with reference to the following drawings by way of exemplary embodiments, not limitations of the present invention, and like reference numerals indicate similar parts of the present invention in many respects.

1-6 show several aspects of the I ² C bus protocol and certain installations. 7-14 illustrate several aspects of an exemplary embodiment of the present invention derived with a new serial bus interface (SBI) protocol. The SBI protocol shown uses a bus with three wires. The devices may be connected to the bus to transmit information to each other. The devices include master devices and slave devices. The coordination procedure may be included in the SBI protocol such that one or more masters initiate data transmission simultaneously. The illustrated SBI protocol is compatible with devices that accept I ² C bus devices as well as devices that accept new protocols.

Referring to the drawings in more detail, a conventional I ² C bus protocol is described with reference to FIGS. 1 shows a pair of devices connected to an I ² C bus, or I ² C bus structure 10. The illustrated I ² C bus structure 10 includes a bus 11 having a pair of wires. The pair includes a first wire that is a serial data line SDA and a second wire that is a serial clock line SCL. The stop registers 12, 13 are respectively connected to the serial clock line SCL and the serial data line SDA at the first ends, respectively, and to the common DC voltage source + V _DD at the second end. The pair of devices connecting the first device 14 and the second device 16 are connected to the illustrated I ² C bus 11. The first device 14 includes a clock interface circuit 18 and a data interface circuit 19, among other elements (not shown). The second device 16 includes a clock interface circuit 18 'and a data interface circuit 19', among other elements (not shown). The clock interface circuits 18, 18 ′ shown include amplifiers and transistors. Both wires are high or in one state when each wire SDA, SCL is free. Of the respective data interface circuits 18, 18 ', 19, 19' to pull down the respective lines (SDA, SCL) to a low state when operating the transistor, thereby logically indicating "zero". Transistors are connected to an open drain or open collector to perform a wired AND function. Various different technologies (CMOS, NMOS, BIPOLAR, etc.) can be connected to the I ² C bus.

2 is a waveform diagram illustrating bit transmission on an I ² C bus. The upper waveforms are signal and data lines (SDA), and the lower waveforms are signal and clock lines (SCL). During the stability check period 20, the data signal level on the data line SDA does not change while the clock signal is high. During the data line change period 22, i.e. while the clock signal is low, the high or low state of the data line SDA may change. One clock pulse is generated for each data bit sent on the data line SDA.

3 shows a waveform diagram showing stop and start instructions on an I ² C bus. The two waveforms on data line SDA and clock line SCL represent a start condition 24 and a stop condition 26, respectively, as shown. The start condition 24 is indicated when there is a transition from high to low on the data line SDA while the signal level on the clock line SCL is high. A stop condition 26 is indicated when there is a transition from low to high on the data line SDA while the signal level on the clock line SCL is high. According to the I ² C bus specification, start and stop conditions are always generated by the master.

4 is a schematic block diagram illustrating the general protocol format of the I ² C bus protocol. A single transaction is shown, the beginning of which is indicated by the start condition 24 and the end of which is indicated by the stop condition 26. The first byte of transmitted information includes a seven bit slave address 28 with one bit read / write bit (R / W) 30. Thereafter, response bit A 32 is involved. The first response bit 32 is followed by the data and the second response bit 36. This is followed by an additional byte of data 38 followed by another response bit 40.

As shown, each byte carries a response bit as indicated by the "A" blocks in the sequence. If the R / W bit is zero, data is written from the master to the slave device, in which case a response or failure of the response only occurs from the slave device to the master. If there is one R / W bit, data is read from the slave device to the master device and response bits are sent from the master device to the slave device.

5 shows a serial bus structure according to the illustrated embodiment of the present invention. As shown in FIG. 5, the master device 50 is connected to the first and second slave devices 52, 54 via a serial bus 48. The serial bus 48 includes a clock wire SBCK, a start / stop wire SBST, and a data wire SBDT. The clock wire SBCK and data wire SBDT are connected to the stop DC voltage V _DD through the stop register R, respectively. The stop register values can be adjusted to maintain a predetermined RC constant as more devices are added on the serial bus 48. The start / stop wire SBST is not connected in stop form. Each of the master device 50, the first slave device 52, and the second slave device 54 each have a respective SBI controller and bus interaction which serves as a serial bus interface for connecting each device to the serial bus 48. It includes a set of circuits.

The master SBI controller 56 has a clock wire SBCK through respective interaction circuits including a clock wire interaction circuit 62, a start / stop wire interaction circuit 64, and a data wire interaction circuit 66. , Start / stop wire (SBST) and data wire (SBDT). The illustrated clock wire interaction 62 includes a field effect transistor 68 that includes source, drain, and gate electrodes. The source electrode is connected to the clock wire SBCK. The drain electrode is connected to ground, and the gate electrode is connected to the clock wire operation terminal 78 of the master SBI controller 56.

Start / stop interaction circuit 64 includes an amplifier 70 having input and output terminals. The output terminal is connected to the start / stop wire SBST and the input terminal is connected to the start / stop wire operation terminal 80.

Data / wire interaction circuit 66 includes an amplifier 72 and a field effect transistor 74. Amplifier 72 includes an input terminal and an output terminal, the input terminal is connected to a data wire (SBDT), and the output terminal is connected to data monitoring terminal 82 of master SBI controller 56. The field effect transistor 74 includes source, drain and gate electrodes. The source electrode is connected to the data wire SBDT like the input terminal of the amplifier 72. The drain electrode is connected to ground. The gate electrode is connected to the data operation terminal 84 of the master SBI controller 56.

Each of the slave devices 52, 54 includes a number of interaction circuits connected to a clock wire SBCK, a start / stop wire SBST, and a data wire SBDT, respectively. More specifically, the slave devices 52, 54 are clock wire interaction circuits 63a, 63b connected to the clock wire SBCK, start / stop wire interaction circuit connected to the start / stop wire SBST. 65a, 65b, data wire interaction circuits 67a, 67b connected to the data wire SBST.

Clock interaction circuits 63a and 63b include amplifiers 86a and 86b, respectively. Start / stop wire interaction circuits 65a, 65b include amplifiers 88a, 88b, respectively. The data wire interaction circuits 67a and 67b each include a first and a second set of circuit tenants. The first set of circuit elements forming the data wire interaction circuit 67a includes an amplifier 90a and a field effect transistor 92a. The second set of circuit elements forming the data wire interaction circuit 67b includes an amplifier 90b and a field effect transistor 92b.

The amplifier 86a includes an input terminal and an output terminal, the input terminal is connected to the clock wire SBCK, and the output terminal is connected to the clock monitoring terminal 94a. Amplifier 88a includes input and output terminals, the input terminal is connected to start / stop wire SBST, and the output terminal is connected to start / stop monitoring terminal 96a. Amplifier 90a includes input and output terminals, the input terminal of which is connected to a data wire (SBDT), the output terminal of which is connected to data monitoring terminal 98a. The field effect transistor 92a includes source, drain, and gate electrodes. The source electrode is connected to the data wire SBDT together with the input terminal of the amplifier 90a. The drain electrode is connected to ground. The gate electrode is connected to the data operation terminal of the slave controller 58.

In operation, zero is directed to one of the wires SBCK, SBST, SBDT by a low voltage level. In particular, on clock wire SBCK and data wire SBDT, zero is indicated by pulling down the line and 1 is indicated by operating the driver three times and allowing the voltage of the external pullup to be at a high level. On start / stop wire SBST, zero or one is indicated via exclusive control of the appropriate master controller 56 via amplifier 70. If the signal at the output terminal of the amplifier 70 is low, zero is indicated on the start / stop wire SBST, and if the signal is high, " 1 " is indicated. The clock wire interaction circuit 62 of the master device 50 causes the master SBI controller 56 to operate on the clock wire SBCK via the clock wire operation terminal 78 and thereby on the clock wire SBCK. It serves to bring the voltage level low. The start / stop wire detection circuit 64 of the master device 50 is placed on the start / stop wire SBST through the start / stop operation terminal 80 to control the signal level appearing on the start / stop wire SBST. To facilitate operation of the master SBI controller 56. The data wire interaction circuit 66 of the master device 50 allows the master SBI controller 56 to operate on the data wire SBDT via the data monitoring terminal 82 and the data operation terminal 84 and the data wire, respectively. Monitor the signal level on the (SBDT).

More specifically, the clock wire and master controller 56 will operate on the gate electrode of the field effect transistor 68 via the clock wire operating terminal 78, so that current is applied to the source and drain of the field effect transistor 68. The voltage level appearing on the clock wire SBCK goes low. The master controller 56 operates on the data wire SBDT by triggering the gate electrode of the field effect transistor 74 through the data operation terminal 84 so that current flows from the source to the drain of the field effect transistor 74. And the voltage level on the data wire SBDT goes low.

Each slave device 52, 54 (others if possible, not shown) is connected to a clock wire (SBCK), start / stop wire (SBST) and data wire (SBDT) via a monitoring terminal that receives the output terminal of the corresponding amplifier. The signal level at each of the can be monitored. More specifically, slave SBI controller 58 of slave device 52 includes a clock monitoring terminal 94a whose input terminal receives the output terminal of amplifier 86a connected to clock wire SBCK. Slave controller 58 also includes a start / stop monitoring terminal 96a that receives an output terminal of amplifier 88a to which an input terminal is connected to start / stop wire SBST. The data monitoring terminal 98a of the slave controller 58 receives the output terminal of the amplifier 90a to which the input terminal is connected to the data wire SBDT. The data wire operation terminal 100a of the slave controller 58 is connected to the gate electrode of the field effect transistor 92a. This causes the slave controller 58 to switch the field effect transistor 92a so that current flows from the source of the field effect transistor 92a to the drain and the voltage level on the data wire SBDT is low.

Master device 50 is in communication with slave devices 52, 54 (and optionally other devices, not specifically shown) via serial bus 48. The illustrated serial bus 48 includes a set of bus wires (ie, clock wires SBCK, start / stop SBST, data wires SBDT). The master device 50 and one or more slave devices 52, 54 may be initiated by the master device 50 providing a start indication on the start / stop wire SBST. Accordingly, the master SBI controller 56 of the master device 50 outputs the voltage level at the start / stop operation terminal 80 that will cause the amplifier 70 to output the specified voltage level. Will fix the voltage level of the phase. More specifically, in the illustrated embodiment, master SBI controller 56 initiates a transaction by outputting a signal at start / stop operation terminal 80 that causes the signal level on start / stop wire SBST to be pulled low. do.

The clock signal is placed on the clock wire SBCK by the master device 50. The master controller 56 includes a clock driver (not shown in FIG. 5) that causes a suitable operating signal to be output at the clock wire operating terminal 78 to switch the field effect transistor 68. In this form, the master SBI controller 56 controls the signal level on the clock wire SBCK in accordance with the designated clock signal. The last designated clock signal is used together by the master device 50 and the slave devices 52, 54 to facilitate synchronous operation of the master device 50 and one or more slave devices 52, 54 involved in the transaction. .

The master SBI controller 56 of the master device 50 includes a data write mechanism, which uses the data operation terminal 84 to switch the field effect transistor 74 and thus three state field effect transistors. A 74 is generated to generate a current flow from the source of the field effect transistor 74 to the drain, thereby keeping the voltage level on the data wire SBDT high or pulling the voltage level low. Thus, the signal level on the data wire SBDT is controlled in accordance with the data written to the slave devices 52 and 54 involved in the specific transaction. The above operation will be further described below with reference to the following figures.

Figure 6 shows a serial bus structure, in which a master device and a slave device of the first type (using the new protocol described here) are in series with a master and slave device of the second type (using the I ² C bus protocol). It is connected to the bus 48. Specifically, as shown, the serial bus 48 includes a clock wire SBCK, a start / stop wire SBST, and a data wire SBDT. Clock wire SBCK and data wire SBDT are connected to DC voltage V _DD through pull-up resistor R, respectively. A first type master 100 comprising a master device using a first serial bus interface protocol is connected to a clock wire SBCK, a start / stop wire SBST and a data wire SBDT through respective terminals, respectively. The first type master 100 and the first type slave 102 can include master and slave devices as described above with reference to FIG. 5. Thus, the first type master 100 may include a master SBI controller 56 and a clock wire interaction circuit 62, a start / stop wire interaction circuit 64, and a data wire interaction circuit 66. . The first type slave 102 includes interaction circuits including a slave controller 58 and a clock wire interaction circuit 63a, a start / stop wire interaction circuit 65a, and a data wire interaction circuit 67a. can do.

The I ² C master 104 and the I ² C slave 106 are incorporated herein by reference in their entirety in the 1995 updated Philips Semiconductors document "I ² C Bus and Instructions (with Documentation)" 1 p.-24 p. It includes master and slave devices as described in. In some cases, I ² C master 104 and I ² C slave 106 may be configured in a known manner. Each of the I ² C devices 104, 106 includes two terminals connected to a clock wire SBCK and a data wire SBDT suitable for the I ² C protocol. Thus, the I ² C master 104 includes a first terminal connected to the clock wire SBCK and includes a mechanism for controlling the signal level on the clock wire SBCK according to the designated clock signal. Specified clock signal I to facilitate synchronizing the operation of the transaction is I ² C master 104 and the I ² C the I ² C master 104 and the I ² C slave 106, in the event between the slave 106 Used together by the ² C master 104 and the I ² C slave 106.

The I ² C master 104 initiates a transaction by providing a start indication on the data wire (SBDT) in accordance with the I ² C bus protocol described above with reference to FIG. It further includes a second terminal connected to the wire SBDT. The I ² C master 104 further has a master data recording mechanism (not shown) for controlling the signal level on the data wire SBDT according to the data written to the I ² C slave 106. The data may include payload data and overhead data including information addressing I ² C slave 106 in accordance with the I ² C protocol.

The signal level on the clock wire SBCK is configured to facilitate the synchronous operation of the first type master device 100 and the first type slave device 102 and the first type master device 100 and the first type slave device 102. Control by the first type master device 100 in accordance with the designated clock signal used together.

The first type master device 100 provides a stop instruction on the designated bus wire (start / stop wire (SBST)) so that the stop instruction appears on the data and clock wires SBDT, SBCK, regardless of which instructions are present. Block transactions by keeping them. In the embodiment shown, this is done by maintaining the level of the start / stop wire SBST in the high state. Accordingly, the first type master device 100 prevents control by the first type master device 100 of the signal level on the data wire SBDT for transmitting data and while the stop wire is provided and maintained, the clock wire SBCK The control by the 1st type master device 100 of the signal level on () is prevented.

I ² C master device 104 initiates the transaction by providing the I ² C start instruction according to the I ² C protocol on the data wire (SBDT). I ² C master device 104 I ² C slave control the signal level on the data wire (SBDT) according to the data to be transmitted to the device 106, the data I ² information addressed according to the C bus protocol I ² C It may include payload and overhead data including the slave 106. The I ² C master device 104 controls the signal level on the clock wire SBCK according to the designated clock signal. The designated clock signal is used together by the I ² C master device 104 and the I ² C slave device 106 to facilitate synchronous operation of the two devices during the transaction. The transaction is blocked by the I ² C master 104 by providing a stop indication on the data wire SBDT. I ² C master unit 104 detects a Low signal level on the do not match the intended level of the signal data wires (SBDT) indicated by the I ² C master device 104, I ² C Master (104) and I ² It will block any transaction between the C slaves 106. The performance of the new bus operating with the old I ² C bus is a useful aspect of one embodiment of the present invention.

FIG. 7 shows a timing diagram illustrating an interrupt transmission mode message (ITM) of the illustrated serial bus interface protocol. A schematic illustration of ITM transaction 110 is provided with clock wire SBCK, start / stop wire SBST and data wire SBDT. The illustrated ITM transaction 110 includes a start indication 112, a transmission mode identifier 114, a slave address 116, an encoded message 118, a clock stop period 120, and a stop indication 122. Start indication 112 triggers a first bit transmitted on data line SBDT, which is the internal clock signal of the master device after the start / stop signal goes low (the signal is clearly shown in FIG. 7). (Not shown) on the second falling edge. Thus, the first bit of data is shown in FIG. 7 as it begins at start time 124. This is the transaction start time.

With the transaction start time 24, the transmission mode is transmitted from the master device to all slave devices using the same protocol and connected to the same serial bus. In the illustrated embodiment, the transmission mode identifier 114 includes a pair of bits 00 that instruct the master device to initiate a transaction in interrupt mode. Thus, the signal level on the data wire SBDT is low for two clock cycles until the slave address start time 126 is reached to correspond to the falling edge of the clock signal SBCK. Thereafter, one bit slave address 116 is transmitted. Thus, two receivers (including the master or slave) can be addressed in interrupt mode. Interrupt transmission mode (ITM) is used to transmit only one byte of encoded information. ITM messages can be used as write-only messages used by one master to signal interrupts to another master. Encoded message 118 contains five transmitted data bits. Along with the encoded message 118, the clock stop period 120 is shown after the stop instruction 122 is transmitted as a signal on the start / stop wire SBST.

As described above, when one or more master devices are connected to the serial bus, the master device will yield to another master device first to transmit zero on the data wire. Thus, the first two bits of information sent on the data wire (SBDT) (transmission mode identifier 114) fail to maintain a signal level on the data wire (SBDT) with zero (i.e., the start bits in their intended state). ITM transaction will have priority over other transactions as it is low voltage levels that prevent other master devices from not transmitting two consecutive zeros.

Referring to FIG. 5, the master device 50 will control the signal level on the data wire SBDT via the data operation terminal 84 and simultaneously signal on the data wire SBDT via the data monitoring terminal 82. Will monitor the level. If the signal level on the data wire SBDT does not match the intended signal level per operation of the data operation terminal 84 associated with the field effect transistor 74, the master controller 56 of the master device 50 releases the bus. something to do. Thus, a master transmitting zero always has an advantage in arbitration over a master transmitting one. For this reason, ITM transactions are suitable for one master device to interrupt another master device or to take over control of another master device on a serial bus.

8 shows transactions and waveforms corresponding to a fast transmission mode (FTM) transaction. FTM transaction 134 is shown to include 5 bytes of transmitted information. Specifically, the illustrated FTM transaction 134 is directed to a six-bit slave address 140 that completes the initial two bits of information ("01") transmitted on the data wire (SBDT), i.e., the first byte of transmitted information. It starts when the start indication 136 accompanied by the transmission mode identifier 138 accompanied by occurs. The first clock stop period 141a then follows. The second transmitted byte contains the initial R / W (read / write) bit 142 carried by the 7 bit register address 144. The second clock stop period 141b then separates another information byte sent over the data wire SBDT. During each clock stop period 141a-141e, the signal level on the data wire SBDT is high.

The first set of information transmitted between the transmitter and the receiver includes a first byte of data 146. The data may be sent from the master device (transmitter role) to the slave device (receiver role) or from the slave device (transmitter role) to the master device (receiver role) depending on the state of the previously transmitted read / write bit 142. have. The second read / write bit 147 is then transmitted by the master device as the start bit carried by the register address 148 to the data proceeding from where the data is retrieved. If data is read from the identified register, the slave device will drive the data wire SBDT for the next 150 bytes of data to begin when another clock stop period 141d expires. When the completion of the transmission is near, a final clock stop period 141e will occur, and the transaction will end when a stop indication signal is sent by the master device on the start / stop wire SBST.

FTM transactions are made for data transmission between slave devices that may not support other transmission modes. Transmissions to the slave devices have a medium priority and are therefore prioritized by a transmission mode identifier of "01". In this mode, data can be written and read from the slave device in the same transaction.

9 illustrates a bulk transmit mode (BTM) transaction with signals on each of the clock, start / stop and data wires. The illustrated BTM transaction 160 begins with a start indication 162 followed by a two bit transmission mode identifier 164 and a slave address 166. The information sent in the illustrated BTM transaction 160 includes many bytes. The second byte transmitted with the first clock stop period 169a includes the read / write bits 167 carried by the 7 bit register address 168. The third byte of data 170 is then transmitted with a second clock stop period 169b. All remaining bytes are sent in a similar manner until the master requests the SBST line, indicating the end of the transaction. The number of data bytes sent depends only on the protocol's time limit. The final clock stop period 169d then occurs with a stop indication placed on the start / stop wire SBST. The first and second bytes (and subsequent bytes) of the data 170, 172 may be written to a specific register of the slave device or depending on the value placed in the read / write bit 167, the specific register of the slave device. Can be read from. More specifically, in the illustrated embodiment, if the read / write bit 167 is empty, that is, if the signal level on the data wire SBDT is low, the master device writes data to the slave device. If the read / write bit 167 is fixed, that is, the signal level on the data wire SBDT is high, the master device reads data from the slave device.

When the master device wants to read data accompanying a specific register address byte, it releases the data wire SBDT after the edge of the signal on the clock wire SBCK immediately following the last bit transmitted in the register address 168. . In conjunction with each of the second and third clock stop periods 169b, 169c, the slave device then transmits data. The master device subsequently controls the signal level on the clock wire SBCK. The signal level on the start / stop wire (SBST) is low throughout the transaction.

In each of the above modes, the register address is a 7 bit field. This allows the slave to address up to 128 registers. In the bulk transmission mode, the slave generates its register addresses and thus an unlimited number of register addresses can be generated inside the slave.

The master SBI controller of each master device can be configured to have two modes of operation including a functional mode and a test mode. During the functional mode, the master device will only maintain control of the bus for a limited time. In such a mode, when the threshold value indicating the length of the transaction is reached, the master device provides a stop indication on the designated clock wire (SBCK). In the illustrated embodiment, the threshold is the amount of data transmitted when 32 bytes were transmitted. In test mode, the master device will be allowed for unlimited data transmission. By limiting the amount of bytes that can be sent in a given transaction dominated by a single master, this allows the master devices to share the use of the serial bus.

Some general characteristics of the illustrated exemplary embodiments of the protocol presented herein may be described as follows.

(1) All changes in the state on the data wire SBDT occur while the signal level on the clock wire SBCK is low.

(2) All transactions are initiated by pulling the signal of the start / stop wire SBST low, and are completed by raising the signal level on the start / stop wire SBST high.

(3) SBST, SBDT, and SBCK must all be high for at least one clock period (600 ns clock rate must be 1.53 MHz) before a new transaction can begin. If either of the three wires is low, the master cannot start a new transaction and must wait until all three signal levels go high for one clock period.

(4) Data transmission is always the first most significant bit (MSB) and the last least significant bit (LSB).

(5) In functional mode, the master device will not maintain control of the bus for data transmissions greater than 32 bytes. During the test mode, the constraint does not apply.

(6) The master releases transmission on the serial bus if the data it transmits does not appear on the bus. A master sending zero will always be superior to a master sending one. As described above, this law facilitates mutual master arbitration and also for which receivers and some forms of transmission modes for interrupt mode, fast transmission mode and bulk transmission mode, for example as described above. Facilitates the assignment of priorities to. While the fast transmission mode starts a transaction by sending a zero followed by one on the data wire SBDT, the interrupt transmission mode starts a transaction by sending two zeros on the data wire SBDT. The bulk transmission mode starts transmission by transmitting a 1 followed by zero on the data wire SBDT. Thus, the above modes are exactly given priority ordered by master devices that may attempt to gain control of the serial data bus at the same time.

(7) Data transmission can be interrupted at any time by raising the signal level on the start / stop wire SBST high.

(8) The master device or the slave device can drive the data wire SBDT during the clock spacer time.

FIG. 10 is a block diagram further illustrating an exemplary master device 178 that may be connected to the serial bus 48 shown, for example, as shown in FIG. The master device 178 shown in FIG. 10 includes a master serial bus interface (SBI) 180 that includes a master SBI controller 181, a parallel processor interface 183, and a serial interface 185. Parallel processor interface 183 links master SBI controller 181 to master device processor 182. Serial interface 185 links master SBI controller 181 to a serial bus (ie, serial bus 48 shown in FIG. 5).

In the embodiment shown in FIG. 10, the serial interface 185 includes a clock wire interaction circuit 188, a start / stop wire interaction circuit 190, and a data wire interaction circuit 192. Each of the interaction circuits may be configured as described above for the master device 50 as shown in FIG. 5.

Parallel processor interface 183 includes a 16-bit two-way data bus, a second interface 186 provided for other connections between master device processor 182 and master SBI controller 181 in the illustrated embodiment.

The master SBI controller 181 forms a serial link interface between various slave devices that can be connected to the serial bus and the master device processor 182. The master SBI controller 181 will further promote the performance of the master device 182 to monitor the operation of slave devices.

Parallel processor interface 183 may include any known microprocessor parallel interface constructed or commercially available using techniques known in the art. Master SBI controller 181 receives data from parallel processor 183 and serializes address and data using serial interface 185 including three pins and thereby forms the serial bus interface protocol described herein.

As indicated above, the parallel processor interface 183 includes a primary interface 184 and a secondary interface 186. Primary interface 184 includes a pair of assembled 8-bit SBI addresses for transmission between slave devices connected to a serial bus and a 16-bit bidirectional data bus allowing transmission of 8-bit data. The master device processor 182 periodically or, for example, once per NSBI clock cycle, fills the buffer provided within the master SBI controller 181 with new address pairs for transmission to the appropriate slave devices. Will need to be addressed.

11 shows master SBI controller 181 in more detail. The illustrated master SBI controller 181 may include a processor interface 194 (not shown here for simplicity of explanation for other elements) connected to the divider 196 and the data path block 198. . Processor interface 194 receives at one parallel processor 183. The data path block 198 interfaces with the serial bus via serial bus I / O pins 200. As shown in FIG. 11, the parallel processor interface 183 includes a number of parallel connection and control pins, a MICRO_RESET pin 202 and a clock CLK input pin 204. The MICRO_RESET pin 202 causes the master device processor to reset the master SBI controller 181. Clock pin CLK 204 includes an input pin that receives a two phase clock input from master device processor 182. The remaining data pin connections 206 include the remaining pins of the secondary processor connection 186 as well as the remaining pins of the primary interface 184 as shown in FIG.

Processor interface 194 includes several internal connections, including write enable connection WR_EN 208, write data connection WR_DATA 210, write address connection WR_ADDR 212, and read data connection RD_DATA 214. Read data connection 214 is an input to processor interface 194 and other connections 208, 210, 212 are outputs. The connections are connected to divider 196 and data path block 198 via internal buses of master SBI controller 181.

Divider 196 shown includes an internal bus connection 208 and a clock "CLK" input pin 210. The divider further includes a first output 210 for outputting the serial bus clock signal MSBI_SBCK and a second output 212 for outputting the master SBI controller enable signal MSBI_EN.

Data path device 198 has an internal bus connection 215 on one side and includes a plurality of serial bus I / O interfacing pins 200 on the opposite side. Serial bus I / O interfacing pins 200 (other pins not specifically shown for simplicity) include clock wire operation terminal 218, start / stop operation terminal 220, data monitoring terminal 220, data monitoring terminal. 222 and data operation terminal 224.

The processor interface 194 asynchronously interfaces the master SBI controller 181 to the processor bus while retaining synchronous operation for registers that are read and written by the master SBI controller 181. Divider block 196 subdivides the primary CLK clock input received at clock input 210 to generate the appropriate enables for operation of serial shift clock and master SBI controller 181. The divider 196 may have a mechanism that allows for serial operation with a clock speed in the range of, for example, 1.5 MHz to 100 KHz. The illustrated divider 196 facilitates the clock speeds in the above range and allows the master SBI controller 181 to function at a clock rate defined by a resolution of 1 / M divisor of the main clock input CLK with a duty cycle of 40-50%. To make it possible.

12 is a block diagram of a more detailed data path block 228. Various details and specific elements that may form part of data path block 228 are omitted herein for simplicity of description. The illustrated data path block 228 includes a plurality of write registers 238, a plurality of read registers 240, a multiplexer 242, and a central shift register 244. The data path block 228 further includes an SBI control register 246, a start control register 248, and an output 250. Multiple write registers 238 include write register 230 and operation buffer 232. The write register 230 includes a one byte register address portion 234a and a one byte register data portion 234b. Register address and register data portions 234a and 234b respectively include outputs connected to register address portion 236a and register data portion 236b of operation buffer 232. Operation buffer 232 includes an operation buffer enable input 233 for receiving an enable signal. Each of the register address and register data portions 236a and 236b of the operation buffer 232 includes an output that is input to the multiplexer 242. Multiplexer 242 includes a serial register select input 243 that receives a serial register select signal. Multiplexer 242 also receives a slave ID from SBI control register 246.

SBI start control register 248 includes an output that is coupled to the control word input to SBI control register 246.

Multiple read registers 240 include a register address portion 252 and an SBI read data portion 254. Information provided in the read registers 240 is output via the read bus output 255. Read registers 240 further include a read register enable input 256 that receives a read register enable signal.

Shift register 244 includes a data input terminal 258 corresponding to data monitoring terminal 222 of data path device 198 as shown in FIG. Shift register 244 includes a shift register enable input 260 for receiving a shift register enable signal. Shift register 244 includes an output directed to the input of output multiplexer 262 that forms part of output portion 250. The output multiplexer 262 includes a clock output terminal 264 corresponding to the clock wire operating terminal 218 shown in FIG. 11, a start / stop output terminal 266 corresponding to the start / stop operating terminal 220, and FIG. 11. And a data output terminal 268 corresponding to the data operation terminal as shown in FIG.

FIG. 13 is a flow diagram illustrating certain operations performed by the data path block 228 and other elements of the master SBI controller 181 performing a multiword transaction over a serial bus to a slave device as shown in the illustrated embodiment. to be. In the starting step S2, the controller will write to the clock control register provided to the divider 196 to collect the specified split ratio. In step S4, the controller will write to the SBI control register 246. In the write operation, the proper mode of controller operation is selected by writing the appropriate slave ID (SLV_ID) and serial bus protocol mode bits in the SBI control register 246. In step S6, the controller will write the address and data sent to the particular slave device to the write register 230. Then, in step S8, when the controller is ready to begin a transaction, it will write a bit of the SBI start control register 248 to zero to lock START_FLAG to one. In step S10, the controller will first transmit the serial transmission mode bits and the slave ID bits, and then transmit the contents of the write register 230 to the operation buffer 232. The controller will then request an interrupt so that the master device processor 182 notifies the write register 230 is empty.

In step S12, the controller will serialize bits [15: 8] and bits [7: 0] of the operation register 232.

In the down step S14, it is determined whether the write register 230 has been rewritten. If the write register 230 has been rewritten, the process returns to step S10 at which point data will be sent to the operation buffer 232 and an interrupt will be sent to the master device processor 182. If it is determined in step S14 that the write register 230 is not written, then the transaction is blocked in step S16.

The controller 181 has a status register that provides a complete picture of the status of the controller with one read operation. The register will be readable by the master device processor 182.

11 is a block diagram illustrating the slave device 170. The illustrated device 270 includes a slave SBI controller 272 connected to the read / write register 274 and the read register 276 by the bus structure 278. The serial interface is provided at the front end of the slave SBI controller 272 that includes a data wire interaction circuit 280, a clock wire interaction circuit 282, and a start / stop interaction circuit 284.

The illustrated slave 272 is more specifically a bidirectional 7 bit parallel data bus connection 286 connected to a 7 bit parallel bus 287, a 5 bit parallel address bus connection 288 connected to an address bus 289, and a write. Write clock pin 290 and read enable bus (wire) 293 connected to clock bus (wire) 291.

In operation, if the master device, for example master device 178 shown in FIG. 10, addresses the slave device 270 to write data to the read / write register 274, the master device processor 182 may The master SBI controller 181 will instruct it to perform a write transaction and send the recorded data to the master SBI controller 181 via the primary interface 184. The master SBI controller 181 will then control the serialization process, which signals the start indication on the start / stop wire SBST via the start / stop interaction circuit 190. Slave SBI controller 272 of slave device 270 will be ready for the start indication via start / stop interaction circuit 284. Slave SBI controller 272 will receive the clock signal through clock interaction circuit 282. The transmitted data is received via data interaction circuit 280.

While the invention has been described by way of example, it will be understood that the words which have been used herein are words of description rather than of limitation. Modifications may be made within the scope of the appended claims in their broader scope without departing from the scope and spirit of the invention. Although the present invention has been described with reference to specific structures, materials and embodiments, it will be understood that the invention is not limited to the specific features shown. The invention extends to all suitable equivalent structures, mechanisms, installations and uses.

Claims (17)

A serial bus including a clock wire, a data wire and a start / stop wire; A master serial bus interface for connecting a master device to the serial bus; And A slave serial bus interface for connecting a slave device to the serial bus, The master serial bus interface, (a) a transaction initiator for initiating a transaction by providing a start indication on the start / stop wire; (b) a master data recording mechanism for controlling a signal level on the data wire in accordance with data to be written to the slave device; (c) a master data reading mechanism for reading data by monitoring signal levels on the data wires; And (d) a clock driver for controlling the signal level on the clock wire in accordance with a designated clock signal, The slave serial bus interface, (e) a slave data recording mechanism for controlling a signal level on the data wire in accordance with slave origin data to be recorded from the slave device to another device; (f) a slave data reading mechanism for reading data by monitoring signal levels on the data wires; And (g) an internal clocking mechanism for clocking the control of the signal level on the data wire according to a clock signal received from the master serial bus interface by the slave serial bus interface. 2. The inter-device control link of claim 1, wherein the transaction initiator includes a mechanism to bring the signal level on the start / stop wire low. 2. The method of claim 1, wherein said master data recording mechanism comprises a mechanism for controlling a signal level on said data wire in accordance with data comprising payload data and overhead data comprising information addressing said slave device. A device-to-device control link. 4. The inter-device control link of claim 3, wherein the information addressing the slave device specifies a register within the slave device. The device-to-device control link of claim 1, wherein the designated clock signal is commonly used by the master device and the slave device to facilitate synchronous operation of the master device and the slave device. The data recording driver of claim 1, further comprising a pull-up circuit connected to the data wire and the clock wire, wherein the master data write mechanism indicates zero on the data wire by lowering the voltage level on the data wire. Includes a data write driver which instructs three on the data wires to cause the pull-up circuit to bring the voltage level of the data wires high, the clock driver setting a voltage level on the clock wires. And a clock signal driver to direct zero on the clock wire by turning it down and to indicate 1 on the clock wire by turning the clock signal driver into three states, thereby causing the pullup circuit to raise the voltage level of the clock wire. Characterized by Device-to-device control link. The device of claim 1, comprising at least one additional master device, wherein the additional master device and the master device contend for use of the bus, wherein the additional master device comprises: (a) a transaction initiator for initiating a transaction by providing a start indication on the start / stop wire; (b) a master data recording mechanism for controlling a signal level on the data wire in accordance with data to be written to the slave device; (c) a master data reading mechanism for reading data by monitoring signal levels on the data wires; And (d) a clock driver for controlling the signal level on the clock wire in accordance with a designated clock signal, Each of the master device and the additional master device monitors the signal level on the data wire when the monitored signal level does not match the intended signal level and prevents the operation of the master device or the additional master device. Includes a monitor, Each said data recording mechanism of said master device and said additional master device comprises a slave addressing mechanism that overrides the transmitted slave address with a sequence of ones and zeros in accordance with the priority of the transaction to be replaced. Device-to-device control link. 8. The method of claim 7, wherein each of the transaction initiator of the master serial bus interface of the master device and the transaction initiator of the master serial bus interface of the additional master device lower the signal level on the start / stop wire. And a mechanism for providing a start indication on the start / stop wire by pulling down. 8. The master data recording mechanism of each of the master serial bus interfaces of the master device and the additional master device specifies payload data and one register within the slave device and addresses the slave device. And a mechanism for recording data including overhead data comprising said information. 8. The operation of claim 7, wherein the designated clock signal of the clock driver of the master serial bus interface of each of the master device and the additional master device is synchronous of the master device or the additional master device and the slave device. And a signal commonly used by the master device or the additional master device and the slave device to facilitate the operation. 8. The device-to-device control link of claim 7, wherein the sequence of ones and zeros includes at least two zeros for transactions related to broadcast to all slaves connected to the bus. Each connected to a serial bus, comprising a first type master device, a first type slave device, a second type master device, and a second type slave device, wherein the first type master and slave devices use a first serial bus protocol; And wherein the second type master and slave devices use a second serial bus protocol, wherein the serial bus comprises a set of bus wires having a data bus wire and a clock bus wire. (a) the first type master device initiates a transaction by providing a designated start instruction on a designated bus wire for sending transaction start and stop instructions, (b) the first type master device controls a signal level on the data bus wire in accordance with data to be sent to the first type slave diabis, the data addressing payload data and the second type slave device. Includes overhead data with information, (c) a signal level on the clock bus is controlled according to a designated clock signal commonly used by the master device and the first type slave device to facilitate synchronous operation of the master device and the slave device, (d) the first type master device terminates a transaction by providing a stop instruction on the designated bus wire and maintaining the stop instruction, while the stop instruction is provided and maintained by the master device; Preventing control of the signal on the phase by the first type master device and preventing control of the signal level on the clock bus wire by the first type master device, (e) the first type slave device ceases operation while the stop indication is provided and maintained by the first type master device, (f) the second type master device initiates a transaction by providing a start indication on the data bus wire, (g) the second type master device controls the signal level on the data bus according to data transmitted to the second type slave device, and the data includes payload data and information addressing the second type slave device. Include overhead data that you include, (h) the second type master adjusts the signal level on the clock bus wire in accordance with a designated clock signal commonly used by the master device and the slave device to facilitate synchronous operation of the master device and the slave device. Control, (i) the second type master device terminates the transaction by providing a stop indication on the data bus wire, (j) The second type master device prevents a transaction between the second type master device and the second type slave device. 13. The method of claim 12, wherein the second serial bus protocol comprises an I ² C bus protocol. 13. The method of claim 12, wherein the designated bus wire comprises a separate and separate bus wire from the data and clock bus wires. 13. The method of claim 12, wherein the first type master device maintains the stop indication regardless of the presence of any instructions on the data or clock buses. 13. The method of claim 12, wherein the first type master device provides a stop indication on the designated bus wire when a threshold indication of the length of a transaction between the first type master and slave devices is reached. 17. The method of claim 16, wherein the threshold comprises the amount of data sent in the transaction.