JP2786732B2 - Serial / parallel conversion circuit - Google Patents

Description

The present invention relates to a serial / parallel conversion circuit including an external IC that receives serial data from a microcomputer and outputs the data in parallel.

(Prior art) Conventionally, for example, in a one-chip microcomputer incorporated in a control circuit of a microwave oven, since the number of output terminals is limited, data which does not require relatively high speed is output through an external IC. Has been done. In this case, the microcomputer supplies serial data to an external IC, and the external IC outputs the serial data in parallel.

FIG. 4 shows the configuration. Connection between the microcomputer 1 and the external IC2 are as in the figure, the power supply terminal V _SS of the microcomputer 1, the V _DD is a power supply terminal V _SS external IC2, V _DD is connected, likewise, micro The data output terminal D _OUT , clock output terminal CLK _OUT , enable signal output terminal E _OUT , and strobe signal output terminal ST _OUT of the computer 1 are connected to the data input terminal D _IN , clock input terminal CLK _IN and enable signal input of the external IC 2, respectively. Terminal E _IN and strobe signal input terminal ST _IN are connected.

The external IC 2 is generally composed of a shift register 3, a latch circuit 4, and a three-state buffer 5, as shown in FIG. The contents of D are determined and shifted one bit at a time, and 8 bits of data are given to the latch circuit 4. The latch circuit 4 is, for example, of a high active type. The latch circuit 4 latches the immediately preceding output data while the strobe signal input terminal ST _IN is at a low level, and passes the 8-bit data as it is while the strobe signal input terminal ST _IN is at a high level. Three-state buffer 5, when the enable signal input terminal E _IN and the output terminals O ₁ ~ O ₈ becomes disable state when the enable signal input terminal E _IN is, for example, a low level to the high impedance state is at the high level as to output the output of the latch circuit 4 from the output terminals O ₁ ~ O ₈ becomes enabled state. The output terminals D _OUT , CLK of the microcomputer 1
_OUT , E _OUT , and ST _OUT can have three states of high impedance, high level, and low level by the operation of an internal program, and the high impedance is set at the time of reset release immediately after power-on.

The data transfer from the microcomputer 1 to the external IC 2 will now be described. As shown in FIG. 5, in the reset state, the microcomputer 1 is in an operation stop state, but the enable signal output terminal E _OUT is set to a low level state by an external pull-down resistor (not shown), and the strobe signal output terminal ST _OUT is similarly set. It is set to a high level by an external pull-up resistor (not shown).

Now, when the power is turned on and the reset is released, the microcomputer operates based on a program in the microcomputer 1 to set the strobe signal output terminal ST _OUT to a high level (apparently continuing to a high level) and to enable an output terminal.
E _{OUT is set} to low level (apparently continuing to be low level), and at the same time, a clock pulse for 8 bits is output from the clock output terminal CLK _OUT and 8-bit data D is output as 1 unit data from the data output terminal D _OUT. I do. During this time, in the shift register 3 of the external IC 2, undefined data at the time of reset is shifted by the input data. At this time the state of the latch circuit 4 is in the indefinite state is in disable state enable input E _IN of the three-state buffer 5 is a low level, but the three-state buffer 5 is in a high impedance state. Therefore, the output terminals O _{1 to} O ₈ of the external IC 2 are in a so-called open state, and the internal data in the undefined state is not output.

Thereafter, when the microcomputer 1 outputs 8-bit data D corresponding to the number of converted parallel output lines, the microcomputer 1 inverts the strobe signal output terminal ST _OUT to the high level for a moment, and then changes the low level to the low level. (That is, twice in a short time). As a result, the latch circuit 4 of the external IC 2 latches and outputs the state of the shift register 3. The instantaneous change to the high level is performed periodically.

Next, the microcomputer 1 changes the enable signal output terminal _EOUT to a high level. This in, becomes an enable state enable input E _IN of the three-state buffer 5 is changed to the high level, the latch contents as is the three-state buffer 5 of the latch circuit 4
Output from

Hereinafter, while the enable signal output terminal E _OUT of the microcomputer 1 remains at the high level, one unit of data D is output at a cycle of, for example, 1 msec, and every time the output is completed, the strobe signal output terminal ST _OUT is momentarily set. And then falls and outputs 8-bit data in parallel from external IC2.

Note that the latch circuit 3 of the external IC 2 may be of a low active type instead of a high active type. In this case, the strobe signal is normally at a high level, and temporarily becomes a low level after data transmission. Also, the three-state buffer 4 may be of a low active type instead of a high active type. In this case, the enable signal is at a high level until after the first data transmission, and then maintained at a low level.

(Problems to be Solved by the Invention) However, from the viewpoint of reducing the number of output terminals used in the microcomputer 1, even in the above-described conventional configuration, since four output terminals are used to expand the output port. Further, there is a demand for reducing the number of terminals used for the expansion and securing the number of terminals for other purposes.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a serial / parallel conversion circuit capable of reducing the number of terminals used in the order of microcomputers for expanding an output port.

[Structure of the Invention] (Means for Solving the Problems) A serial / parallel conversion circuit according to the present invention outputs serial data from a data output terminal and outputs the serial data from a strobe signal output terminal by the number of parallel outputs to be converted. A microcomputer that outputs a strobe signal whose signal level is inverted twice in a short time when the number of data is output, a data input terminal connected to the data output terminal, and a strobe signal connected to the strobe signal output terminal An input terminal, and an enable signal input terminal for receiving an input of an enable signal for controlling permission or prohibition of an output signal of an output port; and a function of converting the serial data into parallel, wherein the enable signal has a predetermined level. Enable output signal output and disable at inverted level An external IC and a smoothing circuit having an input side connected to the strobe signal output terminal for smoothing a level change of the strobe signal and outputting the same, and an output side connected to an enable signal input terminal of the external IC. Has features.

(Operation) The enable input terminal of the external IC must be in a disabled state until one unit of data is input in order to prevent an output data indefinite state after power-on, and then to an enabled state. It is. In consideration of this point, the strobe signal output terminal of the microcomputer remains at a constant level until the output of the first unit of data is completed after the microcomputer is turned on, and this constant level output is used as a disable signal. It is possible. However, according to the above means, since the output from the strobe signal output terminal of the microcomputer is provided to the enable input terminal of the external IC, the output from the strobe terminal can be used as a disable signal and an enable signal. Therefore, although the number of terminals used for the expansion of the output port can be reduced in the microcomputer, the output of the strobe signal output terminal periodically changes in the form of a pulse (inverted twice) from the second time. When a pulse is input to the enable input terminal of the external IC, there is a disadvantage that the enable input terminal is temporarily disabled.

According to this point, according to the above means, the level change of the output from the strobe signal output terminal of the microcomputer is smoothed by the smoothing circuit, so that the pulse waveform signal is not given to the enable input terminal of the external IC. There will be no disable state later, and the data output from the external IC will not be in an abnormal state.

(Embodiment) An embodiment of the present invention will be described below with reference to FIGS.

In this embodiment, the internal configuration of the external IC is the same as that of the conventional IC. Therefore, the same parts as those of the conventional IC are denoted by the same reference numerals, and FIG. 3 is also used in this embodiment. ing.

Thus, the external IC 2 includes the shift register 3, the latch circuit 4, and the three-state buffer 5, as shown in FIG.

When the data D is serially supplied, the shift register 3 determines the content of the data D at the timing of the clock, shifts the data D by 1 bit, and supplies the data of 8 bits to the latch circuit 4 in parallel. The latch circuit 4 is, for example, a high active type. The latch circuit 4 latches the immediately preceding output data during a period when the strobe signal input terminal ST _IN is at a low level (inverted level).
The bit data is passed as it is. Three-state buffer 5 prohibits the output disable state and turned to the output terminals O ₁ ~ O ₈ when the enable signal input terminal E _IN is, for example, a low level to a high impedance state, the enable signal input terminal E _IN When it is at the high level, it becomes enabled and the output of the latch circuit 4 is passed through each output terminal O _{1 to} O ₈ as it is,
Allow output.

FIG. 1 shows the microcomputer 9 and the external device.
This shows the connection relationship with IC2. Power supply terminal V _SS of the microcomputer 9, the power supply terminal V _SS external IC2, V _DD is connected to V _DD, Similarly, the data output terminal D _OUT of the microcomputer 9, the clock output terminal CLK _OUT respectively external IC2
Are connected to the data input terminal D _IN and the clock input terminal CLK _IN . The strobe signal output terminal ST _OUT is connected to the strobe signal input terminal ST _IN of the external IC2.
In addition, this strobe signal output terminal ST _OUT, smoothing circuit 11 via the inverter 10 is connected to the output side of the smoothing circuit 11 is connected to the enable signal input terminal E _IN external IC2 . The inverter 10 is connected to GND
PNP transistor 10a and resistor between line and −5V line
It is configured to be connected in series with 10b, and its output point 10c
Becomes low level (-5V) when the strobe signal output terminal ST _OUT becomes high level (GND level in this case),
When the strobe signal output terminal ST _OUT goes low,
High level (GND). The smoothing circuit 11 comprising a capacitor 11a and a resistor 11b is connected between the output point 10c and the -5V line. In the microcomputer 9, the output terminal Oa corresponds to the one conventionally used as the enable signal output terminal E _OUT , but is used for another purpose in this embodiment. Reference numeral P _1, P ₂ as another input terminal, denoted by ... P _n.

The data transfer from the microcomputer 9 to the external IC 2 will now be described. As shown in FIG. 2, the microcomputer 9 is in an operation stop state in the reset state, but the strobe signal output terminal ST _OUT is connected to the resistor 9 in FIG.
It is pulled up by a and the resistor 9b and is at a high level. Therefore, in the external IC 2, the strobe signal input terminal ST _IN is at a high level, and the enable signal input terminal E _IN is at a low level inverted by the inverter 10.

Now, when the current is supplied and the reset is released, the microcomputer 9 operates based on the internal program, and sets the strobe signal output terminal ST _OUT to a high level (apparently continuing to a high level), and at the same time, the clock output terminal. CL
An 8-bit clock pulse is output from K _OUT and 8-bit data D is output as one unit of data from a data output terminal D _OUT .

During this time, in the shift register 3 of the external IC 2, undefined data is shifted by the input data at the time of reset. At this time the state of the latch circuit 4 is in the indefinite state is in the disable state is a enable input terminal E _IN is low register state buffer 5, the three-state buffer 5 is in a high impedance state. Therefore, the output terminals O _{1 to} O ₈ of the external IC 2 are in a so-called open state, and internal reception data in an undefined state is not output.

Thereafter, when the microcomputer 9 completes outputting the data D for 8 bits, the microcomputer 9 outputs the strobe signal output terminal ST.
_{Return OUT} to high level for a moment and then return to low level (strobe signal output). As a result, the strobe signal input terminal ST _{IN of} the external IC 2 changes to low level, and the latch circuit 4
Latches the state of the shift register 3 and outputs it. The output of the strobe signal output terminal ST _OUT is
While being inverted by 0, it is given to the enable signal input terminal E _IN external IC2 as a high level signal with a slight time delay by the smoothing circuit 11. This at the enable input terminal E _IN of the three-state buffer 5 becomes an enable state changes to the high level, the latch content of the latch circuit 4 is directly outputted from the three-state buffer 5. As can be seen from the description so far, the external IC2 is
It is in a disabled state until one unit of data D is input, data output in a state where the content of the external IC is indefinite after power-on is prohibited, and first normal one unit of data D is output. .

Hereinafter, the microcomputer 9 stores one unit of data D
Is output at a cycle of, for example, 1 msec, and each time the output is completed,
The strobe signal output terminal ST _{OUT rises} and falls instantaneously, and the strobe signal input terminal ST _IN in the external IC 2 is intermittently changed into a pulse shape, and the strobe signal ST _OUT
Outputs 8-bit data in parallel from the external IC2.

At this time, if the enable signal input terminal E of the external IC 2 is
_If the input of _IN also changes in a pulse shape, the three-state buffer 5 is disabled, and there is a possibility that the output from the external IC 2 may be temporarily inhibited. 9, the output from the strobe signal output terminal ST _OUT , particularly the periodic level change, is smoothed by the smoothing circuit 11.
The enable input terminal E _IN of IC2 becomes the same level state as before, therefore, not be a disable state after the first enable change, not the data output from the external IC2 becomes disabled.

In the above-described embodiment, the high active type is illustrated as the latch circuit 4 of the external IC 2, but this may be a low active type instead of the high active type. Although the three-state buffer 5 is of the high active type, it may be of the low active type. Thus, when the latch circuit and the three-state buffer in the external IC are of the low active type and the high active type, or of the high active type and the low active type, the inverter 10 is not required. Therefore, the inverter 10 may be provided accordingly.

In addition, the present invention is not limited to the above-described embodiment, and can be implemented with various modifications without departing from the scope of the invention.

[Effects of the Invention] As is apparent from the above description, the present invention connects the strobe signal output terminal of the microcomputer to the strobe signal output terminal of the external IC, and connects the input side to the strobe input terminal of the microcomputer. A smoothing circuit for smoothing a level change of a strobe signal output from the microcomputer is provided, and an output side of the smoothing circuit is connected to an enable input terminal of an external IC. The strobe signal output terminal of the microcomputer can also be used as an enable signal output terminal for an external IC, so that the number of terminals used for expanding the output port can be reduced. When the enable input terminal of this external IC is It without which without a Buru state output of the external IC becomes inhibited state, also, an excellent effect that not even the missing data is output prior to transmitting the first-time data.

[Brief description of the drawings]

1 to 3 show an embodiment of the present invention.
1 is an overall electric circuit diagram, FIG. 2 is a time chart showing the output status of each output terminal of the microcomputer and the input status of each input terminal of the external IC, and FIG. 3 is a block diagram showing the configuration of the external IC. FIG. 4 and 5 show a conventional example, FIG. 4 is a diagram corresponding to FIG. 1, and FIG. 5 is a time chart showing an output state of each output terminal of the microcomputer. In the drawing, 2 is an external IC, 3 is a shift register, 4 is a latch circuit, 5 is a three-state buffer, 9 is a microcomputer, 10 is an inverter, and 11 is a smoothing circuit.

Claims (1)

(57) [Claims] 1. A strobe in which serial data is output from a data output terminal and a signal level is inverted twice in a short time when the number of data corresponding to the number of parallel outputs to be converted is output from a strobe signal output terminal. A microcomputer that outputs a signal; a data input terminal connected to the data output terminal; and a strobe signal input terminal connected to the strobe signal output terminal, and an enable that controls permission or prohibition of an output signal of an output port. An external IC that has an enable signal input terminal for receiving a signal input, has a function of converting the serial data into parallel, enables an output of an output signal at a predetermined level of the enable signal, and prohibits the output of the output signal at an inverted level; Connected to strobe signal output pin to connect strobe signal And a smoothing circuit whose output side is connected to an enable signal input terminal of the external IC.