KR20010011000A - Forming method of capacitor pattern using double exposure - Google Patents

Abstract

PURPOSE: A method for forming a capacitor pattern is to primarily expose using a capacitor mask and to secondarily expose using a plug contact hole mask, thus to improve an overlay accuracy between a capacitor and the plug contact hole. CONSTITUTION: A forming method of a capacitor pattern comprises the steps of: coating a photoresistor on a certain base structure and soft-baking the same to form a photoresist layer; primarily expose the photoresist layer using a capacitor mask; secondarily expose the former object using a plug contact hole mask; and post exposure-baking and developing the former object to form a capacitor mask pattern, the base structure being chemically mechanically polished to be planarized, and upon forming the capacitor mask pattern, the photoresist layer being deposited in depth of 0.1 to 3.5 micrometers.

Description

Forming method of capacitor pattern using double exposure

The present invention relates to a method of forming a capacitor pattern using a double exposure process, and more particularly, to a capacitor contact after exposing a capacitor mask using an exposure source when forming a capacitor pattern in a semiconductor integrated circuit manufacturing process. The present invention relates to a method of forming a capacitor pattern capable of greatly improving an overlay accuracy between a capacitor and a plug contact hole by applying a double exposure process of exposing a hole mask.

When forming a semiconductor capacitor by applying a technology of 0.15㎛ or less at present, the CD of the capacitor should have a short axis of 160 nm or less. However, when using KrF exposure equipment, the limit resolution of the capacitor pattern is 180 nm or less. However, such a 180 nm capacitor pattern is formed when there is almost no process margin, and due to the resolution limitation of the exposure equipment, a pattern reaching the limit resolution is usually found. It is difficult to implement properly on the wafer.

In the case of the capacitor, since the capacitance is proportional to the area of the capacitor pattern, if the CD of the long axis of the capacitor pattern is small, the area of the capacitor is reduced, thereby reducing the capacitance of the capacitor. That is, a capacitor pattern with a small CD having a long axis does not satisfy the capacitance of the capacitor required for the operation of the device.

On the other hand, as the circuit integration degree of the semiconductor device increases, the overlapping accuracy becomes more important because the semiconductor device can operate properly only when the overlapping degree between layers is accurately controlled in a smaller cell.

1, 2 and 3 are front views showing the capacitor pattern misaligned with the plug contact hole. The capacitor pattern is in contact with the plug contact hole because the overlapping accuracy between the capacitor and the plug contact hole is not good. The figure shows that it is not possible. This misalignment causes the device to fail.

In an effort to solve the above problems, the present inventors first perform a two-step exposure process in which a capacitor mask is first exposed using a positive photoresist when forming a capacitor mask pattern, followed by a plug contact hole. By improving the overlapping accuracy of the capacitor and the plug contact hole, the present inventors have found that the capacitor long-axis CD of an appropriate length can be secured, thereby completing the present invention.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of forming a capacitor pattern that can improve the overlapping accuracy between a capacitor and a plug contact hole and at the same time ensure an effective long-axis CD of the capacitor.

1 to 3 are plan views showing a state in which misalignment of a capacitor pattern and a plug contact hole occurs;

4 illustrates a double exposure process of a capacitor pattern mask and a plug contact hole mask;

5 is a plan view illustrating a state in which overlapping accuracy of a capacitor pattern and a plug contact hole is improved by a double exposure process of the present invention.

In order to achieve the above object, the present invention provides a method of forming a capacitor pattern applying a double exposure step of performing a second exposure step using a plug contact hole mask subsequent to a first exposure step using a capacitor mask when forming a capacitor mask pattern. .

Hereinafter, the present invention will be described in detail.

In the present invention, first, in the process of manufacturing a capacitor mask of a semiconductor integrated circuit manufacturing process, a capacitor pattern using a double exposure process of first exposing using a capacitor mask and subsequently exposing second using a plug contact hole mask It provides a formation method.

Specifically, the method of forming a capacitor pattern of the present invention comprises the steps of: (a) coating a photoresist composition on the lower substrate on which the contact plug is formed and soft baked to form a photoresist film; (b) first exposing the photoresist film using a capacitor mask; (c) secondly exposing the photoresist film using a plug contact hole mask; And (d) post-exposure bake and develop the resultant to form a capacitor mask pattern.

In the inner cylinder type capacitor mask, a photoresist of an exposed portion, such as a contact hole, is developed to form a hole. In the present invention, in order to solve the problems described above, a capacitor mask is first used. After forming a capacitor mask pattern having a suitable margin for the limit resolution of the exposure equipment, and then performs a double exposure to re-expose the capacitor mask pattern using a plug contact hole mask. At this time, after the first exposure, a misalignment of the capacitor pattern and the plug contact hole as shown in FIGS. 1 to 3 occurs, which is again exposed using a plug contact hole mask, thereby showing the original plug contact as shown in FIG. 4. The final capacitor mask pattern is formed as shown in FIG. 5 by exposing to the portion where the hole was, so that the overlapping accuracy of the capacitor pattern and the lower plug contact hole can be greatly improved.

In this case, the photoresist composition used to form the capacitor pattern includes a resist resin and an organic solvent, and the resist resin is polyvinylphenol-based, polyhydroxystyrene-based, polynorbornene-based, polyamidine-based, polyimide-based, poly Homopolymers or copolymers selected from the group consisting of acrylates and polymethacrylates may be used, and the organic solvent may be ethyl 3-ethoxypropionate, methyl 3-methoxypropionate, cyclohexanone, propylene. A single solvent or a mixed solvent thereof selected from the group consisting of glycol methyl ether acetate, methyl ethyl ketone, benzene, toluene, dioxane and dimethylformamide can be used.

In addition, the coating thickness of the photoresist in the above process is preferably 0.1 to 3.5㎛, as the exposure source, deep ultraviolet (DUV; Deep Ultra Violet), including ArF, KrF and EUV, E-beam, X-ray, ion beam And i-line can be used.

In addition, the double exposure process is applied not only to a capacitor formation process but also to patterning an etched layer made of oxide, polyoxide, nitride, BPSG, aluminum, tungsten, cobalt, organic diffuse reflection prevention material, inorganic diffuse reflection prevention material, titanium, or the like. can do.

In addition, the double exposure process may be applied to both the case of forming a capacitor on the stacked structure in which the planarization process after the deposition of the insulator filling the plug contact hole or the formation of the capacitor without the planarization process after the deposition of the insulator. have.

Hereinafter, the present invention will be described in detail by examples. However, the examples are only to illustrate the invention and the present invention is not limited by the following examples.

Example 1.

In order to obtain a mask pattern of a capacitor, an ultraviolet-ray positive photoresist was coated on a substrate, and then soft baked at 110 ° C. for 90 seconds and exposed to a KrF exposure machine using a capacitor mask. Then, it was exposed once more using a plug contact hole mask, heated at 110 ° C. for 90 seconds with a post-exposure bake (PEB), and then wet developed with a developer to form a capacitor mask pattern.

Example 2.

In order to obtain a mask pattern of a capacitor, a positive photoresist for ArF was coated on a substrate, and then soft baked at 110 ° C. for 90 seconds and exposed to an ArF exposure machine using a capacitor mask. Then, it was exposed once more using a plug contact hole mask, heated at 110 ° C. for 90 seconds with a post-exposure bake (PEB), and then wet developed with a developer to form a capacitor mask pattern.

Example 3.

An i-line positive photoresist was coated on the substrate to obtain a mask pattern of the capacitor, then soft baked at 110 ° C. for 90 seconds and exposed with an i-line exposure machine using a capacitor mask. Then, it was exposed once more using a plug contact hole mask, heated at 110 ° C. for 90 seconds with a post-exposure bake (PEB), and then wet developed with a developer to form a capacitor mask pattern.

As described above, in the present invention, in the semiconductor manufacturing process having a design rule of 0.15 μm or less, by applying a double exposure process using a capacitor mask and a plug contact hole mask during a capacitor mask pattern forming process, Not only can the superimposition accuracy of the capacitor pattern and the plug contact hole be greatly improved, but also the proper long-term capacitance CD of the capacitor lower electrode can be sufficiently secured. The process of the present invention can be applied to the semiconductor manufacturing process of the overlap accuracy of 4G and 16G class or higher to produce a semiconductor device having an improved capacitance (capacitor value), and even when applied to 128M and 256M class can bring a yield improvement. In addition, it is an economical way to reduce the production cost of semiconductor devices because it can reduce the cost of new equipment investment by extending the life of the exposure equipment.

Claims (8)

A capacitor fabrication process in an integrated circuit fabrication process for a semiconductor, comprising: (a) coating and soft baking a photoresist composition on a predetermined underlying structure to form a photoresist film; (b) first exposing the photoresist film using a capacitor mask; (c) second exposure using a plug contact hole mask; And (d) post-exposure bake and developing the resultant to form a capacitor mask pattern. The method of claim 1, The photoresist composition is a homopolymer or copolymer selected from the group consisting of polyvinylphenol-based, polyhydroxystyrene-based, polynorbornene-based, polyamidine-based, polyimide-based, polyacrylate-based, and polymethacrylate-based Resist resin composed and Single solvent selected from the group consisting of ethyl 3-ethoxypropionate, methyl 3-methoxypropionate, cyclohexanone, propylene glycol methyl ether acetate, methylethylketone, benzene, toluene, dioxane and dimethylformamide Or an organic solvent composed of a mixed solvent thereof. The method of claim 1, The method of forming a capacitor pattern, characterized in that the coating thickness of the photoresist when forming the capacitor mask pattern is 0.1 to 3.5㎛. The method of claim 1, The exposure steps (b) and (c) are selected from the group consisting of Deep Ultra Violet (DUV), E-beam, X-ray, ion beam and i-line including ArF, KrF and EUV. A capacitor pattern forming method, characterized in that performed using an exposure source. The method of claim 1, And the lower structure has a surface planarization process (CMP). The method of claim 1, The lower structure is a capacitor pattern forming method characterized in that the surface planarization process (CMP) has not been performed. In the semiconductor device manufacturing method comprising a laminated structure of a first device pattern and a second device pattern in contact with the first device pattern, (a) forming a lower structure provided with the first device pattern; (b) forming an etching target layer for forming a second device on the entire lower structure; (c) applying a photoresist composition on the result to form a photoresist film; (d) first exposing the photoresist film using the second device mask; (e) secondly exposing the top of the resultant product using the first device mask; And (f) developing the resultant to form a second device mask pattern. The method of claim 7, wherein The etching layer is a semiconductor device manufacturing method, characterized in that selected from the group consisting of oxide, polyoxide, nitride, BPSG, aluminum, tungsten, cobalt, organic diffuse reflection prevention material, inorganic diffuse reflection prevention material and titanium.