KR20010004437A - A circuit for reseting LIU on clock change - Google Patents

Abstract

PURPOSE: A reset circuit used in case of clock change in a multiplexer is provided which generates reset by software when a low-speed multiplexer changes its mode while operating to reset a line interface unit, thereby preventing generation of error when the clock is varied. CONSTITUTION: A reset circuit used in case of clock change in a multiplexer includes an E1 processor(10) for mapping E1 to multiplex it into TUG2 or demultiplex it, a T1 processor(20) for mapping T1 to multiplex it into TUG2 or demultiplex it, and a mode selector(40) for selecting the data/clock of the E1 processor or the data/clock of the T1 processor according to a mode selection signal. The reset circuit further includes a line interface chip(50), reset according to a reset signal, for line-coding and decoding a selected data/clock, and a switch(SW1) for setting an operation mode, and a processor(30) for operating the E1 processor or T1 processor based on the set operation mode, providing the mode selection signal to the mode selector and applying the reset signal to the line interface chip whenever the mode is changed.

Description

A circuit for reset LIU on clock change}

The present invention relates to an E1 / T1 unit of a digital transmission system, and more particularly, to a reset circuit during clock conversion in a low speed multiplexing unit supporting T1 and E1 clocks simultaneously.

In accordance with the trend toward compact communication systems, E1 and T1, which were provided as individual units in the conventional multiplexing device, have been improved to be provided in one unit. As it is possible to provide E1 and T1 in one unit, it is necessary to select either T1 clock or E1 clock according to the operation mode in using the widely used Line Interface Unit (LIU). .

In the past, when a single clock was used, the LIU chip was hardware-reset when the unit was mounted or dismounted.However, if two clock sources are used to change the clock source of the LIU chip during operation, it is impossible to reset the previous data. Since the signal path is affected, an error occurs in the transmission data.

Accordingly, the present invention has been made to solve the above problems, and when an E1 or T1 is processed by one multiplexing unit, an error is generated by software reset of the line matching (LIU) chip at the time of clock change. An object of the present invention is to provide a reset circuit when a clock is changed in a multiplexing device that can be prevented.

In order to achieve the above object, the apparatus of the present invention comprises: an E1 processing unit for multiplexing or demultiplexing E1 to TUG2; A T1 processing unit that maps T1 to multiplex or demultiplex to TUG2; A mode selector for selecting data / clock of the E1 processor or data / clock of the T1 processor according to a mode selection signal; A line matching chip which is reset according to the reset signal and line codes and decodes the selected data / clock; A switch for setting an operation mode; And a processor for operating the E1 processing unit or the T1 processing unit according to the setting of the operation mode, providing a mode selection signal to the mode selection unit, and providing a reset signal to the line matching chip every time the mode is changed. .

1 is a block diagram showing the configuration of a multiplexing apparatus according to the present invention;

2 is a detailed block diagram of an E1 processing unit shown in FIG. 1;

3 is a detailed block diagram of a T1 processing unit shown in FIG. 1;

4 is a flowchart for describing an operation of the processor illustrated in FIG. 1.

* Explanation of symbols for main parts of the drawings

10: E1 processing unit 20: T1 processing unit

30: processor 40: mode selector

50: line matching unit 60: reset unit

12,22: high speed multiplexing interface unit 14,24: transmitting unit

16, 26: receiver 18, 28: register

SW1: Mode selector switch

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram showing the configuration of a low speed multiplexing device according to the present invention. Referring to FIG. 1, the apparatus of the present invention includes an E1 processor 10, a T1 processor 20, a processor 30, a mode selector 40, a line matching chip (LIU) 50, and a hardware reset unit 60. , Oragate OR1 and mode selector switch SW1.

As shown in FIG. 2, the E1 processor 10 includes a high speed multiplexing interface unit 12, a transmitter 14, a receiver 16, and a register 18 to exchange information with the processor 30. In a synchronous multiplexing scheme, three DS1E signals are multiplexed along the paths DS1E-> C12-> VC12-> TU12-> TUG2 and demultiplexed inversely. At this time, the mapping method uses floating asynchronous mapping.

As shown in FIG. 3, the T1 processing unit 20 includes a high speed multiplexing interface unit 22, a transmitter unit 24, a receiver unit 26, and a register unit 28. -> C11-> VC11-> TU11-> TUG2 Multiplex and demultiplex along the path. At this time, the method of mapping the DS1 dependent signal to the VC11 multiframe uses floating asynchronous mapping, and the VC11 frame is composed of the DS1 dependent signal, fixed stuff and overhead, V5 path overhead, J2 byte, Z6 byte, and K5 byte. . Pointer processing is performed on this multiframe, a TUG2 signal is formed, transmitted to the high-speed multiplexer (AMUX), a pointer is interpreted from the TUG2 signal received from the high-speed multiplexer (MUX / DMUX), and each VC11 multiframe is extracted and routed. Overhead processing is performed to generate a received DS1 frame.

Although not shown in the figure, the high speed multiplexing interface unit 22 includes a TX TUG2 P / S converter, a TX INTER CP inserter, a TUG2 clock / data selector, an RX INTERCP detector, and an RX TUG2 S / P converter. Provides interface with high speed multiplexer (MUX / DEMUX). The transmitter 24 includes a decoder, a TX asynchronous buffer, a VC12 forming unit, a VC12 S / P converter, a TX synchronous buffer, an OH generator, a TUG2 forming unit, a pointer generating unit, a TX TUG clock control unit, and a TX VC12 clock control unit. Multiplex 1 DS1E or 4 DS1Ns. The receiver 26 includes a TUG / TU converter, an RX TUG clock controller, a DS1 AIS clock generator, a DS1 pattern generator, an RX synchronous buffer, a P / S converter, an RX asynchronous buffer, an encoder, a pointer processor, a TU12 clock controller, and a BLC processor. It consists of RX VC12 clock control unit and OH processing unit to demultiplex four DS1N.

In FIG. 2 and FIG. 3, "T6M" represents a transmission 6.912 MHz clock coming from the high speed multiplexer (MUX / DEMUX), and "R6M" represents a reception 6.912 MHz clock coming from the high speed multiplexer (MUX / DEMUX), and "T2K". "2KHz clock transmits from high-speed multiplexer", "R2K" indicates receive frame 2KHz clock, "RTUGD" represents receive 6Mbps serial data from high-speed multiplexer, "TTUGD" indicates transmit 6Mbps serial data to high-speed multiplexer Indicates. "DS1D" represents 1.544 Mbps DS1 data, "DS1CK" represents 1.544 MHz DS1 clock, "DS1ED" represents 2.048 Mbps DS1E data, and "DS1E CK" represents 2.048 MHz DS1E clock. "R / W" represents a read / write signal from the processor 30, and "CKS" is a 2.048 MHz interface clock coming from the processor 30.

Referring back to FIG. 1, the mode selector 40 receives a T1 clock (T1 CLK) and data (T1 DATA) from the T1 processor 20, and the E1 clock (E1 CLK) and data from the E1 processor 10. Receives (E1 DATA) and selects one clock (CLK) and data (DATA) according to the mode selection signal.

The line matching chip (LIU) 50 processes line coding and decoding to transfer data through a transmission line. That is, the line matching chip 50 lines-codes a 1.544 Mbps DS1N signal or a 2.048 Mbps DS1E signal using an AMI or B8ZS method and then inserts a predetermined forced violation signal to improve jitter characteristics during error correction and clock recovery. .

The hardware reset unit 60 provides a reset signal when the board is unmounted or powered on as in the prior art, and the oragate provides a software reset signal provided by the processor 30 and a reset signal of the hardware reset unit 60. To the LIU 50.

4 is a flowchart for describing an operation of the processor illustrated in FIG. 1.

Referring to FIG. 4, in step S1, a mode selection command is inputted. In step S2, it is determined whether the mode E1 is selected. If YES, in step S3, E1 clock and E1 data are selected. (LIU: 50) is reset, and in step S5, the E1 clock and E1 data are supplied to the line matching chip LIU: 50. In step S6, T1 clock and T1 data are selected in the T1 mode. In step S7, the line matching chip LIU: 50 is reset. In step S8, the T1 clock and T1 data are supplied to the line matching chip LIU 50. .

As described above, according to the present invention, when a mode is changed during operation in a low speed multiplexing device capable of multiplexing T1 and E1 with one unit, a line reset chip (LIU) can be reset by generating a software reset. Therefore, an error can be prevented from occurring when the clock is changed.

Claims (2)

An E1 processing unit that maps E1 to multiplex or demultiplex to TUG2; A T1 processing unit that maps T1 to multiplex or demultiplex to TUG2; A mode selector for selecting data / clock of the E1 processor or data / clock of the T1 processor according to a mode selection signal; A line matching chip which is reset according to the reset signal and line codes and decodes the selected data / clock; A switch for setting an operation mode; And When the clock is changed in a multiplexing device including a processor operating an E1 processing unit or a T1 processing unit according to the set operation mode, providing a mode selection signal to the mode selection unit, and providing a reset signal to the line matching chip every time the mode is changed. Reset circuit. The method of claim 1, wherein the E1 processing unit, A high speed multiplexing interface unit for providing an interface with the high speed multiplexing unit; A transmission unit multiplexing an E1 signal and providing the same to the high speed multiplexing interface unit; A receiver which demultiplexes an E1 signal received from the high speed multiplexing interface unit; And a register unit for receiving a control value from a processor and providing the control value to each unit.