KR100237456B1 - Frame structure for time divisional multiplex - Google Patents

Abstract

A frame structure for data channel multiplexing is provided. This frame structure is characterized in that 8 information blocks each consisting of 5 8-bit timeslots are contiguous in order to multiplex data having a transmission rate of 64 kilobytes per second in a time division multiplexing transmission equipment.

Description

Frame structure for multiplexing

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for multiplexing and transmitting multiple low bit rate channels at a high bit rate in a communication system, and more particularly to a frame structure for multiplexing four 64 kbps data to 320 kbps.

In recent years, transmission equipment has been shifting to synchronous hierarchy. A representative advantage is the convenience of network monitoring. In addition, the design of the promised rules means that signals of the same bit rate can be accessed without any modification. Synchronous Digital Hierachy (SDH) is referred to by ITU-T as SOH (Setion Over-Head).

One important aspect of communication is how much information can be sent and received over a limited channel. This can be implemented as a method of multiplexing a low bit rate signal into multiple channels to transmit at a high bit rate. In other words, a low frequency signal is transmitted on a high frequency by using time division multiplexing technology. In order to multiplex a low frequency signal to a high frequency as described above, a predetermined protocol is required to extract data by demultiplexing the receiver. This convention is called a frame structure.

Accordingly, an object of the present invention is to provide a frame structure for multiplexing four 64kbps data to 320kbps.

In order to achieve the above object, the present frame structure allows 8 information blocks consisting of five 8-bit time slots to be contiguous in order to multiplex data having a transmission rate of 64 Kbps in a time division multiplexing transmission equipment. It features.

1 is a view showing a schematic configuration of a communication equipment to which the present invention is applied

2 illustrates a frame structure for multiplexing according to an embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. First of all, in adding reference numerals to the components of each drawing, it should be noted that the same reference numerals have the same reference numerals as much as possible even if displayed on different drawings. Also, in the following description, many specific details such as components of specific circuits are shown, which are provided to help a more general understanding of the present invention, and the present invention may be practiced without these specific details. It is self-evident to those of ordinary knowledge in Esau. In the following description of the present invention, if it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

1 is a view showing a schematic configuration of communication equipment to which the present invention is applied. The inputs of the multiplexer 100, i.e., the outputs of the transmitting data ports DP1 to DP4, each have a data transfer rate of 64 Kbps. The multiplexer 100 and the demultiplexer 200 communicate by wire or wirelessly. The output of the demultiplexer 200, that is, the inputs of the receiving data ports DP5 to DP8 also have a data transfer rate of 64 Kbps.

2 is a diagram illustrating a frame structure for multiplexing, that is, multiplexing 64 channels of 64kbps data to 320kbps according to an embodiment of the present invention. As shown in the drawing, it has a multi-frame structure incorporating four sub-frames corresponding to the reference numerals SB1 to SB4, respectively. The four subframes SB1 to SB4 all contain a basic frame of 125 ms, a parity byte P, error correction bytes C1 to C5, and stuffing bytes.

Each subframe is for processing one 64kbps data channel, and the multiplexing transmits data in a magnetic timeslot determined by a time division multiplexing scheme. Each subframe has a period of 1 ms in a structure of '8 [bit] × 5 [H1234] × 8 [All kind of H bytes]'.

As shown, the first subframe SB1 includes a frame byte F indicating the start of the frame in a basic frame of 125 ms unlike the other three subframes. That is, when the frame byte is inserted into the first byte of the first basic frame among the four subframes constituting the multi-frame as 8 bits and transmitted, the frame byte is detected and the time slot is reproduced in the demultiplexing process.

Even parity check is performed for each channel for line monitoring of the powering device, and the result is inserted as parity byte P. In the playing device, the parity byte is used for error searching.

The error correction bytes C1 to C5 indicate whether there is stuffing for the corresponding channel, and the same data is repeatedly inserted and sent five times in order to allow error correction during the demultiplexing process. This is also performed for each channel, and in this embodiment, a logic correction method using '3 out of 5' parity is used for error correction occurring in a transmission section.

When each data port detects a positive or negative stuffing request, the multiplexer 100 sends a contracted code, and the demultiplexer 200 controls the stuffing byte designated for each channel according to the received code. . Specifically, the case where the reception clock is later in frequency than the transmission clock is positive, and data of the channel where the stuffing request is generated is not transmitted. This can be done by disabling the timeslot of the channel. On the contrary, a case in which the transmission clock frequency is faster than the reception clock is called negative and data is added once more to the stuffing byte slot "0" of the corresponding channel subframe in which the stuffing request is generated and transmitted.

In the above description, the first subframe SB1 is described as follows. Data input to the first data port DP1 is actually stored in an external memory (for example, SRAM (static RAM)), not shown, and read by the multiplexer 100 (processor). When the multiplexer 100 reads the data from the memory, the multiplexer 100 should read the same clock. Therefore, the first data port DP1 compares the frequency of the write clock generated by the first data port DP1 with the read clock generated by the multiplexer 100 and makes an appropriate adjustment when either one is early or late. That is, when the reception clock frequency is later than the transmission clock frequency, a positive code, for example, "O000" is inserted into the error correction bytes C1 to C5 and transmitted. In this manner, when the seventh information block of the first subframe SB1 is transmitted and then the eighth information block is transmitted, the time slot "0" as well as the time slot "1" as well as the "0" time slot (I) are also positive. Adjust synchronization by emptying without data. When the demultiplexing apparatus detects that the error correction bytes C1 to C5 are positive codes when demultiplexing, it can be known in advance that there is no reception of data in the times slots "0" and "1". However, if it is assumed that the result of receiving the positive code 'O0O00' from the power device is 'O1O00', this is a logic correction method using the above-described '3 out of 5' parity, although an error occurred in the transmission step. When four of the five codes are identical, it is considered normal transmission.

On the contrary, in the case of a negative code, synchronization is adjusted by additionally transmitting data in the time slot "0" as well as the time slot "1" which is its own time slot. In other words, the same data is repeatedly transmitted in times slots "0" and "1". At this time, the station apparatus receives the error correction bytes C1 to C5 and detects that the result is a negative code. As a result, data is received in the times slots "0" and "1".

Like the above, the remaining subframes SB2 to SB4 are synchronized by additionally inserting or emptying data in the corresponding timeslot (D, D) or (D, D) or (D, D).

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications may be made without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined not only by the scope of the following claims, but also by the equivalents of the claims.

As described above, the present invention has an advantage of being able to multiplex into 64 channels of 64kbps data and 320kbps. In addition, the present frame structure can apply a logic correction method based on a predetermined parity, so that an error occurring in a transmission section can be corrected.

Claims (12)

In a frame structure for multiplexing data having a transmission rate of 64 kilobytes per second in a time division multiplexing transmission equipment, Frame structure characterized in that the eight information blocks of five timeslots as a unit consists of eight consecutive. The method of claim 1, Wherein any information block has a parity byte, at least one other information block has an error correction byte, and another information block includes a stuffing byte. The method of claim 2, And a stuffing byte corresponding timeslot for sending data of a channel having a stuffing request once more when the transmit clock frequency is faster than the receiving clock. The method according to claim 2 or 3, And if the received clock frequency is later than the transmit clock frequency, disable the corresponding timeslot to transmit data of the channel where the stuffing request occurs. The method of claim 1, Frame structure characterized in that the first byte of the first information block is a byte indicating the start of the frame. The method of claim 1, wherein the error correction byte, Frame structure, characterized in that inserted into each one of five information blocks. In a frame structure for multiplexing four data having a transmission rate of 64 kilobytes per second in a time division multiplexing transmission equipment at a transmission rate of 320 kilobytes, A frame structure, characterized by having four subframes in which eight information blocks in units of five 8-bit timeslots are contiguous. The method of claim 7, wherein in each of the subframes, Wherein any information block has a parity byte, at least one other information block has an error correction byte, and another information block includes a stuffing byte. The method of claim 8, And a stuffing byte corresponding timeslot for sending data of a channel having a stuffing request once more when the transmit clock frequency is faster than the receiving clock. The method according to claim 8 or 9, And a stuffing byte corresponding timeslot for sending data of a channel having a stuffing request once more when the transmit clock frequency is faster than the receiving clock. The method of claim 7, wherein Frame structure characterized in that the first byte of the first information block of the first subframe is a byte indicating the start of the frame. The method of claim 7, wherein the error correction byte, Frame structure, characterized in that inserted into each one of five information blocks.

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