KR20000072897A - method of manufacturing semiconductor device - Google Patents
method of manufacturing semiconductor device Download PDFInfo
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- KR20000072897A KR20000072897A KR1019990015847A KR19990015847A KR20000072897A KR 20000072897 A KR20000072897 A KR 20000072897A KR 1019990015847 A KR1019990015847 A KR 1019990015847A KR 19990015847 A KR19990015847 A KR 19990015847A KR 20000072897 A KR20000072897 A KR 20000072897A
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- film
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- interlayer insulating
- via contact
- insulating film
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000010410 layer Substances 0.000 claims abstract description 63
- 238000000034 method Methods 0.000 claims abstract description 44
- 239000011229 interlayer Substances 0.000 claims abstract description 43
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 42
- 238000005530 etching Methods 0.000 claims abstract description 21
- 239000004020 conductor Substances 0.000 claims abstract description 8
- 239000010949 copper Substances 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- 239000007769 metal material Substances 0.000 claims description 2
- 230000000149 penetrating effect Effects 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 239000010937 tungsten Substances 0.000 claims description 2
- 238000009413 insulation Methods 0.000 abstract 5
- 230000004888 barrier function Effects 0.000 description 5
- 239000011521 glass Substances 0.000 description 3
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- HIVGXUNKSAJJDN-UHFFFAOYSA-N [Si].[P] Chemical compound [Si].[P] HIVGXUNKSAJJDN-UHFFFAOYSA-N 0.000 description 1
- MXSJNBRAMXILSE-UHFFFAOYSA-N [Si].[P].[B] Chemical compound [Si].[P].[B] MXSJNBRAMXILSE-UHFFFAOYSA-N 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 장치의 제조 방법에 관한 것으로서, 특히 이중-상감 기술을 이용한 반도체 장치의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device using a double damascene technique.
최근 반도체 장치가 고집적화됨에 따라 회로의 구조가 평면구조에서 수직구조로 변화되고 있으며, 이에 따라 배선의 구조도 다층화되고 있는 실정이다. 이처럼 반도체 장치의 배선 구조가 다층화됨에 따라 콘택홀의 종횡비(aspect ratio)가 증가되고 있어 종래의 배선 방법으로는 배선의 비평탄화, 불량한 스텝 커버리지(step coverage), 잔류성 금속 단락, 낮은 수율, 및 신뢰성의 열화 등과 같은 문제점들이 발생하게 된다.Recently, as semiconductor devices have been highly integrated, the circuit structure has been changed from a planar structure to a vertical structure. As a result, the structure of the wiring is also multilayered. As the wiring structure of the semiconductor device is multilayered, the aspect ratio of the contact hole increases, and thus, conventional wiring methods include uneven wiring, poor step coverage, residual metal short circuit, low yield, and reliability. Problems such as deterioration will occur.
따라서, 본 분야에서는 상기한 종래의 문제점들을 해결하기 위한 새로운 배선 기술로서 하부 배선과 상부 배선을 전기적으로 연결하는 비아콘택과 상부 배선을 동시에 형성하는 소위, "이중-상감(Dual Damascene)" 공정을 개발하게 되었으며, 이러한 이중-상감 공정은 현재 디램(DRAM)의 비트라인 및 다이렉트 콘택(Direct Contact)을 형성하거나, 에스램(SRAM)의 국부(local) 배선을 형성하는 공정에 널리 이용되고 있다. 또한, 향후 구리(Cu)를 이용한 초미세 배선을 형성함에 있어서 필수적으로 수행되어질 공정으로 전망되고 있다.Accordingly, in this field, a so-called "Dual Damascene" process for simultaneously forming a via contact and an upper interconnection electrically connecting the lower interconnection and the upper interconnection as a new interconnection technique for solving the above-described problems is employed. The dual-inlay process is now widely used in the process of forming bit lines and direct contacts of DRAMs or local wiring of SRAMs. In addition, in the future, it is expected that the process to be essentially performed in forming ultra fine wiring using copper (Cu).
상기 이중-상감 공정은 통상적으로 하부배선막 상부에 제1층간절연막을 형성한 뒤, 상기 제1층간절연막을 후속의 식각공정으로부터 보호하기 위한 식각방지막을 형성한다. 그리고 나서, 상기 식각방지막 상부에 제2층간절연막을 형성한 뒤, 사진 및 식각공정을 실시하여 상기 제2층간절연막에서부터 하부배선막에 이르는 비아 콘택홀을 형성한다. 이어서, 상기 제2층간절연막의 소정영역 및 비아 콘택홀에 감광막을 형성한 뒤, 이를 자기정렬된 식각마스크로서 이용하여 식각공정을 실시함으로써, 상기 하부배선막과 비아 콘택을 통해 전기적으로 연결되어질 상부배선용 트렌치가 형성된다.The double damascene process typically forms a first interlayer insulating film over the lower wiring film, and then forms an etch stop layer for protecting the first interlayer insulating film from subsequent etching. Thereafter, a second interlayer insulating layer is formed on the etch stop layer, and a photo contact and an etching process are performed to form a via contact hole from the second interlayer insulating layer to the lower wiring layer. Subsequently, after forming a photoresist film in a predetermined region and a via contact hole of the second interlayer insulating film, an etching process is performed using the photoresist film as a self-aligned etching mask, thereby forming an upper portion to be electrically connected through the lower wiring film and the via contact. A wiring trench is formed.
그러나 상술한 종래의 이중-상감 공정에 따르면, 트렌치 형성을 위한 상기 제2층간절연막 식각시에 상기 비아 콘택홀 내의 감광막이 식각방지막에 비해 보다 낮은 위치에 형성되어 있어 식각방지막이 노출된다. 따라서, 트렌치 형성을 위한 식각공정시 제2층간절연막이 식각되는 과정에서 발생된 플라즈마가 CFx(x는 자연수)계 플라즈마인 경우에 C 또는 CFx 래디컬을 소모하여 상기 식각방지막을 보호할 수 있는 폴리머가 적어 식각방지막이 쉽게 식각된다. 그 결과, 비아 콘택홀의 임계치수가 변화되어 원하는 패턴의 비아 콘택을 형성할 수 없게 되는 문제점이 있다. 한편, 상기와 같은 종래의 문제점을 해소하기 위해, 상기 식각방지막을 두껍게 형성할 경우, 공정시간 및 단가가 증가되는 단점이 있으며, 상기한 종래의 문제점 또한 완전하게 해소되지 못한다.However, according to the above-described conventional double-inlay process, the photoresist layer in the via contact hole is formed at a lower position than the etch stop layer during the second interlayer insulating layer etching to form the trench, thereby exposing the etch stop layer. Therefore, when the plasma generated in the process of etching the second interlayer insulating film during the etching process for forming the trench is a CFx (x is a natural number) plasma, a polymer capable of protecting the etch stop layer by consuming C or CFx radicals As a result, the etch barrier is easily etched. As a result, there is a problem in that the critical dimension of the via contact hole is changed so that a via contact having a desired pattern cannot be formed. On the other hand, in order to solve the above problems, there is a disadvantage in that the process time and unit cost is increased when the etch barrier is formed thick, the above problems are not completely solved.
따라서 본 발명의 목적은, 상기한 종래의 문제점을 해소할 수 있는 이중-상감 공정을 제공함에 있다.It is therefore an object of the present invention to provide a double-inlay process that can solve the above-mentioned conventional problems.
본 발명의 다른 목적은, 식각방지막의 손상을 방지할 수 있는 이중-상감 기술을 이용한 반도체 장치의 제조 방법을 제공함에 있다.Another object of the present invention is to provide a method of manufacturing a semiconductor device using a double-inlay technique capable of preventing damage to an etch stop layer.
본 발명의 또 다른 목적은, 비아콘택용 개구의 프로파일을 변화시키지 않는 개선된 이중-상감 기술을 이용한 반도체 장치의 제조 방법을 제공함에 있다.It is still another object of the present invention to provide a method of manufacturing a semiconductor device using an improved double-inlay technique that does not change the profile of the opening for via contact.
상기의 목적들을 달성하기 위해서 본 발명에서는, 배선과 비아 콘택을 동시에 구현하는 이중-상감 기술을 이용한 반도체 장치의 제조 방법에 있어서: 하부도전막 상부에 제1층간절연막 및 제2층간절연막을 차례로 형성하는 단계와; 상기 제2층간절연막 및 제1층간절연막을 관통하여 상기 하부도전막에 이르는 비아 콘택용 개구를 형성하는 단계와; 상기 비아 콘택용 개구가 채워지도록 제1감광막을 형성하는 단계와; 상기 개구가 포함되는 트렌치를 형성하기 위해, 상기 제2층간절연막의 소정영역 상부에 상기 제1감광막과는 반대되는 현상 타입의 제2감광막을 형성하는 단계와; 상기 제2감광막을 식각마스크로서 이용하여 제2층간절연막을 식각하여 트렌치를 형성한 뒤, 상기 트렌치 및 개구에 도전물을 채움으로써, 비아 콘택 및 상부도전막을 동시에 구현하는 단계를 포함함을 특징으로 하는 이중-상감 기술을 이용한 반도체 장치의 제조 방법을 제공한다.SUMMARY OF THE INVENTION In order to achieve the above objects, the present invention provides a method of manufacturing a semiconductor device using a double damascene technique that simultaneously implements wiring and via contacts. A first interlayer insulating film and a second interlayer insulating film are sequentially formed on a lower conductive film. Making a step; Forming an opening for a via contact penetrating through said second interlayer insulating film and said first interlayer insulating film to reach said lower conductive film; Forming a first photoresist film to fill the via contact opening; Forming a second photoresist film of a development type opposite to the first photoresist film on a predetermined region of the second interlayer insulating film to form a trench including the opening; And forming a trench by etching the second interlayer insulating layer using the second photoresist layer as an etch mask, and then filling the trench and the opening with a conductive material to simultaneously form a via contact and an upper conductive layer. To provide a method of manufacturing a semiconductor device using a double-inlay technique.
도 1a 내지 도 1f는 본 발명의 바람직한 실시예에 따른 이중-상감 공정을 설명하기 위한 단면도들이다.1A-1F are cross-sectional views illustrating a dual-laid process in accordance with a preferred embodiment of the present invention.
이하, 본 발명의 바람직한 실시예를 첨부한 도면을 참조하여 상세히 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1f는 본 발명의 바람직한 실시예에 따른, 이중-상감 기술을 이용한 반도체 장치의 제조 방법을 설명하기 위한 단면도들이다.1A to 1F are cross-sectional views illustrating a method of manufacturing a semiconductor device using a double-inlay technique according to a preferred embodiment of the present invention.
도 1a는 제1층간절연막(102), 식각방지막(104) 및 제2층간절연막(106)을 형성하는 단계를 나타낸다. 억세스 트랜지스터가 형성되어 있는 반도체 기판 또는 금속막등의 하부도전층(100) 상부에 절연물질로서 예컨대 PSG(Phosphorus Silicon Glass), BPSG(Boron Phosphorus Silicon Glass) 또는 USG(Undoped Silicon Glass)등과 같은 산화막을 증착하여 제1층간절연막(102)을 형성한다. 이어서, 상기 제1층간절연막(102) 상부에 상기 제1층간절연막(102)에 대해 높은 식각 선택비를 갖는 물질로서, 예컨대 SiN 또는 SiON을 증착하여 식각방지막(104)을 형성한다. 이때, 상기 식각방지막(104)은 형성하지 않아도 무관하다.FIG. 1A illustrates a step of forming the first interlayer dielectric layer 102, the etch stop layer 104, and the second interlayer dielectric layer 106. An oxide film such as PSG (Phosphorus Silicon Glass), BPSG (Boron Phosphorus Silicon Glass), or USG (Undoped Silicon Glass), or the like is formed as an insulating material on the lower conductive layer 100 such as a semiconductor substrate or a metal film on which the access transistor is formed. By depositing, a first interlayer insulating film 102 is formed. Subsequently, as the material having a high etching selectivity with respect to the first interlayer insulating layer 102 on the first interlayer insulating layer 102, for example, SiN or SiON is deposited to form an etch stop layer 104. In this case, the etch stop layer 104 may not be formed.
계속해서, 상기 식각방지막(104)과 높은 식각 선택비를 갖는 예컨대 산화막을 증착하여 제2층간절연막(106)을 형성한다. 여기서, 상기 제2층간절연막(106) 또한 PSG, BPSG 또는 USG등과 같은 산화막으로 형성할 수 있다.Subsequently, for example, an oxide film having a high etching selectivity with the etch stop film 104 is deposited to form a second interlayer insulating film 106. The second interlayer insulating film 106 may also be formed of an oxide film such as PSG, BPSG, or USG.
도 1b는 상기 결과물의 소정 영역에 비아 콘택홀(108)을 형성하는 단계를 나타낸다. 상기 제2층간절연막(106)의 상부에 감광막(도시하지 않음)을 형성한 뒤, 상기 하부도전층(100)과 후속의 공정을 통해 형성되어질 상부도전층간을 전기적으로 접속시키는 비아 콘택이 형성되어질 영역만을 노광하여 감광막을 제거한다. 그리고 나서, 상기 감광막 패턴을 식각마스크로 이용하여 상기 제2층간절연막(106), 식각방지막(104) 및 제1층간절연막(102)을 식각함으로써 비아 콘택홀(108)을 형성한다.1B illustrates a step of forming a via contact hole 108 in a predetermined region of the resultant product. After forming a photoresist film (not shown) on the second interlayer insulating film 106, a via contact for electrically connecting the lower conductive layer 100 and the upper conductive layer to be formed through a subsequent process is formed. Only the area is exposed to remove the photosensitive film. Then, the via contact hole 108 is formed by etching the second interlayer insulating film 106, the etch stop film 104, and the first interlayer insulating film 102 by using the photoresist pattern as an etching mask.
도 1c는 상기 비아 콘택홀(108)에 제1감광막(110)을 채우는 단계를 나타낸다. 상기 비아 콘택홀(108)이 형성되어 있는 결과물의 전면 상부에 스핀코팅(spin coating)법등을 이용하여 제1감광막(110)을 형성한 뒤, 산소 플라즈마 분위기에서 에치백 공정을 실시한다. 이때, 상기 제1감광막(110)은 노광된 부분이 현상되는 포지티브(positive) 타입과 노광되지 않은 부분이 현상되는 네거티브(negative) 타입의 감광막중 어느 하나를 사용하며, 후속의 식각공정으로부터 상기 식각방지막(104)의 손상을 최소화하기 위해 식각방지막(104)에 비해 보다 높게 형성한다.FIG. 1C illustrates filling the via contact hole 108 with the first photoresist layer 110. After forming the first photoresist layer 110 by using a spin coating method on the upper surface of the resultant in which the via contact hole 108 is formed, an etch back process is performed in an oxygen plasma atmosphere. In this case, the first photoresist layer 110 may use either a positive type in which an exposed part is developed or a negative type in which an unexposed part is developed, and the etching may be performed from a subsequent etching process. In order to minimize damage to the barrier layer 104, the barrier layer 104 may be formed higher than the etch barrier layer 104.
도 1d는 상기 제2층간절연막(106)의 상부에 제2감광막(112)을 형성하는 단계를 나타낸다. 상기 에치백(etch back) 공정을 완료한 후에 상기 제1감광막(110)과는 반대 타입의 제2감광막(112)을 상기 결과물의 소정 영역 상부에 형성한다. 즉, 상기 제1감광막(110)을 포지티브 타입의 감광막으로 형성하였을 경우에는 상기 제2감광막(112)은 네거티브 타입의 감광막으로, 이와 반대로 상기 제1감광막(110)을 네거티브 타입의 감광막으로 형성하였을 경우에는 상기 제2감광막(112)은 포지티브 타입의 감광막으로 형성한다. 이처럼 상기 제1감광막(110)은 제2감광막(112)과 반대 타입의 감광막으로 형성되어 있으므로, 제2감광막(112) 형성을 위한 노광시 현상되지 않는다.FIG. 1D illustrates forming a second photoresist layer 112 on the second interlayer insulating layer 106. After the etch back process is completed, a second photoresist layer 112 of a type opposite to the first photoresist layer 110 is formed on a predetermined region of the resultant. That is, when the first photoresist film 110 is formed of a positive photoresist film, the second photoresist film 112 is a negative photoresist film. On the contrary, the first photoresist film 110 is formed of a negative photoresist film. In this case, the second photoresist layer 112 is formed of a positive photoresist layer. As such, since the first photoresist layer 110 is formed of a photoresist film of a type opposite to the second photoresist layer 112, the first photoresist layer 110 is not developed during exposure for forming the second photoresist layer 112.
도 1e는 상기 제2층간절연막(106)에 트렌치(114)를 형성하는 단계를 나타낸다. 상기 제2감광막(112) 패턴을 식각마스크로서 이용하여 제2층간절연막(106)을 건식식각한다. 그 결과, 상기 제2감광막(112) 패턴대로 제2층간절연막(106)이 식각되어 후속의 공정을 통해 상부도전층이 형성되어질 트렌치(114)가 형성된다.FIG. 1E illustrates a step of forming a trench 114 in the second interlayer insulating film 106. The second interlayer insulating film 106 is dry etched using the second photoresist film 112 as an etching mask. As a result, the second interlayer insulating layer 106 is etched according to the pattern of the second photoresist layer 112 to form a trench 114 in which an upper conductive layer is to be formed through a subsequent process.
이때, 상기 식각방지막(104)은 제2층간절연막(106)과 식각 선택비가 높으므로 트렌치(114)를 형성하기 위한 건식식각 공정시 손상되지 않으며, 그 두께 또한 종래에 비해 얇게 형성할 수 있는 장점이 있다. 또한, 식각방지막(104)에 비해 높게 형성되어 있는 제1감광막(110)으로 인해 트렌치(114) 형성을 위한 건식식각 공정으로부터 보다 완벽하게 보호될 수 있으며, 상기 식각방지막(104) 없이도 식각이 가능하므로 공정단계를 줄일수 있는 잇점이 있다.In this case, since the etch stop layer 104 has a high etching selectivity with the second interlayer insulating layer 106, the etch stop layer 104 is not damaged during the dry etching process for forming the trench 114, and the thickness thereof may also be thinner than in the related art. There is this. In addition, the first photoresist layer 110 formed higher than the etch stop layer 104 may be more completely protected from the dry etching process for forming the trench 114, and may be etched without the etch stop layer 104. This has the advantage of reducing process steps.
도 1f는 비아 콘택(116) 및 상부도전층(118)을 형성하는 단계를 나타낸다. 상기 제1감광막(110) 및 제2감광막(112)을 에싱(ashing) 공정등을 실시하여 완전히 제거한다. 그리고 나서, 상기 비아 콘택홀(108) 및 트렌치(114)를 완전히 매립할 수 있을 정도의 두께로 도전물을 형성한 후, 상기 제2층간절연막(106)이 노출될때까지 상기 도전물을 화학 기계적 연마(CMP:Chemical Mechanical Polishing) 방법으로 식각함으로써 상부도전층(118), 그리고 상기 상부도전층(118)과 하부도전층(100)을 전기적으로 연결하는 비아 콘택(116)을 형성한다. 예컨대, 상기 도전물로서는, 텅스텐, 알루미늄, 구리등과 같은 금속물질막을 이용하거나 기타 도전물을 이용하여 형성한다.1F illustrates forming via contact 116 and top conductive layer 118. The first photoresist film 110 and the second photoresist film 112 may be completely removed by an ashing process or the like. Then, the conductive material is formed to a thickness sufficient to completely fill the via contact hole 108 and the trench 114, and then the conductive material is chemically mechanically exposed until the second interlayer insulating film 106 is exposed. By etching by chemical mechanical polishing (CMP), an upper conductive layer 118 and a via contact 116 electrically connecting the upper conductive layer 118 and the lower conductive layer 100 are formed. For example, the conductive material may be formed using a metal material film such as tungsten, aluminum, copper, or the like or other conductive material.
상술한 바와 같이, 본 발명의 바람직한 실시예를 참조하여 설명하였지만 해당 기술 분야의 숙련된 당업자라면 하기의 특허 청구의 범위에 기재된 본 발명의 사상 및 영역으로부터 벗어나지 않는 범위 내에서 본 발명을 다양하게 수정 및 변경시킬 수 있음을 이해할 수 있을 것이다.As described above, although described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified without departing from the spirit and scope of the invention described in the claims below. And can be changed.
상기한 바와 같이 본 발명에서는 상부도전층과 비아 콘택을 동시에 형성하기 위한 이중-상감 공정을 실시함에 있어서, 비아 콘택을 형성하기 위한 비아 콘택홀 내부에 제1감광막을 식각방지막의 위치보다 높게 채움으로써, 트렌치 형성을 위한 식각공정시에 상기 식각방지막이 손상되는 것을 방지하게 된다. 그 결과, 비아 콘택홀의 임계치수가 변화되지 않아, 양호한 프로파일의 비아 콘택을 얻을 수 있는 효과가 있다.As described above, in the present invention, in performing the double-inlay process for simultaneously forming the upper conductive layer and the via contact, the first photoresist film is filled in the via contact hole for forming the via contact higher than the position of the etch stop layer. In the etching process for forming the trench, the etch stop layer is prevented from being damaged. As a result, the critical dimension of the via contact hole does not change, and there is an effect that a via profile having a good profile can be obtained.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100366639B1 (en) * | 2001-03-23 | 2003-01-06 | 삼성전자 주식회사 | A method for formation of contact having low resistivity using porous oxide plug and methods for forming semiconductor devices using the same |
| KR100393974B1 (en) * | 2001-01-12 | 2003-08-06 | 주식회사 하이닉스반도체 | Forming Method for Dual Damascene |
| KR100772719B1 (en) * | 2001-12-31 | 2007-11-02 | 주식회사 하이닉스반도체 | A method for metal wire using dual damascene process |
| KR100780244B1 (en) * | 2006-08-24 | 2007-11-27 | 동부일렉트로닉스 주식회사 | Cmos image sensor and a method of fabricating the same |
| KR100884987B1 (en) * | 2007-08-27 | 2009-02-23 | 주식회사 동부하이텍 | Method for forming cu metal line of semiconductor device |
-
1999
- 1999-05-03 KR KR1019990015847A patent/KR20000072897A/en not_active Application Discontinuation
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100393974B1 (en) * | 2001-01-12 | 2003-08-06 | 주식회사 하이닉스반도체 | Forming Method for Dual Damascene |
| KR100366639B1 (en) * | 2001-03-23 | 2003-01-06 | 삼성전자 주식회사 | A method for formation of contact having low resistivity using porous oxide plug and methods for forming semiconductor devices using the same |
| KR100772719B1 (en) * | 2001-12-31 | 2007-11-02 | 주식회사 하이닉스반도체 | A method for metal wire using dual damascene process |
| KR100780244B1 (en) * | 2006-08-24 | 2007-11-27 | 동부일렉트로닉스 주식회사 | Cmos image sensor and a method of fabricating the same |
| KR100884987B1 (en) * | 2007-08-27 | 2009-02-23 | 주식회사 동부하이텍 | Method for forming cu metal line of semiconductor device |
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