KR20000033430A - Method for manufacturing semiconductor device utilizing dual-damascene - Google Patents
Method for manufacturing semiconductor device utilizing dual-damascene Download PDFInfo
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- KR20000033430A KR20000033430A KR1019980050280A KR19980050280A KR20000033430A KR 20000033430 A KR20000033430 A KR 20000033430A KR 1019980050280 A KR1019980050280 A KR 1019980050280A KR 19980050280 A KR19980050280 A KR 19980050280A KR 20000033430 A KR20000033430 A KR 20000033430A
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- insulating film
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- 238000000034 method Methods 0.000 title claims abstract description 41
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 238000000059 patterning Methods 0.000 claims abstract description 6
- 239000004020 conductor Substances 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 238000001312 dry etching Methods 0.000 claims description 17
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 2
- 238000005530 etching Methods 0.000 abstract description 7
- 238000009413 insulation Methods 0.000 abstract 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 장치의 제조 방법에 관한 것으로서, 특히 이중-상감 기술을 이용한 반도체 장치의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device using a double damascene technique.
최근 반도체 장치가 고집적화됨에 따라 회로의 구조가 평면구조에서 수직구조로 변화되고 있으며, 이에 따라 배선의 구조도 다층화되고 있는 실정이다. 이처럼 반도체 장치의 배선 구조가 다층화됨에 따라 콘택홀의 종횡비(aspect ratio)가 증가되고 있어 종래의 배선 방법으로는 배선의 비평탄화, 불량한 스텝 커버리지(step coverage), 잔류성 금속 단락, 낮은 수율, 및 신뢰성의 열화 등과 같은 문제점들이 발생하게 된다.Recently, as semiconductor devices have been highly integrated, the circuit structure has been changed from a planar structure to a vertical structure. As a result, the structure of the wiring is also multilayered. As the wiring structure of the semiconductor device is multilayered, the aspect ratio of the contact hole increases, and thus, conventional wiring methods include uneven wiring, poor step coverage, residual metal short circuit, low yield, and reliability. Problems such as deterioration will occur.
따라서, 본 분야에서는 상기한 종래의 문제점들을 해결하기 위한 새로운 배선 기술로서 하부 배선과 상부 배선을 전기적으로 연결하는 비아콘택과 상부 배선을 동시에 형성하는 소위, "이중-상감(Dual Damascene)" 기술을 개발하게 되었으며, 이러한 이중-상감 기술은 현재 디램(DRAM)의 비트라인 및 다이렉트 콘택(Direct Contact)을 형성하거나, 에스램(SRAM)의 국부(local) 배선을 형성하는 공정에 널리 이용되고 있다. 또한, 향후 구리(Cu)를 이용한 초미세 배선을 형성함에 있어서 필수적으로 수행되어질 공정으로 전망되고 있다.Therefore, in this field, a so-called "Dual Damascene" technique for simultaneously forming a via contact and an upper interconnection electrically connecting the lower interconnection and the upper interconnection as a new interconnection technique for solving the above-described problems is employed. This dual-inlay technology is now widely used in the process of forming bit lines and direct contacts of DRAMs or local wiring of SRAMs. In addition, in the future, it is expected that the process to be essentially performed in forming ultra fine wiring using copper (Cu).
도 1a 내지 도 1d는 종래 방법에 따른 통상적인 이중-상감 공정순서를 나타내는 단면도들이다.1A-1D are cross-sectional views illustrating a conventional double-inlay process sequence according to a conventional method.
도 1a를 참조하면, 반도체 기판(10) 상부에 제1절연막(12) 및 스토퍼막(14)을 형성한 뒤, 사진 및 건식식각공정을 실시하여 상기 스토퍼막(14)을 패터닝한다. 이어서, 상기 패터닝된 스토퍼막(14) 상부에 제2절연막(16)을 형성한 뒤, 상기 제2절연막(16) 및 제1절연막(12)을 건식식각하기 위한 마스크(18)를 형성한다.Referring to FIG. 1A, after forming the first insulating film 12 and the stopper film 14 on the semiconductor substrate 10, the stopper film 14 is patterned by performing a photolithography and a dry etching process. Subsequently, after the second insulating layer 16 is formed on the patterned stopper layer 14, a mask 18 for dry etching the second insulating layer 16 and the first insulating layer 12 is formed.
도 1b를 참조하면, 상기 마스크(18)를 이용하여 상기 제2절연막(16) 및 제1절연막(12)에 건식식각 공정을 실시한다. 그 결과, 상기 제2절연막(16)에는 상기 마스크(18)패턴에 따른 배선용 트렌치(20)가 형성되며, 제1절연막(12)에는 상기 스토퍼막(14)의 패턴에 따라 상기 트렌치(20)에 비해 보다 협소한 비아콘택용 개구(22)가 형성된다. 이와 같이 형성된 배선용 트렌치(20) 및 비아콘택용 개구(22)에 도전물질을 채워넣음으로써 배선과 비아콘택을 동시에 구현하는 이중-상감 공정을 완료하게 된다.Referring to FIG. 1B, a dry etching process may be performed on the second insulating layer 16 and the first insulating layer 12 using the mask 18. As a result, a wiring trench 20 in accordance with the mask 18 pattern is formed in the second insulating layer 16, and the trench 20 is formed in the first insulating layer 12 in accordance with the pattern of the stopper layer 14. A narrower via contact opening 22 is formed than. The conductive material is filled in the wiring trench 20 and the via contact opening 22 formed as described above to complete the double-inlay process for simultaneously implementing the wiring and the via contact.
그러나, 상기한 이중-상감 공정을 이용하여 배선을 형성하고자 하는 경우, 상기 트렌치(20) 및 비아콘택용 개구(22)를 형성하기 위해 제2절연막(16) 및 제1절연막(12)을 모두 건식하여야 하므로 식각시간이 길어지게 된다. 그 결과, 상기 스토퍼막(14)이 손상되어 상기 비아콘택용 개구(22)의 프로파일이 변화되는 문제점이 있다.However, when the wiring is to be formed using the above double- damascene process, both the second insulating film 16 and the first insulating film 12 are formed to form the trench 20 and the opening 22 for the via contact. Since it has to be dry, the etching time becomes long. As a result, there is a problem that the stopper film 14 is damaged and the profile of the via contact opening 22 is changed.
상기한 이중-상감 공정 이외에도 제1절연막, 스토퍼막 및 제2절연막을 차례로 형성한 뒤, 사진 및 건식식각 공정을 실시하여 비아콘택용 개구를 먼저 형성하고 나서 트렌치를 형성하는 방법이 있다. 또 다른 방법으로서, 제1절연막, 스토퍼막 및 제2절연막을 차례로 형성한 뒤, 사진 및 건식식가 공정을 실시하여 트렌치를 먼저 형성하고 나서 비아콘택용 개구를 형성하는 방법도 있다. 그러나, 상기한 이중-상감 공정에 있어서도, 상기 제1절연막 및 제2절연막과 스토퍼막의 식각선택비로 인하여 식각시간이 길어지거나 건식식각 도중에 상기 스토퍼막이 손상되어 비아콘택용 개구의 프로파일이 변화되는 문제점이 있으며, 배선의 임계치수가 줄어들 경우 오정렬(mis-align)이 발생될 가능성 또한 높아지게 된다.In addition to the double damascene process described above, the first insulating film, the stopper film, and the second insulating film are sequentially formed, followed by photolithography and dry etching to form the openings for the via contacts, and then a trench is formed. As another method, a first insulating film, a stopper film, and a second insulating film are sequentially formed, followed by photographic and dry etching processes to form trenches first, followed by openings for via contacts. However, even in the above double-inlay process, the etching time of the first insulating film, the second insulating film, and the stopper film may be increased, or the stopper film may be damaged during dry etching, thereby changing the profile of the via contact opening. In addition, if the critical dimension of the wiring is reduced, the possibility of mis-alignment is also increased.
따라서 본 발명의 목적은, 상기한 종래의 문제점을 해소할 수 있는 개선된 이중-상감 기술을 이용한 반도체 장치의 제조 방법을 제공함에 있다.It is therefore an object of the present invention to provide a method of manufacturing a semiconductor device using an improved double-inlay technique that can solve the above-mentioned conventional problems.
본 발명의 다른 목적은, 식각시간을 보다 단축시킬 수 있는 개선된 이중-상감 기술을 이용한 반도체 장치의 제조 방법을 제공함에 있다.Another object of the present invention is to provide a method of manufacturing a semiconductor device using an improved double-inlay technique that can further shorten the etching time.
본 발명의 다른 목적은, 비아콘택용 개구의 프로파일을 변화시키지 않는 개선된 이중-상감 기술을 이용한 반도체 장치의 제조 방법을 제공함에 있다.Another object of the present invention is to provide a method for manufacturing a semiconductor device using an improved double-inlay technique that does not change the profile of the opening for via contact.
본 발명의 또 다른 목적은, 오정렬을 방지할 수 있는 개선된 이중-상감 기술을 이용한 반도체 장치의 제조 방법을 제공함에 있다.It is still another object of the present invention to provide a method for manufacturing a semiconductor device using an improved double-inlay technique capable of preventing misalignment.
상기의 목적들을 달성하기 위해서 본 발명에서는, 반도체 기판 상에 증착된 제1절연막을 패터닝하여 비아콘택용 개구를 형성하는 단계와; 상기 개구가 형성되어 있는 제1절연막 상에 스텝 커버리지가 낮은 제2절연막을 이용하여 상기 개구 내부가 완전히 채워지지 않도록 증착하여 상기 개구 내부에 빈공간을 형성하는 단계와; 상기 제2절연막을 패터닝하여 배선 형성을 위한 트렌치를 형성한 뒤, 상기 트렌치 및 개구에 도전물질을 채움으로써 배선 및 비아콘택을 동시에 구현하는 단계를 포함함을 특징으로 하는 이중-상감 기술을 이용한 반도체 장치의 제조 방법을 제공한다.In order to achieve the above objects, the present invention comprises the steps of: forming an opening for via contact by patterning a first insulating film deposited on a semiconductor substrate; Forming an empty space in the opening by depositing a second insulating film having a low step coverage on the first insulating film having the opening so that the inside of the opening is not completely filled; Forming a trench for wiring formation by patterning the second insulating layer, and simultaneously forming a wiring and a via contact by filling a conductive material in the trench and the opening; Provided are methods of manufacturing the device.
도 1a 내지 도 1b는 종래 방법에 따른 이중-상감 공정 순서를 나타내는 단면도들1A-1B are cross-sectional views illustrating a double-inlay process sequence according to a conventional method.
도 2a 내지 도 2c는 본 발명의 바람직한 실시예에 따른 이중-상감 공정을 설명하기 위한 단면도들2A-2C are cross-sectional views illustrating a dual-inlay process in accordance with a preferred embodiment of the present invention.
이하, 본 발명의 바람직한 실시예를 첨부한 도면을 참조하여 상세히 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2c는 본 발명의 바람직한 실시예에 따른 이중-상감 공정을 설명하기 위한 단면도들이다.2A-2C are cross-sectional views illustrating a double-inlay process according to a preferred embodiment of the present invention.
먼저, 도 2a는 제1절연막(102)에 비아콘택용 개구(106)를 형성하는 단계를 나타낸다. 도면을 참조하면, 억세스 트랜지스터등이 형성되어 있는 반도체 기판(100) 상부에 제1절연막(102) 및 후속의 건식식각 공정시 상기 제1절연막(102)의 손상을 방지하기 위한 스토퍼막(104)을 차례로 형성한다. 그리고 나서, 사진 및 건식식각 공정을 실시하여 비아콘택용 개구(106)를 형성한다.First, FIG. 2A illustrates a step of forming the via contact opening 106 in the first insulating layer 102. Referring to the drawings, a stopper film 104 for preventing damage to the first insulating film 102 and the first insulating film 102 during a subsequent dry etching process on the semiconductor substrate 100 on which an access transistor or the like is formed. Form in turn. Then, the via contact opening 106 is formed by performing a photographic and dry etching process.
도 2b는 건식식각 시간을 보다 단축시키기 위하여, 상기 비아콘택용 개구(106)에 빈공간(110)을 형성하는 단계를 나타낸다. 도면을 참조하면, 상기 비아콘택용 개구(106)가 형성되어 있는 상기 결과물의 상부에 화학기상증착(CVD:Chemical Vapor Deposition)법으로 비교적 스텝 커버리지가 낮은 PE(Plasma Enhanced)-SiH4막 또는 HDP(High Density Plasma)-산화막등의 제2절연막(108)을 형성한다. 그 결과, 상기 비아콘택용 개구(106)내에는 상기 제2절연막(108)이 완전히 채워지지 못하여 빈공간(110)이 형성되는데, 이러한 빈공간(110)으로 인하여 후속의 건식식각 공정시 식각시간이 단축되는 효과를 얻을 수 있게 된다.2B illustrates a step of forming an empty space 110 in the via contact opening 106 to shorten the dry etching time. Referring to the drawings, a PE (Plasma Enhanced) -SiH4 film or HDP (low step coverage) having a relatively low step coverage by chemical vapor deposition (CVD) is formed on the upper part of the resultant, in which the openings for the via contact 106 are formed. A second insulating film 108, such as High Density Plasma) -oxide film, is formed. As a result, the second insulating layer 108 may not be completely filled in the via contact opening 106, so that an empty space 110 is formed. The empty space 110 may cause an etching time during a subsequent dry etching process. This shortening effect can be obtained.
계속해서, 상기 제2절연막(108)을 평탄화하기 위해, 화학기상증착법으로 제3절연막(112)을 형성한 뒤, 사진 및 건식식각 공정을 위한 마스크(114)를 형성한다.Subsequently, in order to planarize the second insulating layer 108, the third insulating layer 112 is formed by chemical vapor deposition, and then a mask 114 for photo and dry etching processes is formed.
도 2c는 이중-상감의 배선을 형성하기 위한 트렌치(116) 형성 단계를 나타낸다. 도면을 참조하면, 상기 마스크(114)를 이용하여 상기 제3절연막(112) 및 제2절연막(108)에 건식식각 공정을 실시한다. 그 결과, 상기 제3절연막(112) 및 제2절연막(108)에는 상기 마스크(114)의 패턴에 따른 배선용 트렌치(116)가 형성된다. 이때, 상기 트렌치(116) 형성을 위한 건식식각 공정시, 비아콘택용 개구(106) 내에 존재하는 빈공간(110)으로 인해 단시간 내에 건식식각 공정을 완료할 수 있어 스토퍼막(104)의 손상이 방지되며, 이로 인해 비아콘택용 개구(106)의 프로파일이 변화되지 않게 된다.2C illustrates a step of forming trench 116 to form a double-laid interconnect. Referring to the drawings, a dry etching process is performed on the third insulating layer 112 and the second insulating layer 108 using the mask 114. As a result, wiring trenches 116 in accordance with the pattern of the mask 114 are formed in the third insulating layer 112 and the second insulating layer 108. In this case, during the dry etching process for forming the trench 116, the dry etching process may be completed within a short time due to the empty space 110 present in the via contact opening 106, thereby preventing damage to the stopper film 104. This prevents the profile of the via contact opening 106 from changing.
끝으로, 상기 배선용 트렌치(116) 및 비아콘택용 개구(106)에 도전물질을 채워넣음으로써 배선과 비아콘택을 동시에 형성할 수 있게 된다.Finally, the conductive material is filled in the wiring trench 116 and the via contact opening 106 to simultaneously form the wiring and the via contact.
상기한 바와 같이 본 발명에서는 배선과 비아콘택을 동시에 형성하는 이중-상감 공정을 실시함에 있어서, 제1절연막에 비아콘택용 개구를 형성한 후에 스텝 커버리지가 낮은 제2절연막을 증착하여 상기 비아콘택용 홀에 빈공간이 형성되도록 함으로써 후속의 트렌치 형성을 위한 건식식각 공정시 식각시간이 단축되는 효과를 얻게 된다. 또한 이처럼 트렌치 형성을 위한 식각시간을 단축시킴으로서 미리 형성되어 있던 비아콘택용 개구의 프로파일이 변화되는 문제점을 해소할 수 있으며, 오정렬 문제 또한 방지할 수 있게 된다.As described above, in the present invention, in performing the double-inlay process of simultaneously forming the wiring and the via contact, after forming the via contact opening in the first insulating film, the second insulating film having the low step coverage is deposited to form the via contact. By forming an empty space in the hole, the etching time is reduced during the dry etching process for the subsequent trench formation. In addition, by shortening the etching time for the trench formation, it is possible to solve the problem of changing the profile of the via contact opening previously formed, and also to prevent the misalignment problem.
Claims (4)
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| KR1019980050280A KR20000033430A (en) | 1998-11-23 | 1998-11-23 | Method for manufacturing semiconductor device utilizing dual-damascene |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100668810B1 (en) * | 2000-08-02 | 2007-01-16 | 주식회사 하이닉스반도체 | The method of fabricating metal-line improved rc delay in semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100668810B1 (en) * | 2000-08-02 | 2007-01-16 | 주식회사 하이닉스반도체 | The method of fabricating metal-line improved rc delay in semiconductor device |
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