KR20000056055A - WAN Line Interface Apparatus - Google Patents

Abstract

PURPOSE: A device for interfacing a wide area network(WAN) line is provided to supply many WAN line interfaces with allocation of only one cell switching port, by having an additional transceiving first-in-first-out(FIFO) for many WAN lines of different transmission speed and controlling data transmission between a corresponding transceiving FIFO and one segment and reassemble(SAR) processor, so that waste of wide width is reduced and circuit configuration is simplified. CONSTITUTION: A device for interfacing a wide area network(WAN) line of an asynchronous transfer mode-local area network(ATM-LAN) switch, has a routing processor(26) connected to a cell switching port and a segment and reassemble(SAR) processor(27) mutually converting packet data and an ATM cell. The device comprises many framers(22-1/22-n) and a transmission controller(27). The many framers(22-1/22-n) mutually convert frame data and packet data, transceived between many line interfaces and the SAR processor. And, the transmission controller(27) controls transceiving of the packet data between the respective framers and the SAR processor, according to a round robin system.

Description

WAN Line Interface Apparatus

The present invention relates to a wide area network (WAN) line matching device of an Asynchronous Transfer Mode-Local Area Network (ATM-LAN) switch. In particular, only one cell switching port is allocated to a plurality of WAN lines having different transmission rates. It relates to a WAN line matching device capable of providing an interface to a network.

In general, WAN is a large communication network formed by interconnecting LANs or MAN (Metropolitan Area Networks) distributed in a wide area by using communication line services such as leased lines, packet switching networks, and general information communication networks provided by public carriers. The included ATM-LAN switch uses a WAN line matching device that provides a WAN line interface function for accommodating WAN lines. The WAN line matching device includes a line interface unit 11 as illustrated in FIG. 1. And a framer 12, a segmentation and reassemble (SAR) processor 13, and a routing processor 14.

The line interface unit 11 connects the WAN line to match the frame data input and output through the corresponding WAN line, and the framer 12 is located between the line interface unit 11 and the SAR processing unit 13 to locate the frame data and the packet. Interconvert data.

The SAR processor 13 is located between the framer 12 and the routing processor 14 to decompose packet data into ATM cells or to assemble ATM cells into packet data.

The routing processor 14 converts an ATM cell transmitted from the SAR processor 13 into an internal cell format for cell switching and transfers the cell to a cell switching port, or transfers an internal cell format transmitted through the cell switching port to an ATM cell. It converts and transfers it to the SAR processing part 13.

Referring to the operation of the conventional WAN line matching device configured as described above is as follows.

First, when the WAN line matching device of the ATM-LAN switch receives data through the WAN line, the frame data input through the WAN line and the line interface unit 11 are converted into packet data by the framer 12. It is transmitted to the SAR processing unit 13.

Accordingly, if the packet data transmitted from the SAR processing unit 13 is decomposed into ATM cells and delivered to the routing processing unit 14 through the UTOPIA interface, the corresponding routing processing unit 14 is transferred. The ATM cell is converted into an internal cell format suitable for cell switching, that is, a cell format in which control information such as internal magnetic path selection, cell type classification, and multicasting cell indication is added to the ATM cell, and transferred to the corresponding cell switching port.

Next, when the WAN line matching device of the corresponding ATM-LAN switch transmits data through the WAN line, data of an internal cell format input through the corresponding cell switching port is converted into an ATM cell by the corresponding routing processing unit 14 to be SAR. It is delivered to the processing unit 13.

Accordingly, when the ATM cell delivered by the SAR processing unit 13 is assembled into packet data and delivered to the framer 12 through the UTOPIA interface, the framer 12 converts the transmitted packet data into frame data and then lines. The interface unit 11 outputs the WAN line.

However, in the conventional ATM-LAN switch, a separate cell switching port is allocated to a WAN line matching device, which is basically a low speed (1.5 to 2 Mbps). In this case, the cell switching port uses a transmission rate of 155 Mbps. Bandwidth was wasted as cell switching was performed.

In addition, when a plurality of WAN line interfaces are to be provided, as the number of WAN line matching devices corresponding to the WAN line interfaces to be provided must be used, the number of parts is increased, and the circuit is complicated and the system price is increased.

For example, in order to provide four WAN line interfaces in an ATM-LAN switch, the line interface unit 11, the framer 12, the SAR processing unit 13, and the routing processing unit 14 are provided as shown in FIG. 1. Four WAN line matching devices should be provided and four cell switching ports should be allocated for cell switching for each WAN line matching device.

Therefore, if four 155 Mbps cell switching ports are allocated to one interface board of the corresponding ATM-LAN switch, one cell switching port must be allocated for one WAN line interface. There is a maximum of four matching devices.

As described above, conventionally, one 155 Mbps cell switching port is allocated to each WAN line matching device, which wastes bandwidth. In the case of using a plurality of WAN line matching devices, the number of parts increases and the circuit is complicated. There was a problem that the system price increases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide separate transmit / receive FIFOs for a plurality of WAN lines having different transmission rates, and between the corresponding transmit / receive FIFOs and one SAR processor. By controlling the data transmission / reception of data, only one cell switching port is allocated to provide a plurality of WAN line interfaces.

Another object of the present invention is to provide a plurality of WAN line interfaces by allocating only one cell switching port, thereby reducing bandwidth waste and simplifying circuit configuration.

1 is a block diagram of a conventional WAN line matching device.

2 is a block diagram illustrating a configuration of a WAN line matching device according to the present invention.

3 is a data reception control state transition diagram of a transmission control unit in a WAN line matching device according to the present invention;

4 is a data transmission control state transition diagram of a transmission control unit in a WAN line matching device according to the present invention.

Explanation of symbols on the main parts of the drawings

21-1 to 21-n: Line interface unit 22-1 to 22-n: Framer

23-1 to 23-n: Receive FIFO 24-1 to 24-n: Transmit FIFO

25 SAR processing unit 26 routing processing unit

27: transmission control unit

Features of the present invention for achieving the above object, routing processing means connected to the cell switching port; In a line-line matching device of an ATM-LAN switch having SAR processing means for converting packet data and ATM cells, a plurality of line interface means connected to different WAN lines and transmitted / received between the SAR processing means are provided. A plurality of framers for mutually converting frame data and packet data; And transmission control means for controlling packet data transmission / reception between the framers and the SAR processing means according to a round robin method.

On the other hand, the pigtail line matching device according to the present invention, for controlling the transmission and reception of the packet data between the framer and SAR processing means for a predetermined time by blocking or opening the input / output terminal by the control signal of the transmission control means It further comprises a plurality of transmission / reception storage means for storing the packet data.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

WAN line matching device for providing a plurality of WAN interfaces in the ATM-LAN switch according to the present invention, as shown in Figure 2, a plurality of line interface units (21-1 ~ 21-n), Framers 22-1 to 22-n, a plurality of receive FIFOs 23-1 to 23-n, a plurality of transmit FIFOs 24-1 to 24-n, a SAR processor 25, The routing processing section 26 and the transmission control section 27 are provided.

Each line interface unit 21-1 to 21-n connects a separate WAN line to match frame data input and output through the corresponding WAN line, and each framer 22-1 to 22-n is a line interface unit ( Located between 21-1 ~ 21-n) and transmit / receive FIFO (24-1 ~ 24-n, 23-1 ~ 23-n), converts frame data and packet data to each other and transmits its own status signal. It applies to the control part 27.

Each transmit / receive FIFO 24-1 to 24-n and 23-1 to 23-n block or open an input / output terminal according to a control signal of the transmission control unit 27 to store packet data for a predetermined time.

The SAR processing unit 25 is located between each transmitting / receiving FIFO 24-1 to 24-n, 23-1 to 23-n, and the routing processing unit 26 to decompose packet data into ATM cells or decompose ATM cells into packet data. The control unit receives the control signal from the transmission control unit 27, and transmits / receives the packet data and the transmission / reception FIFOs 24-1 to 24-n and 23-1 to 23-n.

The routing processor 26 converts an ATM cell transmitted from the SAR processor 25 into an internal cell format for cell switching and transmits the cell to a cell switching port, or converts an internal cell format transmitted from the cell switching port into an ATM cell and converts the SAR cell into an ATM cell. To 25.

The transmission control unit 27 receives corresponding frame signals from the framers 22-1 to 22-n and the transmission / reception FIFOs 24-1 to 24-n and 23-1 to 23-n. Generates a control signal and outputs it to the transmit / receive FIFOs (24-1 to 24-n, 23-1 to 23-n) and the SAR processing unit 25, and each transmit / receive FIFO (24-) by a round robin method. 1-24-n, 23-1 to 23-n) are adjusted, and control signals are output to the SAR processor 25 to transmit / receive FIFOs 24-1 to 24-n, 23-. 1 to 23-n) and packet data transmission / reception between one SAR processing unit 25 are controlled.

Referring to the operation of the WAN line matching device according to the present invention configured as described above are as follows.

First, when the WAN line matching device of the ATM-LAN switch receives the data through the WAN line, the frame data input through the corresponding WAN line and the line interface unit 21-1 to 21-n may correspond to a corresponding framer ( 22-1 to 22-n are converted into packet data, and then temporarily stored in each reception FIFO 23-1 to 23-n, and then adjusted by the transmission control unit 27, which is an Arbitration Programmable Logic Device (PLD) for adjustment. Received and delivered to one SAR processing unit 25.

At this time, the transmission control unit 27 receives a state signal from each framer 22-1 to 22-n, detects that there is packet data to be transmitted to the SAR processing unit 25, and receives each received FIFO 23-1 to 23. After receiving the status signal from the n-n) and detecting that the packet data can be received, the framer 22-1 to 22-n is adjusted by adjusting the control signal to each of the reception FIFOs 23-1 to 23-n. Packet data is stored in the reception FIFOs 23-1 to 23-n.

Here, the status signal includes a framer status signal input from each framer 22-1 to 22-n, and a reception FIFO status signal input from each reception FIFO 23-1 to 23-n. The signal is a signal (FD_TXE [1, 2, ..., n]) indicating whether or not packet data is transmitted from the framers 22-1 to 22-n to the reception FIFOs 23-1 to 23-n. The reception FIFO status signal is a signal for indicating its packet data storage state in the reception FIFOs 23-1 to 23-n (RFIFO_FULL [1,2, ..., n], RFIFO_EMPTY [1,2, ..., n]).

The control signal includes a signal RFIFO_WE [1, 2, ..., n] for opening or blocking an input terminal of the reception FIFOs 23-1 to 23-n, and a reception FIFO 23-1 to 23-n. The signal RFIFO_OE [1, 2, ..., n] is used to open or block the output of n).

Subsequently, the transmission control unit 27 adjusts the control signals to the respective reception FIFOs 23-1 to 23-n according to the round robin method, and the SAR processing unit 25 receives the reception FIFOs 23-1 to 23-. The control signal SAR_RXE for receiving the packet data output from n) is output to transmit the packet data stored in the corresponding reception FIFOs 23-1 to 23-n to the SAR processor 25.

Meanwhile, the data reception control operation of the transmission control unit 27 will be described in detail with reference to the state transition diagram shown in FIG. 3.

First, a framer status signal (! FD_TXE1 OR! FD_TXE2 OR! FD_TXE3 OR… OR!) Indicating that there is no packet data to transfer from the framers 22-1 to 22-n to the corresponding reception FIFOs 23-1 to 23-n. When FD_TXEn is input or when the received FIFO status signals RFIFO_EMPTY1 & RFIFO_EMPTY2 & RFIFO_EMPTY3 & ... & RFIFO_EMPTYn indicating that there is no stored packet data from the reception FIFOs 23-1 to 23-n, the corresponding transmission control section 27 Idle state is maintained.

Thereafter, a framer status signal FD_TXE1 indicating that there is packet data to be transmitted from one framer, for example, the first framer 22-1 to the corresponding first receiving FIFO 23-1, is input. When a reception FIFO status signal (! RFIFO_EMPTY1) indicating that there is stored packet data from the first reception FIFO 23-1, the transmission control unit 27 stores the packet data of the first reception FIFO 23-1. While checking, the state transitions to the first reception control state T1 for controlling the input terminal and the output terminal of the first reception FIFO 23-1. At this time, the packet data is stored in the first receiving FIFO 23-1, and at the same time, the received FIFO status signal (! RFIFO_EMPTY1 &&) indicating that the packet data transmitted from the first framer 22-1 can be continuously input. When! RFIFO_FULL1 is input, the control signals RFIFO_WE1 and RFIFO_OE1 for outputting the input terminal and the output terminal to the first receiving FIFO 23-1 are output while maintaining the corresponding first receiving control state T1.

In addition, the transmission control unit 27 outputs a control signal SAR_RXE for receiving the packet data output from the first reception FIFO 23-1 to the SAR processing unit 25, thereby outputting the first reception FIFO 23-1. ) Is transmitted to the SAR processing unit 25.

When the reception FIFO status signal RFIFO_EMPTY1 indicating that no packet data is stored from the first reception FIFO 23-1 is input, the transmission control unit 27 inputs the first reception FIFO 23-1 to the input terminal and After the control signals! RFIFO_WE1 and! RFIFO_OE1 are outputted to block the output stage, the state transitions to the idle state IDLE.

Meanwhile, in the first reception control state T1, if the first reception FIFO 23-1 cannot receive the packet data transmitted from the first framer 22-1, the reception FIFO status signal RFIFO_FULL When is input, the transmission control unit 27 outputs a control signal! RFIFO_WE1 for blocking the input terminal to the first receiving FIFO 23-1, thereby preventing loss of packet data.

The transmission control unit 27 as described above is in the idle state IDLE, and if the framer state indicates that there is packet data to be transmitted from the second framer 22-2 to the corresponding second receiving FIFO 23-2. When the signal FD_TXE2 is input, the state transition to the second reception control state T2 is performed by performing the same processing as the above-described operation, thereby performing the corresponding data reception control operation, and each other framer 22-3. 22-n), the same process is performed to transition the state to the predetermined reception control states T3 to Tn, thereby performing the corresponding data reception control operation.

Second, when the WAN line matching device of the ATM-LAN switch transmits data through the WAN line, the data of the internal cell format input through the corresponding cell switching port is converted into the ATM cell by the corresponding routing processor 26 to be SAR processing unit. The ATM cell delivered to (25) and delivered to the corresponding SAR processing unit (25) is assembled into packet data, and then temporarily stored in each transmission FIFO (24-1 to 24-n) through the UTOPIA interface, which is a PLD for adjustment. The transmission control unit 27 adjusts the transmission control unit 27 to the framers 22-1 to 22-n corresponding to the respective transmission FIFOs 24-1 to 24-n.

At this time, the transmission control unit 27 receives a status signal from each of the transmission FIFOs 24-1 to 24-n and detects that the packet data can be received, and then each transmission FIFO 24-1 to 24-n. ), And outputs a control signal SAR_TXE to transmit the packet data to the transmission FIFOs 24-1 to 24-n to the corresponding SAR processing section 25, thereby outputting the packet data of the corresponding SAR processing section 25. Is stored in each transmit FIFO 24-1 to 24-n.

Here, the status signal is a transmission FIFO status signal input from each transmission FIFO 24-1 to 24-n, and is used to indicate its packet data storage state in the transmission FIFOs 24-1 to 24-n. Signals TFIFO_FULL [1,2, ..., n], TFIFO_EMPTY [1,2, ..., n].

The control signal is a signal (TFIFO_WE [1, 2, ..., n]) for opening or blocking the input terminals of the transmission FIFOs 24-1 to 24-n.

Subsequently, the transmission control unit 27 may receive a state signal from each framer 22-1 to 22-n and receive packet data output from corresponding transmission FIFOs 24-1 to 24-n. Then, the control signal to the corresponding transmission FIFOs 24-1 to 24-n is adjusted according to the round robin method, and the packet data stored in the corresponding transmission FIFOs 24-1 to 24-n are framed. 1 ~ 22-n).

Here, the status signal is a signal FD_RXE [1, 2, ..., n indicating that the framers 22-1 to 22-n receive packet data from the transmission FIFOs 24-1 to 24-n. ], And the control signal is a signal (TFIFO_OE [1, 2, ..., n]) for opening or blocking the output terminals of the transmission FIFOs 24-1 to 24-n.

In this way, the packet data transferred to the framers 22-1 to 22-n is converted into frame data, and then, via the line interface units 21-21-n by the framers 22-1 to 22-n. It will output to the WAN line.

Meanwhile, the data transmission control operation of the transmission control unit 27 will be described in detail with reference to the state transition diagram shown in FIG. 4.

First, the framer status signal (! FD_TXE1 OR! FD_TXE2 OR! FD_TXE3 OR… OR! FD_TXEn) that indicates that the packet data transmitted from the transmission FIFOs 24-1 to 24-n cannot be received. When the transmission FIFO status signals TFIFO_EMPTY1 & TFIFO_EMPTY2 & TFIFO_EMPTY3 &… & TFIFO_EMPTYn are inputted from 1 to 22-n or indicating that there is no packet data stored from the transmission FIFOs 24-1 to 24-n. 27 maintains the idle state IDLE.

Thereafter, any one transmission FIFO, for example, a transmission FIFO status signal TFIFO_EMPTY1 indicating that there is stored packet data from the first transmission FIFO 24-1, is inputted, and the corresponding first transmission FIFO 24-1. When a framer status signal FD_RXE1 indicating that the packet data transmitted from the first frame 22-1 is received from the first framer 22-1, the transmission control unit 27 sends the packet data of the first transmission FIFO 24-1. While checking the storage state, the state transitions to the first transmission control state R1 for controlling the input terminal and the output terminal of the first transmission FIFO 24-1. At this time, the transmission FIFO status signal (! TFIFO_EMPTY1 &! TFIFO_FULL1) indicating that the packet data is stored in the first transmission FIFO 24-1, and at the same time, the packet data transmitted from the SAR processing unit 25 can be continuously input. When is input, while maintaining the first transmission control state (R1), and outputs the control signals (TFIFO_WE1, TFIFO_OE1) for opening the input terminal and the output terminal to the first transmission FIFO (24-1).

In addition, the transmission control unit 27 outputs a control signal SAR_TXE to the SAR processing unit 25 to continuously transmit the packet data to the first transmission FIFO 24-1, and is assembled by the SAR processing unit 25. The packet data is delivered to the first transmission FIFO 24-1.

When the transmission FIFO status signal TFIFO_EMPTY1 indicating that there is no stored packet data is input from the first transmission FIFO 24-1, the transmission control unit 27 inputs the input terminal and the first transmission FIFO 24-1. After outputting the control signals! TFIFO_WE1 and! TFIFO_OE1 to block the output stage, the state transitions to the idle state IDLE.

On the other hand, in the first transmission control state R1, if the transmission FIFO status signal TFIFO_FULL indicating that the first transmission FIFO 24-1 cannot receive the packet data transmitted from the SAR processing unit 25 is inputted, In this case, the transmission control unit 27 outputs a control signal! TFIFO_WE1 for blocking the input terminal to the first transmission FIFO 24-1, thereby preventing loss of packet data.

The transmission control unit 27 as described above is in the idle state IDLE, and if so, the transmission FIFO status signal indicating that there is packet data to be transmitted from the second transmission FIFO 24-2 to the corresponding framer 22-2. When (FD_RXE2) is input, the same process as described above is performed to transition the state to the second transmission control state R2, thereby performing the corresponding data transmission control operation, and performing each other transmission FIFO 24-3. The same process is performed for ˜24-n) and the state transition to the predetermined transmission control states R3 to Rn is performed, thereby performing the corresponding data transmission control operation.

Accordingly, in the present invention, a plurality of transmit / receive FIFOs (23-1 to 23-n, 24-1 to 24-n) are provided in one WAN line matching device connected to a 155 Mbps cell switching port. One WAN line matching device by controlling the transmission / reception of data input / output through each WAN line having different transmission rates using the receiving FIFOs 23-1 to 23-n and 24-1 to 24-n. Multiple WAN line interfaces can be provided, and the number of corresponding WAN line interfaces can vary depending on the capacity and transmission speed of transmit / receive FIFOs (23-1 ~ 23-n, 24-1 ~ 24-n). It becomes possible.

At this time, each transmit / receive FIFO (23-1 to 23-n, 24-1 to 24-n) has a corresponding framer (22-1 to 22-n) and a line interface unit (21-1 to 21-n). It is connected to WAN line through LAN to perform 1.5 ~ 2Mbps processing, and SAR processing unit 25 connected to corresponding transmit / receive FIFO (23-1 ~ 23-n, 24-1 ~ 24-n) processes 155Mbps As a result, a single WAN line matching device can provide smooth data processing, that is, multiple WAN line interfaces, without loss of packet data.

As described above, the present invention provides a separate transmit / receive FIFO for a plurality of WAN lines having different transmission rates, and controls data transmission / reception between the corresponding transmit / receive FIFO and one SAR processing unit. It is possible to provide multiple WAN line interfaces by allocating only cell switching ports of the device, and to provide multiple WAN line interfaces by allocating only one cell switching port, thereby reducing bandwidth waste and simplifying circuit configuration. Will be.

Claims (5)

Routing processing means connected to the cell switching port; In the pigtail line matching device of the ATM-LAN switch having a SAR processing means for converting packet data and ATM cells, A plurality of framers for mutually converting frame data and packet data transmitted / received between the plurality of line interface means connected to different WAN lines and the SAR processing means; And a transmission control means for controlling packet data transmission / reception between the framers and the SAR processing means according to a round robin method. The method of claim 1, A plurality of transmission / reception stores for storing the packet data for a predetermined time by blocking or opening an input / output terminal by a control signal of the transmission control means to control packet data transmission / reception between each framer and SAR processing means. Wen line matching device further comprising a means. The method of claim 2, The transmission control unit receives a status signal from each framer and a transmission / reception storage unit, adjusts input / output terminal blocking and opening control signals outputted to the transmission / reception storage means by a round robin method, and executes the SAR process. And a transmission / reception control signal to a means to control packet data transmission / reception between the plurality of transmission / reception storage means and one SAR processing means. The method of claim 3, The transmission control means opens an input terminal and an output terminal of the reception storage means when a framer status signal indicating that there is packet data to be transmitted to the reception storage means is input and a reception storage means status signal indicating that there is stored packet data is input. And simultaneously control the SAR processing means in a reception state, and transmit packet data transmitted from each framer through a corresponding reception storage means to the SAR processing means. The method of claim 3, The transmission control means controls the SAR processing means to a transmission state when a transmission storage means status signal indicating that there is stored packet data is input and a framer status signal indicating that the transmitted packet data can be received. And simultaneously open the input and output ends of the transmission storage means and transfer the packet data transmitted from the SAR processing means to the corresponding framers to the corresponding framers.