KR20030019835A - Apparatus for ATM switching using cellbus - Google Patents

Abstract

PURPOSE: An ATM switching device using a cell bus is provided to implement ATM switches in one plug-in card, and to use an ATM system as a 25.6Mbit/s ATM serial switch and an ATM 155Mbit/s serial concentrator, thereby supplying a small ATM switching function more stably. CONSTITUTION: Many interfaces(11-1¯11-24) interface with ATM cells. 4 MUXs/DEMUXs(12¯15) perform multiplexing and demultiplexing processes of the ATM cells. The first to the fourth ATM switch(20-23) perform interface functions with input/output cell data and cell bus mediation processes, and perform interface functions with external SRAMs. 4 external SRAMs(30¯33) store data for address conversion of the ATM cells. A cell bus(70) supplies a transmission path of cell data. A control bus(80) transmits a control command. A system processor(61) controls the ATM switches(20¯23). A master ATM switch(40) controls cell bus mediation between the ATM switches(20-23). A cell buffer(63) temporarily stores transmission data. A stream controller(62) controls stream of the cell data.

Description

ATM switching device using cellbus {Apparatus for ATM switching using cellbus}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ATM (Asynchronus Transfer Mode) switching device, and more particularly, to implement a small-capacity ATM switch using Cellbus in one Plug-in card and an ATM method. The present invention relates to an ATM switching device using Cellbus, which can be used as a 25.6Mbit / s ATM serial switch and an ATM 155Mbit / s serial concentrator in all systems using a backbone.

In general, ATM (Asynchronus Transfer Mode) refers to a technology for processing data communication using voice communication, that is, a switching technology used in a common telephone network. ATM uses a virtual channel circuit switching scheme and transmits and receives a cell of fixed length in units of 53 bytes.

In particular, ATM is a communication technology developed as a base technology of B-ISDN (Broadband ISDN) for the next generation network. It uses the same cell in LAN / WAN, and has developed in voice communication technology. It has the advantage of full support.

In ATM, a logical cable called a virtual channel is connected in a physically connected connection section and then data is transmitted through the call. In other words, it is a logical cable rather than a channel concept.

Among these virtual channels, the virtual destinations of the same destination are gathered together and switched into a virtual path. This function is mainly used to switch a large virtual channel in a public ATM switch (a large ATM switch operated by a network operator). If necessary, it is used as a function for switching efficiently.

In other words, the concept of the identifier "VPI / VCI", the addressing scheme used in ATM, is the same as the telephone number / user number of a general telephone number. ATM is the only technology that can transmit voice, video, or data over a single WAN link, and products such as WAN are already available for this purpose, such as Com's PathBuilder 500 family.

In the ATM data transmission system, data is transmitted in a cell of fixed length of 53 bytes. The 53-byte cell is divided into a 5-byte header and a 48-byte data area. In ATM, the destination address is expressed through a VPI / VCI value.

However, the cell switching used in the ATM method has a problem in that its performance is limited by routing 25 Mbps cell data coming from various paths in a UTOPIA matching section.

In addition, the ATM cell switching according to the prior art has an external first in first out (FIFO) that performs a queuing function for the input and output cell data to be controlled by the processor, so the performance and reliability of ATM cell switching There was a problem of this deterioration.

Accordingly, the present invention has been made to solve the above-described problems according to the prior art, an object of the present invention, 25.6Mbit / s ATM serial switch and ATM 155Mbit / s in all systems using the ATM method as a backbone (Backbone) It is to provide an ATM switching device using Cellbus that can be used as a serial concentrator.

A characteristic of the ATM switching device using the cell bus according to the present invention for achieving the above object, in the switching device of the asynchronous transmission mode (ATM) of the base station having a plurality of matching units, connected to the matching unit of the base station An interface unit performing a matching function of a 25 Mbit / s speed ATM cell and a physical layer to be inputted, a mux / demux connected to the interface unit to perform a multiplexing and demultiplexing function of an ATM cell, and the mux / demux A first to fourth ATM switch performing a matching function of input / output cell data and cell bus arbitration and a matching function with an external SRAM for address translation of an ATM cell between a cell bus and a cell bus; Cell connected to a switch to transfer cell data input from one line to another line, and a cell for concentrating cell data input from a plurality of lines The cell bus providing a data transmission path, a control bus connected to the ATM switch to transmit a control command of the ATM switch, a system processor connected to the control bus to control the ATM switch, the cell bus and Master connected to control bus and performing matching function with 155 Mbit / s physical layer interface chip through Utopia interface when cell data is concentrated, and controlling cell bus arbitration between first to fourth ATM switches connected to cell bus An ATM switch, a cell buffer for temporarily storing transmission data when transmitting data from the master ATM switch to the 155 Mbit / s physical layer interface chip, and flow of cell data in association with the mux / demux and cell buffer It is configured to include a flow control unit for controlling.

1 is a block diagram of an ATM switching device using a cell bus according to the present invention;

2 is a view showing the configuration of the cell bus of FIG.

3 is a block diagram showing another embodiment of an ATM switching device using a cell bus according to the present invention.

<Description of the symbols for the main parts of the drawings>

11-1 ~ 11-24: Interface

12 ~ 15: mux / demux

20 ~ 23: ATM switch

70: Selbus

Hereinafter, with reference to the accompanying drawings a preferred embodiment of the ATM switching device using a cell bus according to the present invention will be described.

1 is a block diagram of an ATM switching device using a cell bus according to the present invention.

As shown in FIG. 1, a plurality of interface units 11-1 to 11-24 connected to a matching unit of a base station and performing a matching function of an ATM cell of 25 Mbit / s speed and a physical layer, and the interface Four mux / demuxes 12 to 15 connected to each other and performing multiplexing and demultiplexing functions of ATM cells, and matching functions of input / output cell data between the mux / demuxes 12 to 15 and cell buses. First to fourth ATM switches 20 to 23 for performing cell bus arbitration and matching with an external SRAM for address translation of an ATM cell, and four for storing data for address translation of the ATM cell. An external SRAM 30 to 33, a cell bus 70 connected to the first to fourth ATM switches 20 to 23 to provide a cell data transmission path, and the plurality of ATM switches 20 to 23. A control bus 80 connected to the control bus 80 to transmit control commands, and the ATM switch connected to the control bus 80; A system processor 61 controlling 20 to 23 and a cell bus 70 and a control bus 80 to perform a matching function with a 155 Mbit / s physical layer interface chip and to be connected to the cell bus. The master ATM switch 40 for controlling cell bus arbitration between the first to fourth ATM switches 20 to 23 and the master ATM switch 40 and the cell ATM 64 when transmitting the cell data from the master ATM switch 40 to the physical layer unit 64 of 155 Mbit / s. The cell buffer 63 temporarily stores data, and the flow control unit 62 controls the flow of cell data in association with the mux / demux 12 to 15 and the cell buffer 70.

Six interface units are connected to the mux / demux 12 to 15 so that the cell data through the six interface units is connected to one mux / demux and processed when the cell data is concentrated.

Referring to the operation of the ATM switching device using the cell bus configured as described above are as follows.

As shown in FIG. 1, six line interface units 11-1 to 11-6 having a speed of 25.6 Mbit / s are configured and matched to one mux / demux 12. It is connected to the first ATM switch 20 and is matched to a line of 155.52Mit / s.

At this time, the mux / demux 12 that matches the six lines of 25 Mbit / s performs a queuing and multiplexing function for the ATM cell.

In this way, four groups consist of 25.6 Mbit / s lines.

That is, ATM cell data in 24 24 lines of 25.6 Mbit / s is transferred to one line of 155.52 Mbit / s through the four mux / demux (12 ~ 15) and four ATM switches (20 ~ 23) Matches.

The system processor 61 then performs a control function of the present switching device. The system processor 61 adds one more ATM switch on the cell bus 70 (hereinafter, referred to as a master ATM switch 40), and then a utopia (between the system processor 61 and the master ATM switch 40). UTOPIA) controls ATM cell data through matching.

In addition, since the cell bus 70 needs to have a total data processing rate of 150 Mbit / s, the cell bus can operate at a clock of up to 42 MHz.

The switching function in the above configuration performs matching between 25 Mbit / s lines of the interface units 11-1 to 11-24, and the cell data concentrating function is one line in the 25 25 Mbit / s lines. Matching between 155Mbit / s interface lines.

That is, when performing the switching function in the switching device, the ATM cell input through one interface unit, that is, one 25 Mbit / s line, is multiplexed and transmitted to the cell bus via the corresponding mux / demux and the ATM switch, and again. It is demultiplexed to 25Mbit / s through other ATM switch and Tapmux / Demux and interface unit in Cellbus to switch to another 25Mbit / s line.

In addition, the concentration function in the switching device is that the ATM cells inputted through a plurality of 25Mbit / ss lines are multiplexed on the cell bus through the mux / demux connected to each interface unit and the corresponding ATM switch, and again the master ATM. It is transmitted to the physical layer unit 64 of 155 Mbit / s via a switch. The reverse path can also be used for demultiplexing.

When performing the switching and centralization functions, VPI / VCI conversion is performed in connection with an external SRAM that is connected to each ATM switch and stores data for address conversion of an ATM cell. In this case, VPI / VCI is an addressing method used in ATM, and its system is identical to that of a general telephone number.

FIG. 2 is a diagram illustrating a configuration of the cell bus of FIG. 1.

As illustrated in FIG. 2, the first to fourth ATM switches 20 to 23 perform cell matching and cell bus arbitration, and a matching function with an external SRAM for address translation of an ATM cell.

The master ATM switch 40 transmits a CBF (CellBus Frame) for cell bus synchronization to another ATM node, and controls cell bus arbitration between ATM switches.

Cellbus occupancy between the ATM switches is that each ATM switch has its own cellbus occupancy address and requests the master ATM switch 40 to occupy cellbus, and the master ATM switch 40 requests cellbus occupancy. Allows occupancy in the order of Cellbus occupancy requests of ATM switches.

Here, there are 37 signal lines constituting the cell bus, and there are two clock signals which are 32-bit data buses for ATM cell transmission and control signals for synchronizing transmission / reception data and control signals to clocks. The two clock signals are CBWC (CellBus Write Clock) and CBRC (CellBus Read Clock).

There is a CBF (CellBus Frame) signal, which is a frame synchronization signal for synchronizing the ATM switch matched with the cell bus, an Ack (Acknowledgement) signal indicating that ATM cell reception is normally performed, and ATM cell reception is abnormal. There is a Cong (Congestion) signal that indicates the loss.

Here, the CBF signal is a signal supplied to another ATM switch, and the Ack and Cong signals are signals that can be transmitted and received by all ATM switches matched to the cell bus.

In addition, each of the four ATM switches includes four external SRAMs 30-33 for address translation of an ATM cell.

In particular, one of the plurality of ATM switches 20, 21, 22, 23 becomes a mast of the cell bus and controls the bus.

3 is a block diagram showing another embodiment of an ATM switching device using a cell bus according to the present invention.

As shown in FIG. 3, twelve interface units 70-1 to 70-12 perform a matching function between an ATM cell of a 25 Mbit / s line and a physical layer, and multiplexing an ATM cell connected to the interface unit. Two mux / demux 80-81 performing demultiplexing function, and matching and input / output cell data between the mux / demux 80-81 and cellbus 88 and cellbus arbitration. A control processor 84 for controlling the operation of the first ATM switch 83 and the second ATM switch 85, the first ATM switch and the second ATM switch, and the first ATM switch 83 and the second ATM switch. A cell bus 88 connected to an ATM switch 85 for transmitting cell data input from one line to another line and providing a transmission path of cell data for concentrating cell data input from a plurality of lines; And a control command connected to the first ATM switch 83 and the second ATM switch 85. A control bus 89 to transmit, a control bus interface unit 87 connected to the control bus 89 to perform a control bus matching function with the control processor, and a signal bus connected to the cell bus 88 And a clock receiving / distributing unit 86 for receiving and distributing a clock for the alarm and an alarm manager 82 connected to the first ATM switch to detect an abnormal operation of the switching board.

The six line interface units 70-1 to 70-6 having a speed of 25.6 Mbit / s are matched to one mux / demux 80, which is connected to the first ATM switch 83 to be connected to the cell. Matches to the bus line.

At this time, the mux / demux 80 matching 6 lines of 25 Mbit / s performs a queuing and multiplexing function for the ATM cell.

In this way, two groups are composed of 25.6 Mbit / s lines, and ATM cell data simultaneously inputted in a total of 12 25.6 Mbit / s lines are the two mux / demuxes (80 to 81) and two It can be matched to the cell bus line through the ATM switches 83 and 85.

The switching function in the above configuration performs matching between 25 Mbit / s lines of the interfaces 70-1 to 70-12.

That is, when performing the switching function in the switching device, the ATM cell input through one interface unit, that is, one 25 Mbit / s line, is multiplexed and transmitted to the cell bus through the interface with the corresponding mux / demux, and then the cell. It is demultiplexed to 25 Mbit / s through other ATM switches and other mux / demux and interface units on the bus to switch to another 25 Mbit / s line.

3 may be used for switching ATM cells in an IS-2000 base station system. The cell bus 88 may be used as a main path in routing ATM cells in a switching board in which the apparatus of FIG. 3 is implemented, and the first ATM switch 83 and the second ATM switch 85 may be used as the cell. Direct matching to the bus 88 performs the ATM switching function.

As described above, the present invention has a transmission speed of up to 155 Mbps, and has an effect of more stably providing a small ATM switching function. Also, when implementing a large ATM switching device, a related chip such as an additional ATM switch may be mounted. By matching with cellbus, there is an effect that can be easily implemented.

Claims (3)

In the switching device of the asynchronous transmission mode (ATM) of the base station having a plurality of matching units, An interface unit connected to a matching unit of the base station and performing a matching function of a 25 Mbit / s speed ATM cell and a physical layer; A mux / demux connected to the interface unit to perform a multiplexing and demultiplexing function of an ATM cell; First to fourth ATM switches performing a matching function of I / O cell data and cell bus arbitration between the mux / demux and cell bus, and a matching function with an external SRAM for address conversion of an ATM cell; The cell connected to the first to fourth ATM switches to transmit cell data input from one line to another line, and provide a transmission path of cell data for concentrating cell data input from a plurality of lines; With a bus; A control bus connected to the ATM switch and transmitting a control command of the ATM switch; A system processor coupled to the control bus to control the ATM switch; Cellbus arbitration between the first and fourth ATM switches connected to the cellbus by performing a matching function with a 155 Mbit / s physical layer interface chip through a utopia interface when connected to the cellbus and the control bus through a utopia interface. Master ATM switch for controlling the; A cell buffer that temporarily stores transmission data when the cell data is transmitted from the master ATM switch to the 155 Mbit / s physical layer interface chip; ATM switching device using a cell bus comprising a flow control unit for controlling the flow of cell data in conjunction with the mux / demux and the cell buffer. The cell according to claim 1, wherein the interface unit performing the matching function of the 25 Mbps ATM cell and the physical layer includes a total of 24 interface units in a manner of connecting six interface units to one mux / demux. ATM switching device using bus. In the switching device of the asynchronous transmission mode (ATM), Twelve interface units for performing a matching function between an ATM cell and a physical layer of a 25 Mbit / s line; Two mux / demuxes connected to the twelve interface units to perform multiplexing and demultiplexing functions of ATM cells; A first ATM switch and a second ATM switch configured to perform input / output cell matching and cell bus arbitration between the two mux / demux and cell bus; A control processor for controlling the operation of the first ATM switch and the second ATM switch; It is connected to the first ATM switch and the second ATM switch to transmit cell data input from one line to another line, and provides a transmission path of cell data for concentrating the cell data input from a plurality of lines Celbus; And a control bus connected to the first ATM switch and the second ATM switch to transmit a control command.