KR20000043886A - Muti bit flash memory cell, manufacturing and driving method thereof - Google Patents
Muti bit flash memory cell, manufacturing and driving method thereof Download PDFInfo
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- KR20000043886A KR20000043886A KR1019980060324A KR19980060324A KR20000043886A KR 20000043886 A KR20000043886 A KR 20000043886A KR 1019980060324 A KR1019980060324 A KR 1019980060324A KR 19980060324 A KR19980060324 A KR 19980060324A KR 20000043886 A KR20000043886 A KR 20000043886A
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- 238000000034 method Methods 0.000 title claims description 13
- 238000004519 manufacturing process Methods 0.000 title description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 30
- 229920005591 polysilicon Polymers 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 239000004065 semiconductor Substances 0.000 claims abstract description 21
- 125000006850 spacer group Chemical group 0.000 claims abstract description 11
- 230000005641 tunneling Effects 0.000 claims description 8
- 238000002347 injection Methods 0.000 claims description 4
- 239000007924 injection Substances 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 claims description 3
- 230000010354 integration Effects 0.000 description 4
- 239000000969 carrier Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
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Abstract
Description
본 발명은 멀티 비트 플래쉬 메모리 셀(multi bit flash memory cell), 그 제조 방법 및 구동 방법에 관한 것으로, 특히 2개의 플로팅 게이트의 문턱 전압을 이용하여 서로 다른 포화 전류값을 가지는 멀티 비트 플래쉬 메모리 셀, 제조 방법 및 그 구동 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi bit flash memory cell, a manufacturing method and a driving method thereof. In particular, a multi bit flash memory cell having different saturation current values using threshold voltages of two floating gates, A manufacturing method and its driving method are provided.
현재 플래쉬 메모리 소자의 대중화를 가로막고 있는 가장 큰 문제점은 단위 정보량당 비용이 크다는 것이다. 이와 같은 문제를 해결하기 위해서는 셀의 고집적화가 필수적이며 이를 위해 많은 연구가 진행중이다. 그러나 플래쉬 메모리 소자는 그 구조가 DRAM에 비해 상대적으로 복잡하므로 고집적화에 많은 어려움이 따르게 된다.The biggest problem currently preventing the popularization of flash memory devices is the high cost per unit information amount. In order to solve such a problem, high integration of cells is essential, and many studies are in progress. However, since the structure of the flash memory device is relatively complicated compared to DRAM, it is difficult to achieve high integration.
따라서, 본 발명은 간단한 구조를 가지면서도 적은 수의 셀로도 다수의 서로 다른 상태를 얻을 수 있는 멀티 비트 플래쉬 메모리 셀, 그 제조 방법 및 구동 방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a multi-bit flash memory cell having a simple structure and obtaining a plurality of different states even with a small number of cells, a manufacturing method and a driving method thereof.
상술한 목적을 달성하기 위한 본 발명에 따른 멀티 비트 플래쉬 메모리 셀은 반도체 기판과, 상기 반도체 기판 상부의 선택된 영역에 형성되며, 제 1 터널 산화막에 의해 상기 반도체 기판과 절연되도록 형성된 제 1 플로팅 게이트와, 상기 반도체 기판 상부의 선택된 영역에 형성되며, 제 2 터널 산화막에 의해 상기 반도체 기판과 절연되며, 스페이서에 의해 상기 제 1 플로팅 게이트와 절연되도록 형성된 제 2 플로팅 게이트와, 상기 제 1 및 제 2 플로팅 게이트 상부에 형성되며, 유전체막에 의해 상기 제 1 및 제 2 플로팅 게이트와 절연되도록 형성된 콘트롤 게이트와, 상기 제 1 및 제 2 플로팅 게이트의 양측 종단에 의해 자기정렬적으로 형성된 소오스 및 드레인을 포함하여 이루어진 것을 특징으로 한다.According to an aspect of the present invention, there is provided a multi-bit flash memory cell including a semiconductor substrate, a first floating gate formed in a selected region over the semiconductor substrate, and insulated from the semiconductor substrate by a first tunnel oxide layer; A second floating gate formed in a selected region over the semiconductor substrate, insulated from the semiconductor substrate by a second tunnel oxide film, and insulated from the first floating gate by a spacer, and the first and second floating gates; A control gate formed on the gate and insulated from the first and second floating gates by a dielectric film, and a source and a drain formed self-aligned by both ends of the first and second floating gates; Characterized in that made.
또한, 상술한 목적을 달성하기 위한 본 발명에 따른 멀티 비트 플래쉬 메모리 셀의 제조 방법은 반도체 기판 상부에 제 1 터널 산화막 및 제 1 폴리실리콘막을 형성한 후 패터닝하여 제 1 플로팅 게이트를 형성하는 단계와, 상기 패터닝된 제 1 폴리실리콘막의 측벽에 스페이서를 형성하는 단계와, 전체 구조 상부에 제 2 터널 산화막 및 제 2 폴리실리콘막을 형성한 후 패터닝하여 제 2 플로팅 게이트를 형성하는 단계와, 전체 구조 상부에 유전체막 및 제 3 폴리실리콘막을 순차적으로 형성한 후 패터닝하여 콘트롤 게이트를 형성하는 단계와, 상기 콘트롤 게이트를 마스크로 자기 정렬적인 이온 주입 공정에 의해 소오스 및 드레인을 형성하는 단계를 포함하여 이루어진 것을 특징으로 한다.In addition, the method of manufacturing a multi-bit flash memory cell according to the present invention for achieving the above object is formed by forming a first tunnel oxide film and a first polysilicon film on the semiconductor substrate and patterned to form a first floating gate; Forming a spacer on sidewalls of the patterned first polysilicon layer, forming a second tunnel oxide layer and a second polysilicon layer on the entire structure, and then patterning the second floating gate to form a second floating gate; And forming a control gate by sequentially forming a dielectric film and a third polysilicon film on the substrate, and forming a source and a drain by a self-aligned ion implantation process using the control gate as a mask. It features.
한편, 상술한 목적을 달성하기 위한 본 발명에 따른 멀티 비트 플래쉬 메모리 셀의 구동 방법은 본 발명에 따른 플래쉬 메모리 셀에서 상기 플로팅 게이트의 종단에 의해 자기정렬적으로 형성된 드레인 사이의 전압차에 의한 F-N 터널링을 이용하여 각각의 제 1 플로팅 게이트, 제 2 플로팅 게이트 또는 제 1 플로팅 게이트와 제 2 플로팅 게이트 모두 프로그램할 수 있으며, 이의 결과 제 1 또는 제 2 플로팅 게이트의 서로 다른 전위를 이용한 핫 캐리어 인젝션에 의해 제 2 또는 제 1 플로팅 게이트의 문턱 전압을 다양하게 구현하여 2가지 이상의 상태를 저장할 수 있는 것을 특징으로 한다.On the other hand, the driving method of the multi-bit flash memory cell according to the present invention for achieving the above object is the FN due to the voltage difference between the drain formed self-aligned by the termination of the floating gate in the flash memory cell according to the present invention Tunneling can be used to program each of the first floating gate, the second floating gate, or both the first and second floating gates, resulting in hot carrier injection using different potentials of the first or second floating gate. As a result, various threshold voltages of the second or first floating gate may be implemented to store two or more states.
도 1(a) 내지 도 1(d)는 본 발명에 따른 멀티 비트 플래쉬 메모리 셀의 제조 방법을 설명하기 위한 단면도.1 (a) to 1 (d) are cross-sectional views illustrating a method of manufacturing a multi-bit flash memory cell according to the present invention.
<도면의 주요 부분에 대한 부호 설명><Description of the symbols for the main parts of the drawings>
11 : 반도체 기판 12 : 제 1 터널 산화막11 semiconductor substrate 12 first tunnel oxide film
13 : 제 1 폴리실리콘막 14 : 스페이서13 first polysilicon film 14 spacer
15 : 제 2 터널 산화막 16 : 제 2 폴리실리콘막15 second tunnel oxide film 16 second polysilicon film
17 : 유전체막 18 : 제 3 폴리실리콘막17 dielectric film 18 third polysilicon film
19 : 소오스 20 : 드레인19: source 20: drain
본 발명에서는 5가지 상태가 가능한 셀로써 실제적으로는 집적도를 크게 향상시키는 효과를 얻고자 한다. 예를 들면 16가지의 서로 다른 상태를 얻기 위해 종래에는 4개의 셀이 필요하지만, 본 발명으로는 2개의 셀로서 25가지의 서로 다른 상태를 얻을 수 있다.In the present invention, as a cell capable of five states, the present invention seeks to obtain an effect of greatly improving the degree of integration. For example, four cells are conventionally required to obtain 16 different states, but in the present invention, 25 different states can be obtained as two cells.
본 발명에 적용되는 기술적 원리는 다음과 같다.The technical principle applied to the present invention is as follows.
트랜지스터의 포화 전류는 그 문턱 전압에 따라 변화한다. 따라서 문턱 전압을 변화시킬 수 있으면 서로 다른 포화 전류를 얻을 수 있고 이를 서로 다른 상태로 이용할 수 있다.The saturation current of the transistor changes with its threshold voltage. Therefore, if the threshold voltage can be changed, different saturation currents can be obtained and used in different states.
본 발명에서는 채널 상부에 서로 다른 문턱 전압을 가지는 두 개의 플로팅 게이트와 그 상부에 콘트롤 게이트를 형성하여, 두 플로팅 게이트의 프로그램 및 소거 정도와 콘트롤 게이트의 바이어스 조합으로 서로 다른 포화 전류를 얻는다.In the present invention, two floating gates having different threshold voltages on the upper channel and a control gate are formed on the upper side of the channel to obtain different saturation currents by a combination of program and erase levels of the two floating gates and a bias of the control gate.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 1(a) 내지 도 1(d)는 본 발명에 따른 멀티 비트 플래쉬 메모리 셀의 제조 방법을 설명하기 위한 단면도이다.1A to 1D are cross-sectional views illustrating a method of manufacturing a multi-bit flash memory cell according to the present invention.
도 1(a)를 참조하면, 반도체 기판(11) 상부에 제 1 터널 산화막(12)을 형성한 후 제 1 폴리실리콘막(13)을 형성한다. 제 1 폴리실리콘막(13) 및 제 1 터널 산화막(12)을 형성하고자 하는 제 1 플로팅 게이트의 폭으로 식각한다. 전체 구조 상부에 절연막을 형성한 후 스페이서 식각을 실시하여 제 1 폴리실리콘막(13)측벽에 스페이서(14)를 형성한다.Referring to FIG. 1A, after forming the first tunnel oxide film 12 on the semiconductor substrate 11, the first polysilicon film 13 is formed. The first polysilicon layer 13 and the first tunnel oxide layer 12 are etched with the width of the first floating gate to be formed. After forming an insulating film over the entire structure, spacer etching is performed to form the spacer 14 on the side wall of the first polysilicon film 13.
도 1(b)를 참조하면, 전체 구조 상부에 제 2 터널 산화막(15)을 형성한 후 제 2 폴리실리콘막(16)을 형성한다. 이 공정에 의해 제 2 터널 산화막(15)은 제 1 폴리실리콘막(13) 및 반도체 기판(11) 상부에 형성된다. 제 2 폴리실리콘막(16)을 형성하고자 하는 제 2 플로팅 게이트의 폭으로 식각한다. 이때, 제 2 폴리실리콘막(16)은 스페이서(14)를 통해 제 1 폴리실리콘막(13) 상부에 소정의 폭으로 오버랩된다.Referring to FIG. 1B, the second tunnel oxide layer 15 is formed on the entire structure, and then the second polysilicon layer 16 is formed. By this process, the second tunnel oxide film 15 is formed over the first polysilicon film 13 and the semiconductor substrate 11. The second polysilicon layer 16 is etched with the width of the second floating gate to be formed. In this case, the second polysilicon film 16 overlaps the upper portion of the first polysilicon film 13 by a predetermined width through the spacer 14.
도 1(c)를 참조하면, 전체 구조 상부에 유전체막(17)을 형성한 후 제 3 폴리실리콘막(18)을 형성한다. 제 3 폴리실리콘막(18), 유전체막(17), 제 2 폴리실리콘막(16) 및 터널 산화막을 패터닝하여 콘트롤 게이트, 제 1 및 제 2 플로팅 게이트가 적층된 스택 게이트 구조를 형성한다.Referring to FIG. 1C, after forming the dielectric film 17 over the entire structure, the third polysilicon film 18 is formed. The third polysilicon film 18, the dielectric film 17, the second polysilicon film 16, and the tunnel oxide film are patterned to form a stack gate structure in which the control gate, the first and the second floating gate are stacked.
도 1(d)는 형성된 콘트롤 게이트 및 플로팅 게이트를 마스크로 셀 소오스/드레인 이온 주입 공정을 자기정렬 방식으로 실시하여 소오스(19) 및 드레인(20)을 형성한다.FIG. 1D illustrates a cell source / drain ion implantation process using a formed control gate and a floating gate as a mask to form a source 19 and a drain 20.
상기와 같은 방법으로 제조되는 멀티 비트 플래쉬 메모리 셀의 구동 방법을 설명하면 다음과 같다.A driving method of a multi-bit flash memory cell manufactured by the above method will be described below.
1. 프로그램 및 소거1. Program and erase
프로그램시에는 F-N 터널링과 핫 캐리어 인젝션을 조합하여 실행한다. 즉 트레인쪽 플로팅 게이트의 프로그램 또는 소거 여부에 따라 제 1 플로팅 게이트(소오스쪽 플로팅 게이트)에 주입되는 핫 캐리어의 양이 달라지므로 서로 다른 문턱 전압을 가지게 된다.The programming is performed by combining F-N tunneling and hot carrier injection. That is, since the amount of hot carriers injected into the first floating gate (source floating gate) varies according to whether the train-side floating gate is programmed or erased, the gate floating gate has different threshold voltages.
일괄 소거시에는 기판을 플로팅시킨 상태에서 콘트롤 게이트에 -12V 정도의 고전압을 인가하고, 원하는 플로팅 게이트쪽의 비트라인에 5V 정도를 인가하여 F-N 터널링을 이용하여 소거한다.In the case of batch erasing, a high voltage of about -12V is applied to the control gate while the substrate is floated, and about 5V is applied to the bit line toward the desired floating gate to be erased using F-N tunneling.
2. 독출2. Reading
예를들어 위의 [표 1]에 나타낸 것와 같이 소거시와 프로그램시의 문턱 전압을 각각 -1V, 1V, 3V, 5V, 7V라 하면 콘트롤 게이트에 0V, 2V, 4V, 6V의 전압을 차례로 인가하고 소오스에 0V, 드레인에 5V 정도를 인가하여 데이터를 판별한다.For example, as shown in [Table 1], if the threshold voltages at erasing and programming are -1V, 1V, 3V, 5V, and 7V, respectively, the voltages of 0V, 2V, 4V, and 6V are sequentially applied to the control gate. Then 0V is applied to the source and 5V is applied to the drain to discriminate the data.
상술한 바와 같이 본 발명에 의하면 채널 상부에 서로 다른 문턱 전압을 가지는 두 개의 플로팅 게이트와 그 상부에 콘트롤 게이트를 형성하여, 두 플로팅 게이트의 프로그램 및 소거 정도와 콘트롤 게이트의 바이어스 조합으로 서로 다른 포화 전류를 얻고, 이를 통해 적은 수의 셀로도 많은 서로 다른 상태를 얻을 수 있어 집적도를 향상시킬 수 있다.As described above, according to the present invention, two floating gates having different threshold voltages and upper control gates are formed on the channel, and different saturation currents are formed by a combination of program and erase levels of the two floating gates and a bias of the control gate. In this way, many different states can be obtained with a small number of cells, thereby improving the degree of integration.
Claims (5)
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| JPH09172095A (en) * | 1995-12-18 | 1997-06-30 | Nec Corp | Nonvolatile semiconductor storage device and its manufacturing method and use method |
| KR0142604B1 (en) * | 1995-03-22 | 1998-07-01 | 김주용 | Flash Y pyrom cell and manufacturing method thereof |
| KR19980055724A (en) * | 1996-12-28 | 1998-09-25 | 김영환 | Flash Y pyrom cell and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR0142604B1 (en) * | 1995-03-22 | 1998-07-01 | 김주용 | Flash Y pyrom cell and manufacturing method thereof |
| JPH09172095A (en) * | 1995-12-18 | 1997-06-30 | Nec Corp | Nonvolatile semiconductor storage device and its manufacturing method and use method |
| KR19980055724A (en) * | 1996-12-28 | 1998-09-25 | 김영환 | Flash Y pyrom cell and manufacturing method thereof |
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