KR20000031509A - Method for fabricating thin film type optical path controller - Google Patents

Abstract

PURPOSE: A method for producing a thin film typed optical path controller is provided to prevent a defect of a second sacrifice layer, to reduce a producing time and to improve a producing yield rate by forming the second sacrifice layer using a thick photoresist. CONSTITUTION: In a thin film typed optical path controller, a first signal transferred from the outside is fed to a lower electrode(180) through a MOS transistor(120) embedded in an active matrix(100), a drain pad and a via contact(280) of a first metal layer(120) and a second signal is fed through a common electrode line(240) from the outside in a first and a second upper electrodes(200,201). Therefore, a first electric field is generated according to a potential difference between the first upper electrode(200) and one side of the lower electrode(180) and a second electric field is generated according to the potential difference between the second upper electrode and the other side of the lower electrode(180). An actuator(210) contained a first and a second transforming layers(190) is bent at a certain angle according to shrinkage of the first and the second transforming layers(190) to a direction crossed for the first and the second electric fields. A mirror(260) to reflect light projected from a source of light is inclined with the actuator because the mirror is formed in a upper part of the actuator(210) by supporting with a post(250). Therefore the mirror(260) reflects the projected light at the certain angle and the reflected light makes a picture on a screen by passing a slit.

Description

Manufacturing method of thin film type optical path control device

The present invention relates to a method for manufacturing a thin film type optical path control apparatus using thin-film micromirror array-actuated (TMA), and more particularly, to prevent defects of the second sacrificial layer and to improve the yield of the process. It relates to a method for manufacturing a thin film type optical path control device.

Optical path control devices or spatial light modulators for projecting optical energy onto a screen may be applied to various fields such as optical communication, image processing, and information display devices. Typically, image processing apparatuses using such optical modulators are classified into a direct-view image display device and a projection-type image display device according to a method of displaying optical energy on a screen. do.

An example of a direct view type image display device is a CRT (Cathode Ray Tube), which is called a CRT device, which has excellent image quality but increases its weight and volume as the size of the screen increases, leading to an increase in manufacturing cost. there is a problem. Projection type image display devices include liquid crystal display (LCD), deformable mirror device (DMD) and AMA. Such projection image display apparatuses can be further divided into two groups according to their optical characteristics. That is, devices such as LCDs can be classified as transmissive spatial light modulators, while DMD and AMA can be classified as reflective spatial light modulators.

Transmission optical modulators, such as LCDs, have a very simple optical structure, which makes them thinner, lighter in weight, and smaller in volume. However, the light efficiency is low due to the polarity of the light, there is a problem inherent in the liquid crystal material, for example, the response speed is slow and its inside is easy to overheat. In addition, the maximum light efficiency of existing transmission optical modulators is limited to a range of 1-2% and requires dark room conditions to provide acceptable display quality. Therefore, optical modulators such as DMD and AMA have been developed to solve the above problems.

Although DMD shows a relatively good light efficiency of about 5%, the hinge structure employed in the DMD not only causes serious fatigue problems, but also requires a very complicated and expensive driving circuit. In the AMA, each of the mirrors installed therein reflects light incident from the light source at a predetermined angle, and the reflected light is projected on the screen through an aperture such as a slit or a pinhole. It is a device that can adjust the speed of light to form an image. Therefore, its structure and operation principle are simple, and high light efficiency (more than 10% light efficiency) can be obtained compared to LCD or DMD. In addition, the contrast of the image projected on the screen is improved to obtain a brighter and clearer image.

These AMA devices are largely divided into bulk type and thin film type. The bulk optical path control device is disclosed in US Pat. No. 5,085,497 to Gregory Um et al. The bulk optical path control device is made by thinly cutting a multilayer ceramic to mount a ceramic wafer having a metal electrode formed therein into an active matrix in which transistors are built, and then processing it using a sawing method and installing a mirror thereon. However, the bulk optical path control device requires very high precision in design and manufacturing, and has a disadvantage in that the response of the deformation layer is slow.

Accordingly, a thin film type optical path control device (TMA) that can be manufactured using a semiconductor manufacturing process has been developed. Such a thin film type optical path control device is disclosed in Korean Patent Application No. 98-26300 (name of the invention: a method of manufacturing a thin film type optical path control device) filed by the applicant of the Korean Patent Office on June 30, 1998.

Figure 1 shows a perspective view of the thin film type optical path control device described in the preceding application, Figure 2 shows a cross-sectional view of the device of Figure 1 cut along the line A ₁ -A ₂ .

1 and 2, the thin film type optical path control device includes an active matrix 16, a support element 18, an actuator 31, and a mirror 41.

The active matrix 16 extends from a substrate 1 in which M x N (M, N is a natural number) MOS transistors 5, a drain 2 and a source 3 of the MOS transistor 5. The first metal layer 8 formed on the substrate 1 and the first protective layer 9, the second metal layer 10, the second protective layer 12, and the etch stop layer 13 which are sequentially formed on the substrate 1 are included. do.

The support element 18 comprises a support line 20, a support layer 19, a first anchor 21 and second anchors 22a, 22b. The support line 20 and the support layer 19 are horizontally formed on the etch stop layer 13 via the first air gap 15. The common electrode line 32 is formed on the support line 20. The support layer 19 is integrally formed along the direction orthogonal to the support line 20 in the shape of a rectangular ring on the same plane. A first anchor 21 is integrally formed with the two arms and attached to the etch stop layer 13 at a lower portion between two arms horizontally extending in a direction orthogonal to the support line 20 of the support layer 19. Two second anchors 22a and 22b are integrally formed with the two arms and attached to the etch stop layer 13 at the outer lower portion of the two arms. The first anchor 21 is formed on a portion where the drain pad of the first metal layer 8 is positioned below the etch stop layer 13, and the drain pad of the first metal layer 8 is formed from the center of the first anchor 21. Until the via hole 38 is formed.

The actuator 31 includes a lower electrode 24, a first strained layer 26, a second strained layer 27, a first upper electrode 29, and a second upper electrode 30. The lower electrode 24 has a mirror-shaped 'c' shape spaced apart from the support line 20 by a predetermined distance, and one side of the lower electrode 24 has a stepped protrusion toward the first anchor 21. Are formed corresponding to each other. The protrusions of the lower electrode 24 extend to the periphery of the via hole 38 formed in the first anchor 21, respectively. The via contact 39 is formed from the drain pad of the first metal layer 8 to the protrusions of the lower electrode 24 through the via hole 38 to electrically connect the drain pad and the lower electrode 24. The first and second strain layers 26 and 27 are formed on the two arms of the lower electrode 24, respectively, and the first and second upper electrodes 29 and 30 are respectively the first and second strains. On top of layers 26 and 27.

The first insulating layer 34 is formed from one side of the first upper electrode 29 to a part of the supporting layer 19, and the first insulating layer 34 and the supporting layer 19 from one side of the first upper electrode 29. The first upper electrode connecting member 36 is formed up to the common electrode line 32 through a portion of the upper electrode connecting member 36. In addition, a second insulating layer 35 is formed from one side of the second upper electrode 30 to a part of the support layer 19, and the second insulating layer 35 and the supporting layer (from one side of the second upper electrode 30) A second upper electrode connecting member 37 is formed up to the common electrode line 32 through a portion of 19.

The reflectance increasing layer 45 and the mirror 41 may be formed on a portion of the lower electrode 24 in which the first and second upper electrodes 29 and 30 are not formed, that is, parallel to the support line 20. A supporting post 40 is formed. The reflectivity increasing layer 45 and the mirror 41 are supported at the center portion by the post 40, and both sides thereof are formed horizontally on the actuator 31 via the second air gap 43. The reflectivity increasing layer 45 and the mirror 41 reflect light incident from a light source (not shown) at a predetermined angle.

Hereinafter, a method of manufacturing the above-described thin film type optical path control device will be described.

3A to 3C are diagrams for describing a method of manufacturing the apparatus shown in FIG. 2. Referring to FIG. 3A, a device isolation layer 6 is formed on the substrate 1, which is an n-type doped silicon wafer, to separate an active region and a field region, and a gate 4 formed of polysilicon on the active region. After forming P, the P ⁺ MOS transistors 5 are formed on the substrate 1 by forming the p ⁺ source 3 and the drain 2 by an ion implantation process. .

After the insulating film 7 made of oxide is formed on the P-MOS transistor 5 formed thereon, openings are formed to expose the upper portions of the one side of the source 3 and the drain 2 by photolithography. Next, after depositing the first metal layer 8 made of titanium, titanium nitride, tungsten, nitride, or the like on the resultant, the first metal layer 8 is patterned. The first metal layer 8 includes a drain pad extending from the drain 2 of the P-MOS transistor 5 to the bottom of the first anchor 21.

A first protective layer 9 is formed on the first metal layer 8 and the substrate 1 to prevent the substrate 1 having the P-MOS transistor 5 therein from being damaged. The first protective layer 9 is laminated with an silicate glass (PSG) having a thickness of 8000 kPa by chemical vapor deposition (CVD). The second metal layer 10 is formed on the first protective layer 9. The second metal layer 10 is formed by sputtering titanium to form a titanium layer with a thickness of 300 kV, and then forming a titanium nitride layer having a thickness of 1200 kV on the titanium layer by physical vapor deposition (PVD). Is completed. The second metal layer 10 prevents the device from malfunctioning due to the leakage current caused by the incident light. Subsequently, a hole in the second metal layer 10 is etched by etching the portion of the second metal layer 10 where the drain pad of the first metal layer 8 is positioned below which the via hole 38 is to be formed. To form.

On the upper portion of the second metal layer 10, a second protective layer 12 in which the silicate glass PSG is deposited to a thickness of about 2000 kPa by chemical vapor deposition is formed. On top of the second passivation layer 12, an etch stop layer 13 is deposited to prevent the second passivation layer 12 and the products on the substrate 1 from being etched during the subsequent etching process. The etch stop layer 13 is formed of a low temperature oxide such as silicon oxide (SiO ₂ ) or phosphorus pentoxide (P ₂ O ₅ ), and is formed to have a thickness of 0.2 to 0.8 μm by low pressure chemical vapor deposition (LPCVD). Accordingly, the active matrix 16 including the substrate 1, the first metal layer 8, the first protective layer 9, the second metal layer 10, the second protective layer 12, and the etch stop layer 13. Is completed.

The first sacrificial layer 14 is stacked on the etch stop layer 13. The first sacrificial layer 14 is formed of polysilicon to have a thickness of 2.0 to 3.0 μm by low pressure chemical vapor deposition (LPCVD). Subsequently, the surface of the first sacrificial layer 14 is polished by chemical mechanical polishing (CMP) to planarize the surface of the first sacrificial layer 14 to have a thickness of 1.1 mu m. Subsequently, after applying and patterning a first photoresist (not shown) on top of the first sacrificial layer 14, the second metal layer 10 below the first sacrificial layer 14 is used as a mask. The first anchor 21 and the second anchors 22a and 22b supporting the supporting layer 19 formed later by etching the portion where the hole of the hole and the portions adjacent to both sides thereof are etched to expose a portion of the etch stop layer 13. ) And the first photoresist is removed. Accordingly, the etch stop layer 13 is exposed in three rectangular shapes spaced apart by a predetermined distance.

The first layer 17 is stacked on the upper portion of the etch stop layer 13 and the first sacrificial layer 14 exposed in a rectangular shape as described above. The first layer 17 is formed by depositing nitride to have a thickness of 0.1 to 1.0 μm by a low pressure chemical vapor deposition method. The lower electrode layer 23 formed by the sputtering method or the chemical vapor deposition method is stacked on the first layer 17. The lower electrode layer 23 is made of metal such as platinum (Pt), tantalum (Ta), or platinum-tantalum (Pt-Ta), and has a thickness of 0.1 to 1.0 mu m. The second layer 25 made of a piezoelectric material is stacked on the lower electrode layer 23. The second layer 25 is formed by spin coating PZT prepared by the sol-gel method to have a thickness of 0.4 μm. Subsequently, the piezoelectric material constituting the second layer 25 is subjected to heat treatment by rapid thermal treatment (RTA) to cause phase shift. The upper electrode layer 28 is stacked on top of the second layer 25. The upper electrode layer 28 is formed to have a thickness of 0.1 to 1.0 mu m by depositing platinum, tantalum, silver, or platinum-tantalum by a sputtering method or a chemical vapor deposition method.

Referring to FIG. 3B, after applying and patterning a second photoresist (not shown) on the upper electrode layer 28, the upper electrode layer 28 has a rectangular flat shape using the upper electrode layer 28 as a mask. After patterning the first and second upper electrodes (29, 30) spaced apart by the distance of the second photoresist.

Subsequently, the second layer 25 is patterned in the same manner as the patterning of the upper electrode layer 28 to form a rectangular flat plate, and the first and second strained layers 26 and 27 spaced apart by a predetermined distance. To form. Subsequently, the lower electrode layer 23 has a mirror-shaped 'c' shape with respect to the support line 20 formed later by patterning the lower electrode layer 23, and has a lower electrode 24 having protrusions formed stepped toward the first anchor 21. ). In addition, when the lower electrode layer 23 is patterned, a common electrode line 32 is formed together with the lower electrode 24 on one side of the first layer 17. The common electrode line 32 is formed to be spaced apart from the lower electrode 24 by a predetermined distance on the support line 20 formed later.

The first layer 17 is then patterned to form a support element 18 comprising a support layer 19, a support line 20, a first anchor 21 and second anchors 22a, 22b. At this time, both sides of the portion of the first layer 17 which contacts the etch stop layer 13 exposed in the three rectangular shapes are second anchors 22a and 22b, and the central portion of the first layer 17 is the first anchor 21. Becomes Each of the first anchor 21 and the second anchors 22a and 2b has a rectangular box shape, the first anchor 21 is formed below the lower electrode 24, and the second anchors 22a are formed. , 22b are formed on the outer bottom of the lower electrode 24, respectively.

Subsequently, a third photoresist (not shown) is applied and patterned on the support element 18 and the actuator 31 to form first and second upper portions from the common electrode line 32 formed on the support line 19. A part of the electrodes 29 and 30 are exposed respectively. At this time, even the protrusions of the lower electrode 24 are exposed together from the first anchor 21. Subsequently, by depositing and patterning amorphous silicon or silicon oxide or phosphorus pentoxide, which is a low temperature oxide, on the exposed portion, a portion of the first upper electrode 29 is formed through the first strained layer 26 and the lower electrode 24. The first insulating layer 34 is formed to a part of the support layer 19, and at the same time, a part of the support layer 19 through the second strained layer 27 and the lower electrode 24 from a part of the second upper electrode 30. Until the second insulating layer 35 is formed. The first and second insulating layers 34 and 35 are formed to have a thickness of 0.2 to 0.4 µm, respectively, by a low pressure chemical vapor deposition method.

The first anchor 21, the etch stop layer 13, and the second anchor 21 are formed from a central portion of the first anchor 21, which is a portion where the hole of the second metal layer 10 and the drain pad of the first metal layer 8 are formed. After the protective layer 12 and the first protective layer 9 are etched to form the via hole 38 to the drain pad, the via contact 39 is formed from the drain pad to the protrusions of the lower electrode 24 through the via hole 38. ). At the same time, from the first upper electrode connecting member 36 and the second upper electrode 30 to the common electrode line 32 through the part of the first insulating layer 34 and the supporting layer 19 from the first upper electrode 29. A second upper electrode connecting member 37 is formed to the common electrode line 32 through a portion of the second insulating layer 35 and the support layer 19. The via contact 39 and the first and second upper electrode connecting members 36 and 37 are deposited by depositing platinum or platinum-tantalum to have a thickness of 0.1 to 0.2 μm by sputtering or chemical vapor deposition. Patterned metal is formed. The first and second upper electrode connecting members 36 and 37 connect the first and second upper electrodes 29 and 30 to the common electrode line 32, respectively, and the lower electrode 24 connects the via contact 39. It is connected to the drain pad through.

Referring to FIG. 3C, a second sacrificial layer 42 is formed on top of the actuator 31 and the support element 18 using photoresist or polysilicon. When using a photoresist, the second sacrificial layer 42 is formed by spin coating, that is, multi-coating several times so that the general photoresist can completely cover the actuator 31. The method of forming the second sacrificial layer 42 by multi-coating the photoresist is as follows.

First, the conventional photoresist is spin-coated once and then baked properly so that the photoresist is then evenly deposited. The photoresist is then spin coated twice and the process repeated. This process is repeated four times, and when the thickness of the photoresist is about 5 μm, it is used as the second sacrificial layer 42.

Subsequently, the second sacrificial layer 42 is patterned so that the first and second upper electrodes 29 and 30 of the lower electrode 24 are not formed, that is, parallel to the support line 20. Expose a portion of the formed part.

Aluminum or an aluminum alloy is deposited on the exposed lower electrode 24 and the second sacrificial layer 42 by physical vapor deposition (PVD) or chemical vapor deposition, and then a dielectric layer and a metal layer thereon. A reflectance enhancement layer 45 composed of a multilayer thin film of is deposited by a sputtering method or a chemical vapor deposition method. Subsequently, the deposited metal layer and the dielectric layer are patterned so that the posts from the exposed reflecting layer 45 and the mirror 41 and the exposed lower electrode 24 to the center lower portion of the mirror 41 may each have a rectangular flat plate shape. 40) are formed simultaneously. Then, the second sacrificial layer 42 is removed using an oxygen plasma (O ₂ plasma), and then the first sacrificial layer 14 is removed using xenon fluoride (XeF ₂ ) or bromine fluoride (BrF ₂ ). And cleaning and drying treatments to complete the TMA device.

However, in the above-described manufacturing method of the thin film type optical path control apparatus, since the second sacrificial layer is formed by coating the photoresist several times, the possibility of defects in the photoresist during the multi-coating of the photoresist becomes very high. The problem arises that the yield of a process falls significantly. The defect of the second sacrificial layer causes problems such as lowering the horizontality of the mirror formed thereon, making it difficult to deposit the mirror. There is also a difficulty in that the total process time including the time for forming the second sacrificial layer becomes very long.

Accordingly, an object of the present invention is to form a second sacrificial layer using a photoresist that is significantly thicker than usual, thereby preventing the defects of the second sacrificial layer, shortening the processing time, and improving the process yield. It is to provide a method of manufacturing the device.

1 is a perspective view of a thin film type optical path adjusting device described in the applicant's prior application.

FIG. 2 is a cross-sectional view of the apparatus shown in FIG. _{1 taken along} lines A ₁ -A ₂ .

3A to 3C are manufacturing process diagrams of the apparatus shown in FIG. 2.

Figure 4 is a perspective view of a thin film type optical path control apparatus according to the present invention.

5 is a cross-sectional view of the apparatus of FIG. 4 taken along line B ₁ -B ₂ .

6A to 6E are manufacturing process diagrams of the apparatus shown in FIG.

<Explanation of symbols for main parts of the drawings>

100: active matrix 101: substrate

120: transistor 135: first metal layer

140: first protective layer 145: second metal layer

150: second protective layer 155: etch stop layer

160: first sacrificial layer 170: support layer

171: first anchor 172a, 172b: second anchor

174: support line 175: support element

180: lower electrode 190, 191: first and second strained layers

200, 201: first and second upper electrodes 210: actuators

220, 221: first and second insulating layers

230 and 231: first and second upper electrode connecting members

250: Post 260: Mirror

270: Beer Hall 280: Beer Contact

300: second sacrificial layer

In order to achieve the object of the present invention described above, the present invention provides a method of forming a support element and an actuator on top of an active matrix including a first metal layer having a transistor embedded therein and having a drain pad, while rotating the active matrix at a low speed. Forming a second sacrificial layer comprising spreading a photoresist on top of the support means and the actuator and adjusting the thickness of the photoresist while rotating the active matrix at high speed, and the second It provides a method of manufacturing a thin film type optical path control device comprising the step of forming a mirror on top of the sacrificial layer. The forming of the actuator and the supporting element may include forming and patterning a first sacrificial layer on an active matrix, and then forming a first layer, a lower electrode layer, a second layer, and an upper electrode layer thereon, and then forming the first sacrificial layer on the active matrix. Patterning an electrode layer, the second layer and the lower electrode layer to form a lower electrode, a first strained layer, a second strained layer, a first upper electrode and a second upper electrode, patterning the first layer to support a line; Forming a support layer and first and second anchors.

According to the present invention, the thick photoresist is spread at low speed, and then the spread photoresist is rotated at high speed to form a second sacrificial layer while adjusting its thickness. Therefore, since the second sacrificial layer is formed by one spin coating, the process time can be significantly shorter than in the case of multi-coating, and it is remarkably advantageous in terms of process yield. In addition, the uniformity of the photoresist constituting the second sacrificial layer is greatly improved as compared with the case of multiple coating.

Hereinafter, a manufacturing method of a thin film type optical path control device according to a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

Figure 4 shows a perspective view of the thin film type optical path control apparatus according to the present invention, Figure 5 shows a cross-sectional view of the device of Figure 4 cut line B ₁ -B ₂ .

4 and 5, the thin film type optical path control apparatus according to the present invention includes an active matrix 100, a support element 175 formed on the active matrix 100, and an actuator formed on the support element 175. 210, and a mirror 260 formed on the actuator 210.

The active matrix 100 includes a substrate 101 having M × N (M, N is a natural number) P-MOS transistors 120, a drain 105 and a source 110 of the P-MOS transistors 120. 2) formed on the first metal layer 135 formed on the substrate 101, the first passivation layer 140 formed on the first metal layer 135, and the first passivation layer 140 formed on the substrate 101. The metal layer 145, the second protective layer 150 formed on the second metal layer 145, and the etch stop layer 155 formed on the second protective layer 150 are included.

The first metal layer 135 includes a drain pad extending from the drain 105 of the P-MOS transistor 120 to transmit a first signal (image signal), and the second metal layer 145 includes a titanium layer and It consists of a titanium nitride layer.

Referring to FIG. 4, the support element 175 includes a support line 174, a support layer 170, a first anchor 171, and second anchors 172a and 172b. The support line 174 and the support layer 170 are horizontally formed on the etch stop layer 155 via the first air gap 165. The common electrode line 240 is formed on the support line 174, and the support line 174 serves to support the common electrode line 240.

The support layer 170 has a rectangular ring shape, preferably a rectangular ring shape, and is integrally formed along a direction orthogonal to the support line 174 on the same plane. A first anchor 171 is integrally formed with the two arms and etched in a lower portion between two arms horizontally extending in a direction orthogonal to the support line 174 of the support layer 170 having the shape of a square ring. Attached to the barrier layer 155, two second anchors 172a and 172b are formed integrally with the two arms and attached to the etch stop layer 155 at the outer lower portion of the two arms. The first anchor 171 and the second anchors 172a and 172b each have a shape of a rectangular box.

The support layer 170 is centrally supported by the first anchor 171, and both sides are supported by the second anchors 172a and 172b, so that the support layer 170 and the anchors 171, 172a and 172b are cross-sectioned. Has the shape of a 'T' as shown in FIG.

The first anchor 171 is formed on a portion of the etch stop layer 155 where the drain pad of the first metal layer 135 is located. In the central portion of the first anchor 171, the first metal layer may be formed through the etch stop layer 155, the second passivation layer 150, the holes (not shown) of the second metal layer 145, and the first passivation layer 140. The via hole 270 is formed to the drain pad of the 135.

The actuator 210 is formed to have a mirror-shaped 'c' shape on the support layer 170. The actuator 210 includes a lower electrode 180, a first strained layer 190, a second strained layer 191, a first upper electrode 200, and a second upper electrode 201. The lower electrode 180 has a mirror-shaped 'c' shape spaced apart from the support line 174 by a predetermined distance, and is directed toward the first anchor 171 on both sides of one side of the lower electrode 180. The protrusions are formed stepwise to correspond to each other. The protrusions of the lower electrode 180 extend to the periphery of the via hole 270 formed in the first anchor 171, respectively. The via contact 280 is formed from the drain pad to the protrusion of the lower electrode 180 through the via hole 280 to electrically connect the drain pad and the lower electrode 180.

The two arms of the lower electrode 180 each have a shape of a rectangular plate, and the first and second deformable layers 190 and 191 respectively have a shape of a rectangular plate having a smaller area than the two arms of the lower electrode 180. And is formed on top of two arms of the lower electrode 180. In addition, the first and second upper electrodes 200 and 201 have a shape of a rectangular plate having a smaller area than the first and second deformable layers 190 and 191, respectively, and have the first and second deformed layers 190 and 191. It is formed at the top of the.

The first insulating layer 220 is formed from one side of the first upper electrode 200 to a part of the support layer 170 through the first deforming layer 190 and the lower electrode 180, and the first upper electrode 200. The first upper electrode connecting member 230 is formed from one side of the first through the first insulating layer 220 and the support layer 170 to the common electrode line 240. The first upper electrode connecting member 230 connects the first upper electrode 200 and the common electrode line 240 to each other, and the first insulating layer 220 may include the first upper electrode 200 and the lower electrode 180. They are connected to each other to prevent electrical shorts.

In addition, a second insulating layer 221 is formed from one side of the second upper electrode 201 to a part of the support layer 170 through the second deformable layer 191 and the lower electrode 180. The second upper electrode connecting member 231 is formed from one side of the second upper electrode 201 to the common electrode line 240 through a portion of the second insulating layer 221 and the support layer 170. The second insulating layer 221 and the second upper electrode connecting member 231 are formed to be parallel to the first insulating layer 220 and the first upper electrode connecting member 230, respectively. The second upper electrode connecting member 231 connects the second upper electrode 201 and the common electrode line 240 to each other, and the second insulating layer 221 is formed by the second upper electrode 201 and the lower electrode 180. They are connected to each other to prevent electrical shorts.

Posts for supporting mirrors in portions of the mirror-shaped 'C'-shaped lower electrode 180 where the first and second upper electrodes 200 and 201 are not formed, that is, parallel to the support line 174. 250 is formed. The mirror 260 is supported at the center portion by the post 250, and both sides thereof are horizontally formed on the upper portion of the actuator 210 via the second air gap 310. The mirror 260 serves to reflect light incident from a light source (not shown) at a predetermined angle.

In the above-described thin film type optical path control apparatus according to the present invention, the first signal transmitted from the outside is the MOS transistor 120 embedded in the active matrix 100, the drain pad and the via contact 280 of the first metal layer 120. Is applied to the lower electrode 180, and at the same time, a second signal is applied to the first and second upper electrodes 200 and 201 through the common electrode line 240 from the outside, respectively, and thus, the first upper electrode 200 is applied. And a first electric field is generated between the one side of the lower electrode 180 and the second electric field according to the potential difference between the second upper electrode 201 and the other side of the lower electrode 180. The first strained layer 190 formed between one side of the first upper electrode 200 and the lower electrode 180 causes deformation by the first electric field, and at the same time, the second upper electrode 201 is caused by the second electric field. And the second strained layer 191 formed between the other side of the lower electrode 180 cause deformation.

As the first and second strained layers 190 and 191 contract in a direction orthogonal to the first and second electric fields, respectively, the actuator 210 including the first and second strained layers 190 and 191 may be formed. It is bent at a predetermined angle. The mirror 260 reflecting light incident from the light source is inclined together with the actuator 210 because the mirror 260 is supported by the post 250 and is formed on the actuator 210. Accordingly, the mirror 260 reflects incident light at a predetermined angle, and the reflected light passes through the slit to form an image on the screen.

Hereinafter, a method of manufacturing a thin film type optical path control device according to the present invention will be described in detail with reference to the accompanying drawings.

6A to 6E are diagrams for describing a method of manufacturing the apparatus shown in FIGS. 4 and 5. In Figs. 6A to 6E, the same reference numerals are used for the same members as Figs. 4 and 5.

Referring to FIG. 6A, after preparing a substrate 101, which is an n-type doped silicon wafer, the substrate 101 is divided into an active region and a field region by using a silicon partial oxidation (LOCOS) method, which is a conventional device isolation process. The device isolation film 125 is formed. Subsequently, a gate 115 made of a conductive material such as polysilicon doped with impurities is formed on the active region, and then p ⁺ source 110 and drain 105 are formed by using an ion implantation process. M × N (M and N are natural numbers) P-MOS transistors 120 are formed on the substrate 101.

After forming an insulating film made of an oxide on the resultant formed P-MOS transistor 120, by using a photolithography method to form openings for exposing the top of one side of the source 110 and drain 105, respectively. Subsequently, after depositing the first metal layer 135 made of titanium, titanium nitride, tungsten, nitride, or the like on the resultant, the first metal layer 135 is patterned by photolithography. The patterned first metal layer 135 includes a drain pad extending from the drain 105 of the P-MOS transistor 120 to a lower portion of the first anchor 171 supporting the support layer 170.

A first passivation layer 140 made of insulated glass (PSG) is formed on the first metal layer 135 and the substrate 101. The first protective layer 140 is formed to have a thickness of about 8000 kPa by chemical vapor deposition (CVD). The first protective layer 140 prevents damage to the substrate 101 in which the P-MOS transistor 120 is embedded during the subsequent process.

The second metal layer 145 is formed on the first protective layer 140. The second metal layer 145 is formed by sputtering titanium to form a titanium layer having a thickness of about 300 μs, and then depositing titanium nitride on the titanium layer by physical vapor deposition (PVD) to have a thickness of about 1200 μs. It is completed by forming a titanium nitride layer. Since the light incident from the light source is incident not only to the mirror 260 but also to a portion other than the portion covered by the mirror 260, the second metal layer 145 causes a photocurrent to flow in the active matrix 100, causing the device to malfunction. To prevent them. Subsequently, a portion of the second metal layer 145 in which the via hole 270 is to be formed in a subsequent process, that is, a portion in which the drain pad of the first metal layer 135 is positioned is etched and then etched into the second metal layer 145. Not formed).

The second passivation layer 150 using the silicate glass PSG is stacked on the second metal layer 145. The second protective layer 150 is formed to have a thickness of about 2000 kPa by chemical vapor deposition. The second protective layer 150 prevents the substrate 101 and the resulting products formed on the substrate 101 from being damaged during subsequent processing.

An etch stop layer 155 is stacked on the second passivation layer 150. The etch stop layer 155 prevents the results on the second passivation layer 150 and the substrate 101 from being etched during the subsequent etching process. The etch stop layer 155 is made of low temperature oxide (LTO) such as silicon oxide or phosphorus pentoxide. The etch stop layer 155 is formed to have a thickness of about 0.2 to 0.8 μm at a temperature of about 350 to 450 ° C. using a low pressure chemical vapor deposition (LPCVD) method. Therefore, the active matrix 100 including the substrate 101, the first metal layer 135, the first protective layer 140, the second metal layer 145, the second protective layer 150, and the etch stop layer 155. Is completed.

The first sacrificial layer 160 made of polysilicon is stacked on the etch stop layer 155. The first sacrificial layer 160 serves to facilitate stacking of the thin films constituting the actuator 210. The first sacrificial layer 160 is formed to have a thickness of about 2.0 to 3.0 μm by low pressure chemical vapor deposition (LPCVD) at a temperature of about 500 ° C. or less. Subsequently, the surface of the first sacrificial layer 160 is polished using a chemical mechanical polishing (CMP) method to planarize the surface of the first sacrificial layer 160 to have a thickness of about 1.1 μm.

6B is a plan view illustrating a state in which the first sacrificial layer 160 is patterned. 6A and 6B, after applying and patterning a first photoresist (not shown) on the first sacrificial layer 160, the first sacrificial layer (using the first photoresist as a mask) The portion of the second metal layer 145 where the hole of the second metal layer 145 is positioned and the portions adjacent to both sides thereof are etched to expose a portion of the etch stop layer 155, so that the first anchor 171 and the second anchors later ( 172a and 172b are made to be formed. Therefore, the etch stop layer 155 is exposed in the shape of three squares spaced apart by a predetermined distance. Subsequently, the first photoresist is removed.

Referring to FIG. 6C, the first layer 169 is stacked on top of the etch stop layer 155 and the first sacrificial layer 160 exposed in a quadrangle as described above. The first layer 169 is formed to have a thickness of about 0.1 to 1.0 μm by depositing a hard material such as nitride by low pressure chemical vapor deposition (LPCVD). The first layer 169 is later patterned with a support element 175.

The lower electrode layer 179 is stacked on top of the first layer 179. The lower electrode layer 179 is formed by depositing a metal having electrical conductivity such as platinum (Pt), tantalum (Ta), or platinum-tantalum (Pt-Ta) by a sputtering method or a chemical vapor deposition method, and having a thickness of about 0.1 to 1.0 μm. Form to have. The lower electrode layer 179 is later applied with a first signal (image signal) from the outside and patterned into a lower electrode 180 having a mirror-shaped 'c' shape.

A second layer 189 made of a piezoelectric material such as PZT or PLZT is stacked on the lower electrode layer 179. Preferably, the second layer 189 is formed by spin coating PZT prepared by the sol-gel method to have a thickness of about 0.4 μm. Subsequently, the piezoelectric material constituting the second layer 189 is subjected to heat treatment by a rapid thermal treatment (RTA) method for phase shifting. The second layer 189 may be the first strained layer 190 and the second upper electrode 210 which are deformed by a first electric field generated between the first upper electrode 200 and the lower electrode 180 later. And a second deformation layer 191 causing deformation by a second electric field generated between the other side of the lower electrode 180 and the other side.

The upper electrode layer 199 is stacked on top of the second layer 189. The upper electrode layer 199 is formed by depositing a metal having electrical conductivity such as platinum, tantalum, silver, or platinum-tantalum by sputtering or chemical vapor deposition to have a thickness of about 0.1 to 1.0 μm. The upper electrode layer 199 is later patterned with a first upper electrode 200 and a second upper electrode 201, each of which is applied with a second signal (bias signal) and spaced apart by a predetermined distance.

Referring to FIG. 6D, after applying and patterning a second photoresist (not shown) on the upper electrode layer 199, the upper electrode layer 199 may be squared using the second photoresist as a mask. The first upper electrode 200 and the second upper electrode 201 may have a shape of a flat plate, preferably a rectangular flat plate, and may be spaced apart from each other by a predetermined distance. The second signal is applied to the first and second upper electrodes 200 and 201 through the common electrode line 240 formed later from the outside, respectively. Subsequently, the second photoresist is removed.

Subsequently, the second deforming layer 190 is patterned in the same manner as the method of patterning the upper electrode layer 199, each having a shape of a rectangular flat plate, and separated from each other by a predetermined distance to form the first strained layer 190. And a second strained layer 191. In this case, as shown in FIG. 4, the first and second deformable layers 190 and 191 are patterned to have a rectangular flat plate shape slightly wider than the first and second upper electrodes 200 and 201, respectively.

Subsequently, the lower electrode layer 179 is patterned in the same manner as the patterning of the upper electrode layer 199 to have a mirror-shaped 'C' shape for the support line 174 formed later, and the first anchor 171 may be formed. Towards the lower electrode 180 having a protrusion formed in a stepped shape is formed. In this case, the two arms of the lower electrode 180 have the shape of a rectangular flat plate having a larger area than the first and second deforming layers 190 and 191, respectively.

In addition, when the lower electrode layer 179 is patterned, the common electrode line 240 is simultaneously formed with the lower electrode 180 in a direction orthogonal to the lower electrode 180 on one side of the first layer 169. The common electrode line 240 is formed to be spaced apart from the lower electrode 180 by a predetermined distance on the support line 174 formed later. Thus, the actuator 210 including the first and second upper electrodes 200 and 201, the first and second strained layers 190 and 191, and the lower electrode 180 is completed.

Subsequently, the first layer 169 is patterned to form a support element 175 comprising a support layer 170, a support line 174, a first anchor 171 and second anchors 172a and 172b. . At this time, both sides of the portion of the first layer 169 which contacts the etch stop layer 155 exposed in the three quadrangles are second anchors 172a and 172b, and the center portion of the first anchor 171 is do. Each of the first anchor 171 and the second anchors 172a and 172b has a rectangular box shape, and a hole of the second metal layer 145 and a hole of the first metal layer 135 are disposed below the first anchor 171. The drain pad is located.

The first and second upper electrodes 200 and 201 are formed to be parallel to each other on top of two arms horizontally extending in a direction orthogonal to the support line 174 of the support layer 170, respectively. Accordingly, the first anchor 171 is formed below the lower electrode 180, and the second anchors 172a and 172b are formed below the outer electrode 180, respectively.

Subsequently, a third photoresist (not shown) is applied on the upper portion of the support element 175 and the upper portion of the actuator 210 and patterned to form a first photoresist from the common electrode line 240 formed on the support line 174. Part of the upper electrode 200 and the second upper electrode 201 are exposed. At this time, the protrusions of the lower electrode 180 are also exposed together from the first anchor 171.

Subsequently, the first strained layer 190 and the lower electrode 180 may be removed from a portion of the first upper electrode 200 by depositing and patterning amorphous silicon or silicon oxide or phosphorus pentoxide, which is a low temperature oxide, on the exposed portion. The first insulating layer 220 is formed up to a part of the support layer 170, and at the same time, the support layer 170 is formed through the second strained layer 191 and the lower electrode 180 from a part of the second upper electrode 201. The second insulating layer 221 is formed to a part. The first insulating layer 220 and the second insulating layer 221 are formed to have a thickness of about 0.2 to 0.4 μm, preferably about 0.3 μm, respectively, using a low pressure chemical vapor deposition method.

The first anchor 171, the etch stop layer 155, and the etch stop layer 155 are formed from the center of the first anchor 171, which is a portion where the hole of the second metal layer 145 and the drain pad of the first metal layer 135 are formed below. After the second protective layer 150 and the first protective layer 140 are etched to form the via hole 270 to the drain pad, the via contact extends from the drain pad to the protrusions of the lower electrode 180 through the via hole 270. 280 is formed. At the same time, the first upper electrode connecting member 230 and the second upper electrode 201 extend from the first upper electrode 200 to the common electrode line 240 through a part of the first insulating layer 220 and the support layer 170. The second upper electrode connecting member 231 is formed from the second insulating layer 221 and the support layer 170 to the common electrode line 240.

The via contact 280 and the first and second upper electrode connection members 230 and 231 are deposited to have a thickness of about 0.1 to 0.2 μm by depositing platinum or platinum-tantalum by sputtering or chemical vapor deposition. After that, the deposited metal is formed by patterning. The first and second upper electrode connecting members 230 and 231 connect the first and second upper electrodes 200 and 201 and the common electrode line 240, respectively, and the lower electrode 180 connects the via contact 280. It is connected to the drain pad through.

Referring to FIG. 6E, a second sacrificial layer 300 is formed using a thick photoresist on top of the actuator 210 and the support element 175. First, while rotating the active matrix 100 formed in the actuator 210 at a low speed of about 400 to 500rpm, the photoresist is spread on the upper portion thereof. Subsequently, in order to adjust the thickness of the photoresist constituting the second sacrificial layer 300 and to secure the overall uniformity, the actuator (the active matrix 100) is rotated at a high speed of about 2500 to 3500 rpm to obtain an actuator ( The second sacrificial layer 300 having a thickness of about 5.0 μm or more, which is high enough to completely cover 210, is completed. As such, the second sacrificial layer 300 formed by spin coating the thick photoresist once does not require a separate surface planarization process such as a chemical mechanical polishing process, thereby greatly increasing the process time for forming the second sacrificial layer 300. It can be shortened.

Subsequently, the second sacrificial layer 300 is patterned to form the mirror 260 and the post 250, so that the second sacrificial layer 300 is not adjacent to the support line 174 of the 'C' lower electrode 180. A portion (ie, a portion where the first and second upper electrodes 200 and 201 are not formed) is exposed. Next, a metal such as aluminum (Al) having reflective properties is deposited on a portion of the exposed lower electrode 180 and on the second sacrificial layer 300 by a sputtering method or a chemical vapor deposition method, and then the deposited metal is deposited. The metal is patterned to simultaneously form a mirror 260 having a rectangular flat plate shape and a post 250 supporting the mirror 260. After etching the second sacrificial layer 300, the first sacrificial layer 160 is removed with xenon fluoride (XeF ₂ ) or bromine fluoride (BrF ₂ ), and a cleaning and drying process is performed in FIG. 4. The TMA element as shown is completed. As described above, when the second sacrificial layer 300 is removed, the second air gap 310 is formed at the position of the second sacrificial layer 300, and when the first sacrificial layer 160 is removed, the first sacrificial layer 160 is removed. The first air gap 165 is formed at the position of.

According to the present invention, the thick photoresist is spread at low speed, and then the spread photoresist is rotated at high speed to form a second sacrificial layer while adjusting its thickness. Therefore, since the second sacrificial layer is formed through one spin coating, the process time can be greatly shortened than in the case of multi-coating, and it is remarkably advantageous in terms of process yield. In addition, the uniformity of the photoresist constituting the second sacrificial layer is greatly improved compared to the multiple coating.

As described above, although described with reference to a preferred embodiment of the present invention, those skilled in the art will be modified in various ways without departing from the spirit and scope of the invention described in the claims below. And can be changed.

Claims (2)

Providing an active matrix including a first metal layer having a MOS transistor embedded therein and having a drain pad extending from the drain of the transistor; Forming and patterning a first sacrificial layer on the active matrix; Forming a first layer, a lower electrode layer, a second layer, and an upper electrode layer on the active matrix and the first sacrificial layer; Patterning the upper electrode layer, the second layer and the lower electrode layer to form an actuator including a lower electrode, a first strained layer, a second strained layer, a first upper electrode, and a second upper electrode; Patterning the first layer to form a support line, a support layer, and support means including first and second anchors; Spreading the photoresist on the support means and the actuator while rotating the active matrix at a low speed; and adjusting a thickness of the photoresist while rotating the active matrix at a high speed. Forming; And And forming a mirror on an upper portion of the second sacrificial layer. The method of claim 1, wherein the spreading of the photoresist is performed while rotating the active matrix at a speed of about 400 to 500 rpm, and adjusting the thickness of the photoresist is about 2500 to 3000 rpm. Method of manufacturing a thin film type optical path control device, characterized in that performed while rotating at a speed.