KR20000015580A - Circuit tape for semiconductor package - Google Patents

Circuit tape for semiconductor package Download PDF

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Publication number
KR20000015580A
KR20000015580A KR1019980035606A KR19980035606A KR20000015580A KR 20000015580 A KR20000015580 A KR 20000015580A KR 1019980035606 A KR1019980035606 A KR 1019980035606A KR 19980035606 A KR19980035606 A KR 19980035606A KR 20000015580 A KR20000015580 A KR 20000015580A
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KR
South Korea
Prior art keywords
dam
circuit pattern
layer
semiconductor package
circuit
Prior art date
Application number
KR1019980035606A
Other languages
Korean (ko)
Inventor
윤주훈
강대병
Original Assignee
김규현
아남반도체 주식회사
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Publication date
Application filed by 김규현, 아남반도체 주식회사 filed Critical 김규현
Priority to KR1019980035606A priority Critical patent/KR20000015580A/en
Priority to US09/387,377 priority patent/US6479887B1/en
Priority to JP24633599A priority patent/JP3208401B2/en
Publication of KR20000015580A publication Critical patent/KR20000015580A/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE: A circuit tape for semiconductor package is provided to prevent an inferiority of the semiconductor package by preventing glob top material from flowing to a solder ball land. CONSTITUTION: A polyimide layer(21) is formed and conductive circuit pattern(23) is formed on the polyimide layer(21). A cover coat layer(22) is laminated on the circuit pattern(23). A solder ball land(22a) for sticking a solder ball to the circuit pattern and a penetration hole(24) exposing a region where the wire is to be bonded are formed at the cover coat layer(22). A bond finger(23a) connected to the circuit pattern is formed out side of the penetration hole(24). And, a dam(6) is formed on the cover coat layer(22) for preventing glob top material from flowing, thereby preventing an inferiority of a semiconductor package.

Description

반도체 패키지용 써킷테이프Circuit tape for semiconductor package

본 발명은 반도체 패키지용 써킷테이프에 관한 것으로, 보다 상세하게 설명하면 와이어 등을 외부환경으로부터 보호하기 위한 액상봉지재가 솔더볼 랜드에 까지 흘러가는 것을 방지 및 억제할 수 있도록 된 반도체 패키지용 써킷테이프에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit tape for semiconductor packages. More particularly, the present invention relates to a circuit tape for semiconductor packages that can prevent and suppress a liquid encapsulant for protecting a wire from an external environment. will be.

일반적으로 전자 제품, 통신 기기, 컴퓨터 등 반도체 패키지가 실장되는 전자 제품들이 소형화되어 가고 있는 추세에 따라 반도체 패키지의 크기를 기능의 저하없이 소형화시키고, 고다핀을 구현하면서 경박단소화 하고자 하는 새로운 형태의 반도체 패키지(예를 들면, 반도체칩의 크기와 동일한 크기로 형성되는 칩 사이즈 패키지)가 개발되어 있다.In general, as electronic products, such as electronic products, communication devices, and computers, are being miniaturized, new types of semiconductor packages are being miniaturized without degrading their function and miniaturization while minimizing high size. A semiconductor package (for example, a chip size package formed to be the same size as that of a semiconductor chip) has been developed.

이러한 반도체 패키지는, 다수의 반도체칩이 형성되어 있는 웨이퍼상에 회로패턴이 형성되어 있는 써킷테이프를 접착시킨 채, 웨이퍼상에서 와이어본딩, 인캡슐레이션 및 솔더볼 융착을 마친 후, 마지막 단계에서 상기한 웨이퍼를 각각의 반도체칩으로 절단하여 독립된 반도체 패키지를 완성하는 방법에 의해 제조되는 것이 일반적이다.The semiconductor package is a wafer as described above in the last step after wire bonding, encapsulation and solder ball fusion are completed on the wafer while the circuit tape having the circuit pattern formed thereon is adhered to the wafer on which the semiconductor chips are formed. Is manufactured by a method of cutting an individual semiconductor chip into a separate semiconductor package.

상기한 반도체 패키지의 구조는 도 1에 도시된 바와 같이, 전자회로가 집적되어 있고, 이 전자회로의 신호를 외부로 인출하기 위한 입출력패드(1')가 형성된 반도체칩(1)과, 상기한 반도체칩(1)의 입출력패드(1')를 제외한 영역에 접착수단(2')에 의해 부착되며 폴리이미드층(21)위에 도전체 회로패턴(23)을 형성하고 그 회로패턴(23)의 상부에 카바코트층(Cover Coat Layer ; 22)을 라미네이션시키며, 상기한 카바코트층(22)에는 회로패턴(23)이 오픈되도록 솔더볼랜드(22a)가 형성되어 있는 써킷테이프(2)와, 상기 반도체칩(1)의 입출력패드(1')와 상기한 써킷테이프(2)의 회로패턴(23) 사이에 신호를 전달하기 위하여 연결된 와이어(3)와, 상기 와이어(3)가 본딩된 영역을 외부의 산화 및 부식으로부터 보호하기 위한 액상봉지재(4)와, 상기 와이어(3)에 의해 전달된 반도체칩(1)의 신호를 외부로 인출하기 위하여 상기한 써킷테이프(2)의 솔더볼랜드(22a)에 융착되는 솔더볼(5)로 이루어진다.As shown in FIG. 1, the structure of the semiconductor package includes a semiconductor chip 1 in which an electronic circuit is integrated, and an input / output pad 1 'for drawing out a signal of the electronic circuit to the outside is formed. The conductive circuit pattern 23 is formed on the polyimide layer 21 by the bonding means 2 'in the region excluding the input / output pad 1' of the semiconductor chip 1, and the A circuit tape (2) having a cover layer (22) formed thereon, and a solder ball land (22a) formed thereon so that the circuit pattern (23) is opened on the cover coat layer (22); In order to transmit a signal between the input / output pad 1 ′ of the semiconductor chip 1 and the circuit pattern 23 of the circuit tape 2, a wire 3 connected to the circuit pattern 23 and an area where the wire 3 is bonded are formed. Liquid encapsulant 4 to protect against external oxidation and corrosion, and a semiconductor chip 1 transferred by the wire 3 The solder ball 5 is fused to the solder ball land 22a of the circuit tape 2 in order to take out a signal of a).

여기서, 상기한 써킷테이프의 층(Layer) 구조는 통상 다층으로 형성된 것으로, 하층에 절연체로서 폴리이미드층(21)이 형성되어 있고, 이 폴리이미드층(21)의 상부에는 반도체칩(1)의 입출력패드(1')와 연결되어 반도체칩(1)의 신호를 전달하는 회로패턴(23)이 형성되어 있으며, 상기한 회로패턴(23) 위에는 상기 회로패턴(23)을 보호하도록 절연체인 카바코트층(22)이 라미네이션 되어 있다.Here, the above-described layer structure of the circuit tape is usually formed in a multilayer, and a polyimide layer 21 is formed on the lower layer as an insulator, and the semiconductor chip 1 is formed on the polyimide layer 21. A circuit pattern 23 is formed to be connected to the input / output pad 1 ′ and transmits a signal of the semiconductor chip 1, and the cover pattern is an insulator to protect the circuit pattern 23 on the circuit pattern 23. Layer 22 is laminated.

이러한 상기 써킷테이프(2)의 평면적인 양태는 도 2에 도시된 바와 같이, 반도체칩(1)과 대응하는 회로패턴(23)이 집합되어 대략 웨이퍼의 형태와 비슷하게 형성되어 있다.In the planar aspect of the circuit tape 2, as shown in FIG. 2, a circuit pattern 23 corresponding to the semiconductor chip 1 is assembled to form a shape substantially similar to that of a wafer.

한편, 상기한 써킷테이프(2)에는 와이어(3)가 본딩되는 영역이 오픈되는 관통공(24)이 형성되고, 이 관통공(24)은 상기한 반도체칩(1)의 입출력패드(1')와 와이어(3)를 매개체로 하여 연결될 수 있도록 본드핑거(23a)가 상기한 회로패턴(23)과 연결된다. 여기서, 상기한 본드핑거(23a)에는 와이어(3)와의 본딩력을 향상시키도록 금 또는 니켈이 도금되어 있다.On the other hand, the circuit tape 2 is formed with a through hole 24 through which the area where the wire 3 is bonded is formed, and the through hole 24 is an input / output pad 1 'of the semiconductor chip 1 described above. ) And the bond finger 23a are connected to the circuit pattern 23 so as to be connected via the wire 3. Here, the above-described bond finger 23a is plated with gold or nickel to improve the bonding force with the wire 3.

따라서, 상기한 관통공(24)을 통해 반도체칩(1)의 입출력패드(1')와 써킷테이프(2)의 본드핑거(23a)를 와이어(3)를 매개체로 하여 연결한 후에는 상기한 관통공(24)을 액상봉지재(4)로 덮어 씌움으로써, 외부의 산화 및 부식으로부터 보호한다.Therefore, after connecting the input / output pad 1 'of the semiconductor chip 1 and the bond finger 23a of the circuit tape 2 through the through hole 24 through the wire 3, By covering the through hole 24 with the liquid encapsulant 4, it protects against external oxidation and corrosion.

여기서, 상기한 액상봉지재(4)는 액상봉지재(Glob top material)를 이용하여 관통공(24)의 상부에서 인캡슐레이션(Encapsulation)하고, 상기 액상봉지재를 경화시키는 것에 의해 봉지를 완료한다. 따라서, 상기한 액상봉지재는 경화되기 전까지는 유동성이 있음으로써, 상기한 액상봉지재는 관통공(24)의 외측으로 흘러 넘치는 경우가 발생되고, 이와 같이 흘러 넘친 액상봉지재는 솔더볼랜드(22a)에 까지 영향을 미치는 경우가 발생되는 문제점이 있었다.Here, the liquid encapsulation material 4 is encapsulated in the upper portion of the through hole 24 using a liquid top material, and the encapsulation is completed by curing the liquid encapsulation material. do. Therefore, the liquid encapsulant is fluid until hardened, so that the liquid encapsulant flows outward through the through hole 24, and the liquid encapsulant overflowed in this way reaches the solder bores 22a. There was a problem that occurs when it affects.

상기와 같이 액상봉지재가 솔더볼랜드(22a)에 까지 흘러 넘치게 되면, 상기 솔더볼랜드(22a)에는 솔더볼(5)을 융착할 수 없게 되는 문제가 발생된다. 즉, 상기한 솔더볼랜드(22a)에 액상봉지재가 흘러 넘치게 되면 상기한 솔더볼랜드(22a)의 회로패턴(23)이 오픈되어 있는 것을 덮어 씌우게 됨으로, 솔더볼(5)을 융착시 상기한 솔더볼(5)과 회로패턴(23)과는 서로 연결되지 않음으로써, 반도체패키지의 불량이 발생되는 것이다.When the liquid encapsulant overflows to the solder ball land 22a as described above, a problem arises in that the solder ball 5 cannot be fused to the solder ball land 22a. That is, when the liquid encapsulant flows over the solder ball land 22a, the circuit pattern 23 of the solder ball land 22a is covered, so that the solder ball 5 is fused when the solder ball 5 is fused. 5) and the circuit pattern 23 are not connected to each other, a defect of the semiconductor package is generated.

이와 같이 액상봉지재가 흘러 넘치는 것을 방지하기 위한 방법으로서, 상기한 카바코트층(22)의 높이를 높게 형성하여 액상봉지재가 흘러 넘치는 것을 방지하도록 할 수 있으나, 이러한 방법으로는 상기한 카바코트층(22)에 형성되는 솔더볼랜드(22a)의 개구를 조절하기가 매우 난이하였다. 즉, 상기한 카바코트층(22)의 높이가 높게 되면, 상기한 솔더볼랜드(22a)의 깊이는 그 만큼 깊어지게 되고, 이로 인한 솔더볼랜드(22a)에 융착되는 솔더볼(5)의 높이를 제어하기 매우 어려운 단점이 있었다.As a method for preventing the liquid encapsulant from flowing in this way, the height of the carba coat layer 22 may be formed to be high to prevent the liquid encapsulant from flowing. It was very difficult to control the opening of the solder ball land 22a formed in 22). That is, when the height of the cover coat layer 22 is high, the depth of the solder ball land 22a is deepened by that, thereby controlling the height of the solder ball 5 fused to the solder ball land 22a. It was very difficult to do.

따라서, 상기한 액상봉지재가 흘러 넘치는 것을 방지하기 위해서는 상기한 써킷테이프(2)에 형성된 관통공(24)에 정확한 양 만큼 액상봉지재를 채우는 것이 가장 바람직하나, 이와 같이 액상봉지재의 양을 콘트롤하기는 불가능하다.Therefore, in order to prevent the liquid encapsulant from flowing over, it is most preferable to fill the liquid encapsulant by the exact amount in the through hole 24 formed in the circuit tape 2, but to control the amount of the liquid encapsulant as described above. Is impossible.

따라서 본 발명은 상기와 같은 종래의 문제점을 해결하기 위한 안출한 것으로, 와이어 등을 외부환경으로부터 보호하기 위한 액상봉지재가 솔더볼 랜드에까지 흘러가는 것을 방지 및 억제함으로서, 반도체패키지의 불량을 방지하도록 된 반도체 패키지용 써킷테이프를 제공함에 있다.Therefore, the present invention has been made to solve the above-mentioned conventional problems, by preventing and suppressing the flow of the liquid encapsulant to the solder ball land to protect the wire from the external environment, thereby preventing the semiconductor package defect It provides circuit tape for package.

도 1은 반도체 패키지의 구조를 나타낸 단면도1 is a cross-sectional view showing the structure of a semiconductor package

도 2는 반도체 패키지용 써킷테이프의 구조를 나타낸 평면도2 is a plan view showing the structure of a circuit tape for a semiconductor package

도 3은 본 발명의 제1 실시예에 따른 구조를 나타낸 단면도3 is a cross-sectional view showing a structure according to a first embodiment of the present invention;

도 4는 본 발명의 제2 실시예에 따른 구조를 나타낸 단면도4 is a cross-sectional view showing a structure according to a second embodiment of the present invention;

- 도면중 주요 부호에 대한 설명 --Description of the main symbols in the drawings-

2 - 써킷테이프 21 - 폴리이미드층2-Circuit Tape 21-Polyimide Layer

22 - 카바코트층(Cover coat Layer) 22a - 솔더볼랜드22-Cover coat Layer 22a-Solder Borland

23 - 회로패턴 23a - 본드핑거23-Circuit Pattern 23a-Bond Finger

24 - 관통공 6 - 댐24-through hole 6-dam

61 - 제1 댐 62 - 제2 댐61-First Dam 62-Second Dam

이하, 본 발명은 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 3은 본 발명의 제1 실시예에 따른 반도체 패키지의 댐 구조를 나타낸 것으로, 도시된 바와 같이 폴리이미드층(21)이 형성되고, 이 폴리이미드층(21) 위에 도전체 회로패턴(23)을 형성하며, 상기한 회로패턴(23)의 상부에는 카바코트층(22)을 라미네이션시키되, 상기한 카바코트층(22)에는 상기한 회로패턴(23)에 솔더볼(5)이 융착될 수 있도록 솔더볼랜드(22a)가 형성되며, 와이어(3)가 본딩되는 영역이 오픈되는 관통공(24)이 형성되고, 이 관통공(24)의 외측으로는 상기한 회로패턴(23)과 연결되는 본드핑거(23a)가 형성되며, 상기한 본드핑거(23a)의 외측으로는 카바코트층(22)의 상부에 액상봉지재가 흘러 넘치는 것을 방지하도록 댐(6)이 형성되어 있다3 illustrates a dam structure of a semiconductor package according to a first embodiment of the present invention. As illustrated, a polyimide layer 21 is formed, and a conductor circuit pattern 23 is formed on the polyimide layer 21. And a lamination of the carbacoat layer 22 on the circuit pattern 23, and the solder ball 5 to be fused to the circuit pattern 23 to the carbacoat layer 22. A solder ball land 22a is formed, and a through hole 24 is formed in which an area where the wire 3 is bonded is opened, and a bond connected to the circuit pattern 23 is formed outside the through hole 24. A finger 23a is formed, and a dam 6 is formed outside the bond finger 23a to prevent the liquid encapsulant from flowing over the cover layer 22.

이러한 댐(6)은 상기한 회로패턴(23) 위에 라미네이션되는 카바코트층(22)의 상부에 별도의 솔더마스크층을 접착하거나, 또는 비전도성 필름을 접착시켜서 형성할 수 있고, 또는 상기한 카바코트층(22)을 미리 댐(6)의 높이로 높게 형성한 상태에서 상기한 카바코트층(22)의 댐(6) 위치를 제외한 영역을 식각하여 형성할 수 있다. 즉, 상기한 댐(6)은 카바코트층(22)이 상부로 돌출되어 형성되어 있는 구성이다.The dam 6 may be formed by adhering a separate solder mask layer on top of the cover coat layer 22 laminated on the circuit pattern 23 or by attaching a non-conductive film, or the cover In the state in which the coat layer 22 is formed to be high at the height of the dam 6 in advance, the region except for the position of the dam 6 of the cover coat layer 22 may be etched. That is, the dam 6 is a structure in which the cover coat layer 22 protrudes upward.

도 4는 본 발명의 제2 실시예에 따른 반도체 패키지의 댐 구조를 나타낸 것으로, 그 구조는 본 발명의 제1 실시예와 유사하나, 상기한 댐(6)을 2열로 형성한 것이 특징이다. 즉, 상기한 댐(6)은 본드핑거(23a)의 외측으로 카바코트층(22)의 상부에 액상봉지재가 흘러 넘치는 것을 방지하도록 제1 댐(61)을 형성하고, 이 제1 댐(61)의 외측으로 다시 제2 댐(62)을 형성한 구성이다.FIG. 4 shows a dam structure of a semiconductor package according to a second embodiment of the present invention. The structure is similar to that of the first embodiment of the present invention, but the dam 6 is formed in two rows. That is, the dam 6 forms the first dam 61 so as to prevent the liquid encapsulant from flowing out of the upper portion of the cover coat layer 22 outside the bond finger 23a, and the first dam 61 is formed. 2nd dam 62 is formed in the outer side of ().

상기와 같이 댐(6)을 2열로 형성하면, 액상봉지재는 일차적으로 본드핑거(23a)의 외측으로 위치된 제1 댐(61)에 의해 흘러 넘치는 것이 방지되고, 만약 제1 댐(61)에서 액상봉지재가 흘러 넘치는 경우가 발생되면, 이를 제2 댐(62)에서 완전히 방지한다. 따라서, 액상봉지재(4)가 솔더볼랜드(22a) 까지 흘러 넘치는 일은 발생되지 않는다.When the dams 6 are formed in two rows as described above, the liquid encapsulant is prevented from overflowing by the first dam 61 located primarily outside the bond finger 23a, and in the first dam 61, If the liquid encapsulant overflows, it is completely prevented in the second dam 62. Therefore, the liquid sealing material 4 does not flow to the solder ball land 22a.

이와 같은 구조를 갖는 써킷테이프(2)를 이용한 본 발명의 반도체 패키지의 구조는 종래의 구조와 동일하다. 단, 본 발명에서의 써킷테이프(2)에 형성된 댐(6)에 의해 액상봉지재(4)가 솔더볼랜드(22a)로 흘러가는 것을 방지함으로써, 반도체패키지의 불량을 방지할 수 있다.The structure of the semiconductor package of the present invention using the circuit tape 2 having such a structure is the same as the conventional structure. However, by preventing the liquid encapsulant 4 from flowing into the solder bores 22a by the dam 6 formed in the circuit tape 2 in the present invention, defects in the semiconductor package can be prevented.

또한, 상기한 반도체 패키지는 고다핀을 실현하면서 경박단소화 한 것으로서, 반도체칩의 크기와 동일한 크기로 반도체패키지가 형성된다. 특히, 본 발명은 상기한 써킷테이프에 형성되는 관통공의 외측으로 댐을 형성하는 것에 의해 솔더볼랜드로 액상봉지재가 흘러가는 것을 방지하여 반도체패키지의 수율 및 신뢰성을 높일 수 있다.In addition, the semiconductor package described above is light and small in size while realizing high pins, and the semiconductor package is formed in the same size as that of the semiconductor chip. In particular, the present invention can prevent the liquid encapsulant from flowing to the solder ball land by forming a dam outside the through hole formed in the circuit tape, thereby increasing the yield and reliability of the semiconductor package.

이상의 설명에서와 같이 본 발명의 반도체 패키지용 써킷테이프에 의하면, 반도체 패키지에서 와이어 등을 외부환경으로부터 보호하기 위하여 덮어씌우는 액상봉지재가 솔더볼랜드에 까지 흘러가는 것을 방지 및 억제함으로서, 반도체패키지의 불량을 방지하고, 신뢰성을 향상시킬 수 있는 효과가 있다.According to the circuit tape for a semiconductor package of the present invention as described above, by preventing and suppressing the flow of the liquid encapsulation material to be covered to the solder borland in order to protect the wires and the like from the external environment in the semiconductor package, the defect of the semiconductor package is prevented It is effective in preventing and improving reliability.

Claims (4)

폴리이미드층이 형성되고, 이 폴리이미드층 위에 도전체 회로패턴을 형성하며, 상기한 회로패턴의 상부에는 카바코트층을 라미네이션시키되, 상기한 카바코트층에는 상기한 회로패턴에 솔더볼이 융착될 수 있도록 솔더볼랜드가 형성되며, 와이어가 본딩되는 영역이 오픈되는 관통공이 형성되고, 이 관통공의 외측에는 상기한 회로패턴과 연결되는 본드핑거가 형성되며, 상기한 본드핑거의 외측으로는 카바코트층의 상부에 액상봉지재가 흘러 넘치는 것을 방지하도록 댐이 형성되어 있는 것을 특징으로 하는 반도체 패키지용 써킷테이프.A polyimide layer is formed, and a conductor circuit pattern is formed on the polyimide layer, and a carbacoat layer is laminated on the circuit pattern, but solder balls are fused to the circuit pattern on the carbacoat layer. Solder ball land is formed so that the through-hole is formed to open the area to which the wire is bonded, a bond finger connected to the circuit pattern is formed on the outside of the through hole, the outer side of the bond finger is covered with a carbacoat layer The circuit tape for a semiconductor package, characterized in that the dam is formed to prevent the liquid encapsulant from flowing over the upper portion of the. 제 1 항에 있어서, 상기한 댐은 본드핑거의 외측으로 카바코트층의 상부에 액상봉지재가 흘러 넘치는 것을 방지하도록 제1 댐을 형성하고, 이 제1 댐의 외측으로 제2 댐을 형성하여서 된 것을 특징으로 하는 반도체 패키지용 써킷테이프.The method of claim 1, wherein the dam is formed by forming a first dam to prevent the liquid encapsulant from flowing out of the upper portion of the cover coat layer outside the bond finger, and by forming a second dam outside the first dam. The circuit tape for semiconductor packages characterized by the above-mentioned. 제 1 항 또는 제 2 항에 있어서, 상기한 댐은 카바코트층 위에 비전도성 필름이 접착되어 형성된 것을 특징으로 하는 반도체 패키지용 써킷테이프.The circuit tape for semiconductor packages according to claim 1 or 2, wherein the dam is formed by adhering a non-conductive film on the cover coat layer. 제 1 항 또는 제 2 항에 있어서, 상기한 댐은 카바코트층이 상부로 돌출되어 형성된 것을 특징으로 하는 반도체 패키지용 써킷테이프.The circuit tape for semiconductor packages according to claim 1 or 2, wherein the dam is formed by protruding a cover coat layer.
KR1019980035606A 1998-08-31 1998-08-31 Circuit tape for semiconductor package KR20000015580A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019980035606A KR20000015580A (en) 1998-08-31 1998-08-31 Circuit tape for semiconductor package
US09/387,377 US6479887B1 (en) 1998-08-31 1999-08-30 Circuit pattern tape for wafer-scale production of chip size semiconductor packages
JP24633599A JP3208401B2 (en) 1998-08-31 1999-08-31 Circuit pattern tape and semiconductor package using the same

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020069288A (en) * 2001-02-24 2002-08-30 삼성전자 주식회사 Semiconductor package using tape circuit board forming groove for preventing the encapsulant from overflowing and method for manufacturing thereof
KR100729081B1 (en) * 2000-12-29 2007-06-14 앰코 테크놀로지 코리아 주식회사 Semiconductor package and its Encapsulation method

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Publication number Priority date Publication date Assignee Title
JPH03283552A (en) * 1990-03-30 1991-12-13 Toshiba Lighting & Technol Corp Hybrid integrated circuit substrate
JPH0629427A (en) * 1991-12-24 1994-02-04 Sumitomo Bakelite Co Ltd Semiconductor mounting substrate
JPH09246315A (en) * 1996-03-12 1997-09-19 Sony Corp Semiconductor device and its manufacture
JPH09283659A (en) * 1996-04-12 1997-10-31 Nikko Co Ic package board and manufacture of ic package using the same
WO1998025301A1 (en) * 1996-12-02 1998-06-11 Minnesota Mining And Manufacturing Company Tab tape ball grid array package with vias laterally offset from solder ball bond sites
KR19990001899A (en) * 1997-06-18 1999-01-15 윤종용 Semiconductor chip package using flexible circuit board penetrating the center part

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03283552A (en) * 1990-03-30 1991-12-13 Toshiba Lighting & Technol Corp Hybrid integrated circuit substrate
JPH0629427A (en) * 1991-12-24 1994-02-04 Sumitomo Bakelite Co Ltd Semiconductor mounting substrate
JPH09246315A (en) * 1996-03-12 1997-09-19 Sony Corp Semiconductor device and its manufacture
JPH09283659A (en) * 1996-04-12 1997-10-31 Nikko Co Ic package board and manufacture of ic package using the same
WO1998025301A1 (en) * 1996-12-02 1998-06-11 Minnesota Mining And Manufacturing Company Tab tape ball grid array package with vias laterally offset from solder ball bond sites
KR19990001899A (en) * 1997-06-18 1999-01-15 윤종용 Semiconductor chip package using flexible circuit board penetrating the center part

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100729081B1 (en) * 2000-12-29 2007-06-14 앰코 테크놀로지 코리아 주식회사 Semiconductor package and its Encapsulation method
KR20020069288A (en) * 2001-02-24 2002-08-30 삼성전자 주식회사 Semiconductor package using tape circuit board forming groove for preventing the encapsulant from overflowing and method for manufacturing thereof

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