KR20000012969A - Spreading signal generator of cdma communication system and spreading signal generation method - Google Patents

Abstract

PURPOSE: Diffusion sequence generator and method in CDMA communication system are provided to produce various kinds of spreading codes, and reduces PAR without a deterioration of BER performance. CONSTITUTION: A spreading signal generation method of CDMA communication system generates PN code having PNi and PNq, performs QPSK phase transition about previous spreading signals(Ci,Cq) after receiving the PN code, performs +90°C phase transition or -90°C phase transition, performs 180°C phase transition or 0°C phase transition. After that, the method selectively outputs the phase transition spreading signal according to a predetermined order. Thereby, the method reduces PAR without a deterioration of BER performance.

Description

Spreading Signal Generator and Method for Code Division Multiple Access Communication System

The present invention relates to a spread spectrum device and method in a communication system using a code division multiple access scheme, and more particularly, to a spread sequence generator and a method.

In general, the code division multiple access (hereinafter referred to as CDMA) mobile communication system has been developed from the mobile communication standard, which mainly focuses on voice, and has been developed to the IMT-2000 standard capable of transmitting high speed data as well as voice. It came to the following. In the IMT-2000 standard, services such as high quality voice, moving picture, and internet search are possible. In the CDMA mobile communication system, a communication line existing between a terminal and a base station is largely divided into a reverse link from the terminal to the base station as opposed to a forward link from the base station to the terminal.

PN (Psuedo Noise) complex spreading scheme (PN Complex Spreading Scheme) is widely known as a method for spread spectrum in the reverse link of the CDMA communication system. However, the PN complex diffusion method has a problem in that a peak-to-average power ratio (hereinafter referred to as PAR) increases at the output of a power amplifier according to user data. In other words, when the peak power to average power ratio of the transmission power in the reverse link increases, re-growth occurs, and it has a great influence on the design and performance of the power amplifier of the terminal. In the characteristic curve of the terminal power amplifier, there are a linear section and a non-linear section. When the power of the terminal is increased, the transmission signal of the terminal is spread over the non-linear section, which disturbs the frequency domain of other users. It is called. Therefore, in order not to disturb the frequency range of another user, the cell area is made small, and the terminal in the cell area should transmit a signal to a corresponding base station with low transmission power. Therefore, it is necessary to use a spreading method that reduces PAR while minimizing degradation of bit error rate (BER), which is one of overall system performances.

In order to examine the PN complex diffusion method, a transmitter configuration of a conventional CDMA communication system will be described. 1 is a diagram illustrating a structure of a reverse link channel transmitter of a CDMA communication system.

Referring to FIG. 1, data to be transmitted is subjected to channel coding, repeating, and channel interleaving, and 0 is +1, 1 is -1, and binary mapping is input to each channel data. do. The data of each channel as described above is multiplied by an orthogonal code in the multipliers 111, 121, 131, and 141 to separate each channel. In FIG. 1, each channel transmitter shows an example of channel transmitters such as a pilot channel, a control channel, a supplemental channel, and a fundamental channel. Therefore, the orthogonal codes may use a Walsh code as a code for distinguishing the respective channels. The control channel, the additional channel, and the basic channel data among the orthogonal coded channel data as described above are multiplied by a gain suitable for each channel in the first to third gain adjusters 122, 132, and 142.

The data of each channel thus produced are summed by binary adders 112 and 133, and then spread by a complex multiplier 100. The complex multiplier 100 multiplies the transmission signal by a spreading code to perform spread spectrum. It is assumed here that the spreading code is a PN code. The PN code used as the input of the complex multiplier 100 may have a rate of a chip rate and a value of +1 or -1. The real part of the output data signals of the binary adders 114 and 135 is input to the first low pass filter 115 and the imaginary part is input to the second low pass filter 136. The signals passing through the low pass filters 115 and 136 are modulated by the third and fourth gain adjusters 116 and 137 and then modulated and transmitted to the channel. Until now, various methods have been proposed for reducing the PAR of the signal passing through the first and second low pass filters 115 and 136, and they are used to generate the spread codes C _I and C _Q in the complex multiplier 100. It is focused.

In general, the PAR is a zero-crossing phenomenon caused by simultaneously changing codes of the spreading codes C _I and C _Q of FIG. 1 complex multiplier 100, and the sign of the spreading code does not change. Due to the hold phenomenon, the performance decreases. Therefore, in the CDMA communication system, there is a problem in that the PAR increases according to spreading codes C _I and C _Q when spreading the bandwidth.

Accordingly, an object of the present invention is to provide a spread spectrum device and method capable of reducing PAR without degrading BER performance in a code division multiple access communication system.

Another object of the present invention is to provide an apparatus and method for generating a spreading code by combining QPSK, π / 2-DPSK, and zero crossing or hold in a spread spectrum device of a code division multiple access communication system.

Another object of the present invention is to perform QPSK first, then π / 2-DPSK, and then zero crossing or hold for spreading in a spread spectrum apparatus of a code division multiple access communication system. Next, an apparatus and method for generating a spreading code with π / 2-DPSK are provided.

It is still another object of the present invention to provide an apparatus and method for performing spreading in a spreading code in a spread spectrum device of a code division multiple access communication system, first performing a zero crossing, and then generating a spreading code with [pi] / 2-DPSK. .

In the method for generating a spreading signal in a code division multiple access communication system according to an embodiment of the present invention, a process of generating a PN code having PNi and PNq, and a previous spread signal (Ci) , QqK phase shift, ± 90 degree phase shift, 180 degree phase shift or 0 degree phase shift, and the process of selectively outputting the phase shifted spread signal in a predetermined order. It features.

In addition, a method for generating a spreading signal of a code division multiple access communication apparatus according to an embodiment of the present invention for achieving the above object comprises the first step of continuously generating a PN code sequence having PNi and PNq in a chip period; A second process of shifting the phases Ci and Cq of the previous spread signal by a first phase shift by inputting values of the first chip period of PNi and PNq, and outputting the second process Ci, in the next chip period And a third process of outputting Cq) by the second phase shift.

1 is a diagram illustrating a structure of a reverse link channel transmitter of a code division multiple access mobile communication system.

2 to 5 are diagrams for explaining a basic state transition during QPSK and DPSK spreading

6 is a diagram illustrating an example of a configuration for generating a zero crossing spreading sequence;

7 illustrates another configuration example for generating a zero crossing spreading sequence.

8 is a diagram showing a configuration example for generating a hold spreading sequence;

9 is π / 2 A diagram showing a configuration example for generating a DPSK spreading sequence

10 is π / 2 A diagram showing another configuration example for generating a DPSK spreading sequence

11 to 15 are diagrams for explaining the extended state transition of the basic state transition of FIGS.

16 is a diagram showing an example of a configuration for generating a zero crossing or hold spreading sequence;

17 is a diagram showing another configuration example for generating a zero crossing or hold spreading sequence;

18 is zero crossing or π / 2 A diagram showing a configuration example for generating a DPSK spreading sequence

19 is zero crossing or π / 2 A diagram showing another configuration example for generating a DPSK spreading sequence

20 is hold or π / 2 A diagram showing a configuration example for generating a DPSK spreading sequence

21 is Hold or π / 2 A diagram showing another configuration example for generating a DPSK spreading sequence

22 is π / 2 Diagram showing a block diagram for generating a DPSK spreading sequence

23 uses a retarder π / 2 Diagram showing a block diagram for generating a DPSK spreading sequence

Fig. 24 is a diagram showing a configuration example for generating a diffusion sequence according to the first embodiment of the present invention.

25-A illustrates another configuration for generating a spreading sequence according to the first embodiment of the present invention.

Fig. 25-B shows an example of symbol change in the time axis for the decimator output of Fig. 25-A.

FIG. 26 is a diagram showing another configuration of generating a diffusion sequence according to the first embodiment of the present invention. FIG.

Fig. 26-B shows an example of symbol change on the time axis for the decimator output of Fig. 26-A.

27 shows another configuration for generating a spreading sequence according to the second embodiment of the present invention.

FIG. 28 shows yet another configuration for generating a diffusion sequence according to the second embodiment of the present invention. FIG.

29 is a diagram showing another configuration for generating a diffusion sequence according to the third embodiment of the present invention.

30 is in accordance with the embodiment of FIG. 9 of the present invention. π / 2 Showing computer simulated results for generating a DPSK diffusion sequence.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In describing the present invention, when it is determined that the detailed description of the related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

In general, a PAR is a zero-crossing phenomenon caused by simultaneously changing the codes of the spreading codes C _I and C _Q of FIG. 1 complex multiplier 100, and a hold that does not change the sign of the spreading code. (Hold) causes a performance degradation. For example, the ZC refers to a transition to the third quadrant when the initial state is one quadrant, and the phase change at this time is π Becomes Hold is, for example, a transition that stays in one quadrant when the initial state is one quadrant. In the following description, ZC and Hold are used for this concept. On the other hand, the conventional QPSK spreading method has a transition path in which the state transition of the spreading code generated according to the value of the PN code is possible from one quadrant to two quadrants, three quadrants, and four quadrants.

The characteristics of the state transition can be more clearly understood by the following description. For ease of explanation, the initial state is set to be located in the first quadrant. 2-5 illustrate primitive state transitions. 2 shows zero crossing, FIG. 3 shows hold, and FIG. 4 shows + π / 2 -DPSK, Figure 5 -π / 2 -Represents DPSK. This state transition can be implemented in several ways.

6 is a diagram illustrating an example of a configuration for generating a zero crossing diffusion sequence.

Referring to FIG. 6, the delay unit 211 delays the output spread code C _i , and the multiplier 212 multiplies the output of the delay unit 211 by -1 to invert the sign of the previous spread code C _i . The delayer 221 delays the output spreading code C _q , and the multiplier 222 multiplies the output of the delayer 221 by -1 to invert the sign of the previous spreading code C _q . In the above description, multiplying by -1 means inverting the sign, and multiplying by 1 means no inversion of the sign. In the figure showing a configuration example, the position of the sign inverter for inverting the sign may be changed within a range not obscure the subject matter of the present invention. Alternatively, the sign inverter may be used for the output of the control signal as another method for inverting the sign. The control signal may have a chip period and is a device that sequentially outputs a value of 1 or -1. In the following description, multiplying by -1 or 1 has the same meaning as described above. In FIG. 6, delays 211 and 221 respectively store a previous spreading code, C _i represents a real part, and C _q represents an imaginary part. Therefore, if the previous spreading code output was assumed to be one quadrant (1,1), then the current output is the output of three quadrants (-1, -1). In addition, assuming that the previous output was a quadrant (-1, 1), the current output is an output (1, -1) of the quadrant 4.

7 is a diagram illustrating another configuration example of generating the zero crossing diffusion sequence. The spreading codes C _i and C _q generated at this time are zero-crossed by the method shown in FIG. 6. Assuming that the initial orthogonal code 1 is +1 and the orthogonal code 2 is -1, the outputs C _i and C _q of the multipliers 212 and 222 are (-1,1) and are present in the second quadrant. Since orthogonal code 1 is -1 and orthogonal code 2 is +1, the outputs of multipliers 212 and 222 are (+ 1, -1) and are present in the fourth quadrant. Therefore, zero crossing occurs.

8 illustrates an embodiment of implementing a method for hold state transition. Referring to FIG. 8, the delay unit 231 delays the output spread code C _i , and the multiplier 232 multiplies the output of the delay unit 231 by 1 to maintain the sign of the previous spread code C _i . The delayer 241 delays the output spreading code C _q , and the multiplier 242 multiplies the output of the delayer 241 by 1 to maintain the sign of the previous spreading code C _q . Therefore, if the previous spreading code output was assumed to be one quadrant (1, 1), the current spreading code output is also the output of one quadrant (1,1). If the previous spreading code output was assumed to be two quadrants (-1, 1), then the current spreading code output is also an output of two quadrants (-1, 1).

Meanwhile, FIGS. 4 and 5 π / 2 The DPSK state transition has a transition path from the first quadrant to the second or fourth quadrant, assuming that the initial state is the first quadrant. ± π / 2 ZC and hold do not occur.

9 is the above π / 2 A diagram showing a configuration example for generating a DPSK spreading sequence. Referring to FIG. 9, the delay unit 251 delays the output spread code C _i , and the multiplier 252 inverts the sign of the previous spreading code C _q by multiplying the output of the delay unit 261 by −1. Delay 261 also delays the output spreading code C _q . The multiplier 253 multiplies the output of the multiplier 252 by the control signal (1 or -1) and outputs the spread code C _i , and the multiplier 263 multiplies the output of the multiplier 262 by the control signal (1 or -1). Output as _q If the previous state is assumed to be (1,1), which is the value of the first quadrant, the current value has only the value of the second quadrant (-1,1) or the value of the fourth quadrant (1, -1). This is explained in terms of phase change as described above. + π / 2 or -π / 2 It can be seen that there is a phase change. And this state transition is affected by the previous state. That is, if the previous state is the value of the second quadrant (-1,1), the current state is the value of the first quadrant (1,1) or the value of the third quadrant (-1, -1). remind π / 2 -DPSK state transition can be easily implemented by changing the real and imaginary parts in the previous state and changing the sign of the real part. On this principle π / 2 An embodiment implemented by the DPSK state transition is illustrated in FIG. 9. In FIG. 9, when the control signal is 1 + π / 2 If the phase change appears and the control signal is -1 -π / 2 Phase change appears.

FIG. 10 illustrates another embodiment of the same method as the embodiment of FIG. 9 using orthogonal codes. Assuming that the PN codes are +1, -1, -1, +1, -1, initial orthogonal code 1 is +1, and orthogonal code 2 is +1, the output of multiplier 253 (C _i , C _q ) is +1, -1, -1, +1, -1, and the output of the multiplier 263 is +1, +1, -1, -1, -1. Therefore, if we combine the outputs (C _i , C _q ) of multipliers 253 and 263 (+ 1, + 1), (-1, + 1), (-1, -1), (+ 1, -1), ( -1, -1), and the transition state of the spreading code is shifted to one quadrant, two quadrants, three quadrants, four quadrants, and three quadrants. ± π / 2 Phase change appears.

ZC, Hold and π / 2 Another state transition can be obtained by extending the DPSK concept. 11, 12, 13, 14, and 15 are diagrams illustrating such an extended state transition. 11 is π / 2 12 is a diagram illustrating a DPSK state transition, and FIG. 12 is a diagram illustrating a zero-crossing ZC or a state transition of a hold (hereinafter referred to as ZCH), and FIG. 13 is a ZC or π / 2 A diagram illustrating a DPSK state transition, and FIG. 14 is a hold or π / 2 -DPSK state transition diagram, FIG. 15 is ZCH or π / 2 A diagram illustrating a DPSK state transition.

16 is a diagram illustrating an example of a configuration for generating a zero crossing or hold diffusion sequence. The zero crossing "or" hold means that the state transition is repeated from the first state to the second state or from the second state to the first state when the first state is zero crossing and the second state is hold. In the following description of the configuration examples of the present invention "or" is used in the above meaning. Referring to FIG. 16, the delay unit 281 delays the output spread code C _i , and the multiplier 282 multiplies the output of the delay unit 281 by the control signal 1 or −1 and outputs the spread code C _i . In addition, the delay unit 291 delays the output spread code C _q , and the multiplier 292 multiplies the output of the delay unit 291 by the control signal (1 or -1) and outputs the spread code C _q . The spreading code generator having the structure as shown in FIG. 16 assumes that the initial state is the value (1,1) of the first quadrant, but remains in the previous state or transitions to the third quadrant (-1, -1). It is a way. If it is assumed that the value of the control signal 301 is 1, FIG. 16 is exactly the same as the hold structure of FIG. Also, if it is assumed that the value of the control signal 301 is -1, FIG. 16 is exactly the same as the ZC structure of FIG. In other words, the above-described method is a combination of ZC and hold.

FIG. 17 is a diagram showing another configuration example for generating the zero crossing or hold spreading sequence using an orthogonal code. Assuming that the PN codes are +1, -1, -1, +1, -1, initial orthogonal code 1 is +1, and orthogonal code 2 is -1, the output of multiplier 282 (C _i , C _q ) is +1, +1, -1, -1, -1, and the output of the multiplier 292 is -1, -1, +1, +1, +1. Therefore, when we combine the outputs (C _i , C _q ) of multipliers 282 and 292, (+ 1, -1), (+ 1, -1), (-1, + 1), (-1, + 1), ( -1, +1), and the transition state of the spreading code is shifted to quadrant 4, quadrant 4, quadrant 2, quadrant 2, quadrant 2, and hold or zero crossing ( ± 3π / 2 Phase change appears.

18 is zero crossing or π / 2 A diagram showing a configuration example for generating a DPSK spreading sequence.

Referring to FIG. 18, the delay unit 311 delays the output spread code C _i . Delay 321 delays the previous spreading code C _q that is output. The multiplier 313 inverts the sign by multiplying the delayed previous spreading code C _i output from the delayer 311 by -1. The multiplier 315 multiplies the control signal (1 or -1) 332 by -1 to invert the control signal 332. The multiplier 314 multiplies the previous spreading code C _q outputted from the delayer 321 by the output of the multiplier 315. The first selector 312 inputs the output of the multiplier 313 as the first signal A, inputs the output of the multiplier 314 as the second signal B, and selects a corresponding signal among the signals A and B input under the control of the control device 331. Output The multiplier 323 multiplies the output of the multiplier 315 by the previous spreading code C _i output from the delay unit 311. The multiplier 324 multiplies the previous spreading code C _q output from the delayer 321 by -1 and outputs the result. The second selector 322 inputs the output of the multiplier 323 as the second signal B, inputs the output of the multiplier 324 as the first signal A, and outputs a corresponding signal among the signals A and B input under the control of the controller 331. Selective output. 18 illustrates a case in which the transition state of the ZC state to the third quadrant is assumed when the previous state is called the first quadrant, or + π / 2 Change the phase to transition to two quadrants, -π / 2 It shows the case of state transition to 4 quadrants by changing phase. In FIG. 18, if the controller 331 selects the signal A, the output is ZC while inverting all previous outputs. If the controller 331 selects the signal B, the output is basically π / 2 -DPSK state transition is performed. If the value of control signal 332 is 1, the previous output phase + π / 2 If the control signal 332 is -1, the previous output phase is changed. -π / 2 Phase change is made. ZC of FIG. 18 or π / 2 DPSK state transition is ZC or + π / 2 DPSK and ZC or -π / 2 It can be divided into two kinds of DPSK. That is, the ZC or π / 2 Combination of DPSK state transition should control both control device 331 and control signal 332, but if control signal 332 is always 1, ZC or + π / 2 If it operates with -DPSK and the value of control signal 1841 is always -1, ZC or -π / 2 Operate with DPSK.

19 is zero crossing or π / 2 A diagram showing another configuration example for generating a DPSK spreading sequence. Assuming that the PN codes are +1, -1, -1, +1, +1, -1, initial orthogonal code 1 is -1, and orthogonal code 2 is +1, C _i is -1, +1, -1, +1, -1, +1, and the output C _q of the multiplier 341 becomes +1, +1, -1, -1, +1, +1. Therefore, if you sum the outputs (C _i , C _q ), (-1, + 1), (+ 1, + 1), (-1, -1), (+ 1, -1), (-1, -1 ), The transition state of the spreading code is shifted into quadrants, quadrants, quadrants, quadrants, and quadrants. ± π / 2 Phase change appears.

20 is hold or π / 2 A diagram showing a configuration example for generating a DPSK spreading sequence. Referring to FIG. 20, delay 351 delays the previous spread code C _i output. Delay 361 delays the previous spreading code C _q that is output. The multiplier 353 multiplies the delayed previous spreading code C _i output from the delayer 351 by one. The multiplier 355 multiplies the control signal (1 or -1) 372 by -1 to invert the control signal 372. The multiplier 354 multiplies the output of the multiplier 355 by the previous spreading code C _q output from the delay unit 361 and outputs the multiplier 355. The first selector 352 inputs the output of the multiplier 353 as the first signal A, inputs the output of the multiplier 354 as the second signal B, and selects a corresponding signal among the signals A and B input under the control of the control device 371. Output The multiplier 363 multiplies the output of the multiplier 355 by the previous spreading code C _i output from the delay unit 351 and outputs the multiplier. The multiplier 364 multiplies the previous spreading code C _q output from the delay 361 by 1 and outputs the multiplier 1. The second selector 362 inputs the output of the multiplier 363 as the second signal B, inputs the output of the multiplier 364 as the first signal A, and outputs a corresponding signal among the signals A and B input under the control of the controller 371. Selective output. FIG. 20 is a case where the previous state is called a quadrant and the ZC state transition to the third quadrant is performed. + π / 2 Change the phase to transition to two quadrants, -π / 2 It shows the case of state transition to 4 quadrants by changing phase. In FIG. 20, when the control device 371 selects the signal A, the output is held to output the previous output as it is, and when the control device 371 selects the signal B, basically π / 2 -DPSK state transition is performed. If the value of control signal 372 is 1, the previous output phase + π / 2 If the control signal 372 is -1, the previous output phase is changed. -π / 2 Phase change is made. Hold of FIG. 20 or π / 2 DPSK state transition is hold or + π / 2 DPSK and hold or -π / 2 It can be divided into two kinds of DPSK. That is, the hold or π / 2 The combination of DPSK state transitions should control both control device 371 and control signal 372, but if the value of control signal 372 is always 1, then hold or + π / 2 -DPSK, and if the value of control signal 372 is always -1, hold or -π / 2 Operate with DPSK.

21 is held or orthogonal code using π / 2 A diagram showing another configuration example for generating a DPSK spreading sequence. Assuming that the PN codes are +1, -1, -1, +1, +1, -1, initial orthogonal code 1 is -1, and orthogonal code 2 is +1, C _i is +1, +1, +1, +1, +1, +1, and the output C _q of the multiplier 341 is +1, +1, -1, -1, +1, +1. Therefore, if you sum the outputs (C _i , C _q ), (+ 1, + 1), (+ 1, + 1), (+ 1, -1), (+ 1, -1), (+ 1, -1 ), The transition state of the spreading code is shifted to one quadrant, one quadrant, four quadrants, four quadrants, and four quadrants to hold or ( ± π / 2 Phase change appears.

Meanwhile, ZCH of FIG. 15 or π / 2 The DPSK state transition assumes that if the previous state is assumed to be the first quadrant value (1,1), then the current state is the first quadrant value (1,1), the second quadrant value (-1,1), and the third quadrant. Value (-1, -1) or the quadrant value (1, -1). This has the memoryless nature that transitions to the current state can occur in all quadrants, regardless of the value of the previous state. This is a conventional QPSK diffusion method.

A spreading code having various characteristics can be made by generating a spreading code by inputting a PN code using the state transition methods. That is, by combining the state transition method can be made a diffusion method excellent in the PAR and BER characteristics. For example, QPSK-ZCH, ZCH-QPSK, ZCH- π / 2 -DPSK, π / 2 DPSK-ZCH, QPSK π / 2 -DPSK -ZCH- π / 2 -DPSK, QPSK- π / 2 -DPSK -QPSK-ZCH, QPSK-ZCH-QPSK- π / 2 You can also make a spreading code by DPSK, etc. These various methods vary slightly depending on the orthogonal code used by the PAR and BER characteristics, the degree of multiple access interference (hereinafter referred to as MAI), and the number of channels per user on the reverse link. It may be appropriately selected.

22 is π / 2 -DPSK spreading code generation block diagram. Referring to FIG. 22, the phase mapping unit 411 generates C ₁ and C ₂ codes by mapping phases of a PN _I code. The level converter 415 converts and outputs the level of the PN _Q code. The multiplier 412 multiplies the C ₁ code output from the phase mapping unit 411 and the level-converted PN _Q code and outputs the C _i code. The multiplier 413 multiplies the C ₂ code output from the phase mapping unit 411 and the level-converted PN _Q code, and the multiplier 414 multiplies the output of the multiplier 413 by an imaginary j and outputs the C _q code. Same as FIG. 22 above π / 2 In the process of generating the DPSK spreading code, the odd index of the input signal PN _I becomes (C ₁ = +1, C ₂ = +1) or (C ₁ = -1, C ₂ = -1), and the even number is In the index, (C ₁ = +1, C ₂ = -1) or (C ₁ = -1, C ₂ = +1), or the opposite of this input signal, the phase change of the spreading code ± π / 2 Limited to 22, PN _I and PN _Q have a value of 0 or 1, and C ₁ and C ₂ are outputs of the phase mapping unit 411 having a value of 1 or -1. The level converter 415 outputs 1-2 * (input values) and has a value of 1 or -1. The phase mapping unit 411 changes the phase change of the spreading code. ± π / 2 It serves to limit. For example, if the input signal PN _I is 0, the previous phase + π / 2 On the contrary, if PN _I equals 1, -π / 2 Transition to

23 uses a retarder π / 2 23 illustrates a block diagram for generating a DPSK spreading sequence. Referring to FIG. 23, the multiplier 451 multiplies the PN _I code by the output of the delay unit 452, and the delay unit 452 outputs the output of the multiplier 451. The delay is applied to the multiplier 451. A multiplier 454 multiplies the PN _I code by -1, and a multiplier 455 multiplies the PN _I code by the output of the delay unit 456, and the delay unit 456 delays the output of the multiplier 455 and applies it to the multiplier 455. . A multiplier 453 multiplies the output of the multiplier 451 by a PN _Q code to generate a C _i code, and a multiplier 457 multiplies the output of the multiplier 455 by a PN _Q code to generate a C _q code. Referring to the operation of generating a spreading code with the configuration as shown in FIG. 23, suppose that PN _I is 1 and PN _Q is 1. FIG. At this time, 1 and -1 are output to the spreading codes C _i and C _q , respectively. It has a phase of four quadrants as (1, -1). If PN _Q is -1, the spreading code outputs two quadrant values (-1,1). Depending on the next PN _I and PN _Q values, the output is always output in the first quadrant (1,1) or the third quadrant (-1, -1). In this way, once the phase of the spreading code is one quadrant or three quadrants, the second quadrant or four quadrants are output, so there is no ZC or hold in the phase change of the spreading code.

24 is a quadrature phase shift keying (QPSK) of the present invention; π / 2 -A diagram showing an embodiment of a method for generating a spreading code by combining DPSK and zero crossing or hold (hereinafter referred to as ZCH). In FIG. 24, signal A represents a signal of QPSK from which signals of PN _I and PN _Q are output as they are, and signals B and D are π / 2 -Represents DPSK, and signal C represents ZCH. Referring to FIG. 24, the delay unit 511 delays the output spread code C _i . Delay 521 delays the output previous spreading code C _q . The multiplier 513 multiplies the PN _I code by the previous spreading code C _i output from the delay unit 511 and outputs the multiplier. The multiplier 515 multiplies the PN _Q code by -1 to invert the PN _Q code. The multiplier 514 multiplies the output of the multiplier 515 by the previous spreading code C _q output from the delay unit 521 and outputs the multiplier 515. The first selector 512 inputs the PN _I code as the first signal A, inputs the output of the multiplier 513 as the third signal C, inputs the output of the multiplier 514 as the second signal B and the fourth signal D, and controls. The signal A, B, C, or D input under the control of the device 531 selects and outputs a corresponding signal. The multiplier 523 multiplies the PN _I code by the previous spreading code C _q output from the delay unit 521 and outputs the multiplier. The multiplier 524 multiplies the PN _Q code by the previous spreading code C _i output from the delay unit 511 and outputs the multiplier. The second selector 522 inputs the PN _Q code as the first signal A, inputs the output of the multiplier 523 as the third signal C, inputs the output of the multiplier 524 as the second signal B and the fourth signal D, and controls. The signal A, B, C, or D input under the control of the device 531 selects and outputs a corresponding signal. Here, the first signal A is a QPSK signal in which the signals of PN _I and PN _Q are output as they are, the second signal B is a signal in a zero crossing or hold state, and the second signal B and the third signal D are π / 2- DPSK signal. Referring to the operation of generating the spreading code in the configuration as shown in FIG. 24, the control device 531 controls the first and second selectors 512 and 522 to sequentially select the signals A, B, C, and D in a predetermined order. . QPSK, ZC, π / 2 The combination of DPSK and hold methods can be used to create a variety of diffusion methods with minimal BER degradation and low PAR. For example, QPSK- π / 2 -DPSK-ZCH- π / 2 Hold, first diffusion method using DPSK (hereinafter referred to as QDZD) in order π / 2 Second diffusion method and ZC using DPSK π / 2 There may be a third diffusion method using a DPSK. Also the QPSK, ZC, π / 2 A diffusion method produced by combining the first, second and third diffusion methods as well as the method of DPSK and hold may also be used. The method can be implemented through the following examples.

First, a generation code generation operation according to the first embodiment QDZD of FIG. 24 will be described. The method of the first embodiment of the present invention first outputs the values of PN _I and PN _Q input as they are, so in the quadrant (1,1), (1, -1), (-1,1), (-1, -1) QPSK, which is one of the following values, then the phase at the previous output ± π / 2 Changing π / 2 -DSPK, followed by ZCH, which also outputs the same value at the previous output, or both signs, and finally ± π / 2 Run the DSPK. This can be operated by sequentially repetitively selecting signals A, B, C and D in the selection of the first selector 512 and the second selector 522. The PN _I and PN _Q codes of FIG. 24 may be the same as those used in the conventional PN spreading code. On the other hand, let's look at the case of another state transition using the configuration example of FIG. First, the QPSK-ZCH can operate by sequentially repeating the signals A and C in the selection of the first selector 512 and the second selector 522, and the ZCH-QPSK is used to select the first selector 512 and the second selector 522. It is possible to operate by sequentially selecting the signals C and A in sequence. In the operation description of the present invention, it is assumed that the same spreading codes are generated when the output sequence of the spreading codes is different from the starting order, that is, the time delay during one chip period, such as the QPSK-ZCH and the ZCH-QPSK. ZCH- π / 2 DPSK (or π / 2 DPSK-ZCH) may operate by sequentially repeating signal C and signal B (or signal B and signal C) in the selection of the first selector 512 and the second selector 522. π / 2 -DPSK -ZCH- π / 2 DPSK can be operated by sequentially repetitively selecting signals A, B, C and D in the selection of the first selector 512 and the second selector 522. π / 2 DPSK-QPSK-ZCH π / 2 DPSK can be operated by sequentially repetitively selecting signal B, signal A, signal C, and signal D in the selection of the first selector 512 and the second selector 522. π / 2 -ZCH-QPSK- π / 2 The DPSK can operate by sequentially repeating the signal A, the signal C, the signal A, and the signal B in the selection of the first selector 512 and the second selector 522. To implement the spreading method of FIG. 24 requires a very complex hardware device. However, the first embodiment can be represented in the same manner and in a very simple structure.

25-A is a diagram showing another configuration of generating a diffusion sequence according to the first embodiment (QDZD) of the present invention. Referring to FIG. 25-A, the decimator 611 4-decimates and outputs the PN ₁ code, and the decimator 621 4-decimates and outputs the PN ₂ code. In the following description of the present invention, decimation means that the decimated symbol has the same value for a predetermined chip period. The output of the decimator can be more clearly understood by the following description.

Fig. 25-B shows an example of symbol change in the time axis for the decimation. 25-B shows the result of 4-decimation when PN ₁ is +1 in the decimator 611 of FIG. 25-A, and 621 of FIG. 25-B shows the decimator 621 of FIG. 25-A. When PN ₂ is -1, the result of 4-decimation is shown. The multiplier 613 of FIG. 25-A multiplies the output of the multiplier 612 and the PN ₃ code and outputs the spread code C _i . The multiplier 623 multiplies the output of the multiplier 622 and the PN ₃ code and outputs the spread code C _q . Referring to the operation of generating the spreading code in the configuration as shown in FIG. 25-A, the PN ₁ and PN ₂ codes are decimated in the 4-decimators 611 and 621 and then multiplied by the orthogonal codes in the multipliers 612 and 622. The multipliers 613 and 623 then multiply with another PN ₃ code and output the final spreading codes C _I and C _Q. At this time, once the PN ₁ and PN ₂ codes are determined, they are maintained for 4 chips. The PN ₁ and PN ₂ codes output from the decimators 611 and 621 are multiplied by the orthogonal codes corresponding to the multipliers 612 and 622, respectively. At this time, the first chip time is the QPSK method. In the second chip time, assuming that the previous chip time output is (1,1) of the first quadrant, it is the value of the second quadrant (-1,1) or the fourth quadrant (1, -1), which is π / 2. -DPSK method. At the third chip time, a quadrant (-1,1) or fourth quadrant (1, -1) value is obtained by the orthogonal code and the PN ₃ code, which is a ZCH scheme. At the fourth chip time, the output appears in the first quadrant (1,1) or the third quadrant (-1, -1), which is the π / 2-DPSK scheme. It can be seen that the above generation process of the spreading code is an implementation method of the hybrid spreading code generated in FIG. 24.

Fig. 26-A is a diagram showing still another configuration of generating a diffusion sequence according to the first embodiment QDZD of the present invention. Referring to FIG. 26-A, the multiplier 711 multiplies the PN _I code by the orthogonal code 1, and the multiplier 721 multiplies the PN _I code by the orthogonal code 2 and outputs the multiplier. Serial-to-parallel converter 731 converts serial PN _Q codes into parallel data and outputs the parallel data. The decimator 741 decimates the PN _Q code output from the deserializer 731 and outputs the odd PN _Q code. The decimator 751 decimates the PN _Q code output from the deserializer 731. Output the even-numbered PN _Q code. The output of the serial-to-parallel converter 731 and the outputs of the decimators 741 and 751 can be more clearly understood in the figure showing the symbol change on the time axis of Figure 26-B below. The output of the serial-to-parallel converter 731 has an odd PN _Q code value changed as shown in decimator 741 of FIG. 26-B, and an even PN _Q code value is changed as shown in decimator 751 of FIG. 26-B. .

The multiplier 712 of FIG. 26-A multiplies the output of the decimator 741 by the output of the multiplier 711 and outputs the spread code C _i . The multiplier 722 multiplies the output of the multiplier 721 and the output of the decimator 751 and outputs the spread code C _q . . FIG. 25 is a structure in which three PN codes are to be used. However, FIG. 26 is a structure in which two PN codes are required while having the same function as in FIG. PN _I is multiplied by orthogonal code ₁ and orthogonal code ₂ in multipliers 711 and 721, respectively. On the other hand, PN _Q is passed through 2-decimators 741 and 751 through serial-to-parallel converter 731, and then multiplied by the output of the product of PN _I and the orthogonal codes in multipliers 712 and 722, respectively, and then output as spread codes C _i and C _q do. The spreading code generator having the structure of FIG. 26 generates PN ₁ and PN ₂ of FIG. 25 using PN _q , and PN ₃ of FIG. 25 generates PN _i .

FIG. 27 is a diagram showing a configuration for generating a spreading sequence according to a second embodiment (ZD) of the present invention. π / 2 Generate spreading code with DSPK. Experimentally, zero spreading of the spreading code degrades the performance of the PAR. However, in the orthogonal spreading process located at the front end of the complex multiplier 100, performance may be changed by orthogonal codes assigned to each channel. The generated spreading code periodically performs zero crossing first and then π / 2 PAR performance can be improved by performing -DSPK. Referring to FIG. 27, the delay unit 811 delays the previous spreading code C _i output. Delay 821 delays the previous spreading code C _q that is output. The multiplier 813 multiplies PN _I by the delayed previous spreading code C _i output from the delay unit 811. The multiplier 815 multiplies PN _Q by -1 to invert PN _Q. The multiplier 814 multiplies the previous spreading code C _q output from the delay unit 821 by the output of the multiplier 815 and outputs the multiplier. The first selector 812 inputs the output of the multiplier 813 as the first signal A, inputs the output of the multiplier 814 as the second signal B, and selects a corresponding signal among the signals A and B input under the control of the control device 831. Output The multiplier 823 multiplies the PN _Q by the previous spreading code C _i output from the delay unit 811 and outputs the multiplier. The multiplier 824 multiplies the previous spread code C _q output from the delay unit 821 by the PN _I. The second selector 822 inputs the output of the multiplier 823 as the second signal B, inputs the output of the multiplier 824 as the first signal A, and outputs a corresponding signal among the signals A and B input under the control of the controller 831. Selective output. In FIG. 27, the first signal A is ZCH and the second signal B is π / 2 -DSPK. The first delays 811 and 821 have {(1,1), (-1,1)} values in the first or third quadrants, and the initial delays 811 and 821 have the {(- 1,1) and (1, -1)} values can be divided and considered. First, if there is a value of one quadrant or three quadrants, the value of one quadrant or three quadrants is first outputted by ZCH. next time π / 2 The quadrant or quadrant is output by DSPK, and the second or fourth quadrant is also output by ZCH. When the initial value is in quadrant 2 or quadrant 4, the output is the same as above.

FIG. 28 is a diagram showing another configuration for generating a diffusion sequence according to the second embodiment ZD of the present invention. In FIG. 28, PN _I is multiplied by the sign of orthogonal code 1 changed in the multiplier 911, and multiplied by orthogonal code 2 in the multiplier 921. In FIG. After PN _Q is decimated in the N-decimator 931, the decimated symbol is repeated during the N chip period as shown in FIG. 25-B. The N value of the N-decimator may have an exponential power of two. The output of the decimator 931 is multiplied by the output of the multiplier 911 at the multiplier 912 and the output of the multiplier 921 at the multiplier 922, the output of the output 912 of the multiplier is C _i and the output of the output 922 of the multiplier is C _q. to be.

FIG. 29 is a diagram illustrating a third embodiment of the present invention, and is a method for avoiding a phenomenon in which PAR is relatively increased not only when the spreading code maintains the same value but also when ZC is performed. In order to avoid ZC and hold of spreading codes PN _I and PN _Q , this method changes the phase of spreading code when ZC occurs. + π / 2 (or -π / 2 ), And otherwise, PN _I and PN _Q are output as they are. This way π / 2 -Hybrid of DSPK and QPSK, but ZC and Hold can be excluded. Referring to FIG. 29, first, a PN code value is input in step 1011, and then, in step 1012, a value of PN _I and PN _Q is compared with a previous value of C _i and C _q . If each value is different in the comparison process of step 1012, go to step 1013 to set the phase of the spreading code. + π / 2 Transition as much as. However, if any of the comparisons in step 1012 have the same value, the process moves to step 1015. In step 1015, if the values of PN _I and PN _{Q and the} values of spreading codes C _i and C _q are the same, the flow advances to step 1014 to phase out the spreading code. -π / 2 Transition as much as. If the PN value and the spreading code value are not the same in step 1015, the process proceeds to step 1016. Step 1016 outputs the value of PN _I to C _i and the value of PN _Q to C _q as it is.

FIG. 30 illustrates the invention as shown in FIGS. 22 and 23. π / 2 Computer simulation of how to generate DPSK spreading codes. The PAR performance was compared with the currently well known QPSK method. The simulation environment uses pilot, control and 3 basic channels, and the orthogonal code uses Walsh code. The power, Walsh code, and simulation conditions used for each channel are as follows.

1) Spreading factor: 4

2) Single Interference: 64 chip delay PN code

3) Power allocation ratio for each channel: pilot channel = 1, control channel = 4, basic channel = 4

Walsh Code:

Pilot channel: 1 1 1 1 1 1 1 1

Control channel: 1 1 1 1 -1 -1 -1 -1

Base channel: 1 1 -1 -1 1 1 -1 -1

The low-pass filter uses a conventional IS-95 type (48 taps). As can be seen in Figure 13 of the present invention π / 2 It can be seen that the PAR of the DPSK spreading code method is lower than the conventional QPSK method.

The following description summarizes the simulation results for the diffusion method presented in the embodiment of the present invention. The conditions used for 4-channel simulation are as follows.

1) Power allocation ratio for each channel: pilot channel = 1, control channel = 4, basic channel = 4, additional channel = 16

2) Walsh code and diffusion coefficient for each channel:

Pilot channel: 1 1 1 1 1 1 1 1

Control channel: 1 1 1 1 -1 -1 -1 -1, PG = 96

Base channel: 1 1 -1 -1 1 1 -1 -1, PG = 64

Additional Channels: 1 -1 1 -1 1 -1 1 -1, PG = 4

3) The format of the PAR performance comparison (4-channel) according to each diffusion method is shown in Table 1 below.

I data channel: pilot channel + control channel

Q data channel: base channel + additional channel

1-CDF (%) PAR (10-2) PAR (10-3) Average power QPSK 6.0993 6.4511 12.5056 ZD 6.0966 6.4196 15.5003 QDZD 6.0537 6.2329 12.5005

The conditions used in the simulation when using 3-channel are as follows.

1) Power allocation ratio for each channel: pilot channel = 1, control channel = 4, basic channel = 4

2) Walsh code and diffusion coefficient for each channel:

Pilot channel: 1 1 1 1 1 1 1 1

Control channel: 1 1 1 1 -1 -1 -1 -1, PG = 96

Base channel: 1 1 -1 -1 1 1 -1 -1, PG = 64

3) The format of the PAR performance comparison (3-channel) according to each diffusion method is shown in Table 2 below.

I data channel: pilot channel + control channel

Q Data Channel: Base Channel

1-CDF (%) PAR (10-2) PAR (10-3) Average power QPSK 6.3243 6.5821 4.5013 ZD 4.7049 4.9857 4.4963 QDZD 4.8634 5.2400 4.5037

As can be seen from Tables 1 and 2, the PAR value of the diffusion method used in the present invention is lower than that of the conventional QPSK.

As described above, the present invention is advantageous in that PAR can be reduced by generating various types of spreading codes according to states in a spread spectrum device of a CDMA communication system.

Claims (31)

A spreading signal generation method of a code division multiple access communication system, Generating a PN code having PNi and PNq, QPSK phase shift, ± 90 degree phase shift, 180 degree phase shift or 0 degree phase shift, respectively, with the PN code as input; And spreading out the phase shifted spreading signals in a predetermined order. The method of claim 1, wherein the process of selectively outputting the phase shifted spreading signal comprises: 15. A method for generating a spreading signal, characterized in that the signal is repeatedly output in order of a QPSK phase shifted signal, a ± 90 degree phase shifted signal, a 180 degree phase shifted or 0 degree phase shifted signal, and a ± 90 degree phase shifted signal. The method of claim 1, The process of selectively outputting the phase shifted spreading signal, 15. A method of generating a spreading signal, characterized by repeatedly outputting a signal having a phase shift of ± 90 degrees and a phase shift of 180 degrees or a phase shift of 0 degrees. The method according to claim 2 or 3, And selectively outputting the phase shifted spreading signal to at least one 180 degree phase shifted signal. A spreading signal generation method of a code division multiple access communication apparatus, A first process of continuously generating a PN code sequence having PNi and PNq in a chip cycle; A second process of outputting the phases Ci and Cq of the previous spreading signal as a first phase shift by inputting the generated values of the first chip periods of PNi and PNq; And a third process of outputting the second (Ci, Cq) output of the second process by a second phase shift in a next chip period. The method of claim 5, And outputting the phase shifted Ci and Cq columns by repeating the second process and the third process by inputting PNi and PNq of the first process. The method of claim 6, At least one phase shift of the Ci and Cq phase shifts of 180 degrees. The method of claim 5, And the first phase shift and the second phase shift are zero crossing and 90 degree phase shift, respectively. The method of claim 5, Wherein the first phase shift is 0 degrees and the second phase shift is ± 90 degrees. The method of claim 5, Wherein the first phase shift is 180 degrees and the second phase shift is ± 90 degrees. The method of claim 5, Wherein the first phase shift is ± 90 degrees and the second phase shift is 0 degrees phase shift. The method of claim 5, And the first phase shift is ± 90 degrees, and the second phase shift is 180 degrees. The method of claim 8, wherein The second and third processes are repeated according to the chip period of the PNi and PNq columns to output Ci and Cq columns. The method of claim 5, A fourth process of outputting the phases of the diffusion signals Ci and Cq of the third process by a third phase shift by inputting values of the third chip periods of the PNi and PNq; And a fifth step of outputting the fourth (Ci, Cq) output of the fourth process by outputting the fourth chip period by inputting the values of the fourth chip periods of PNi and PNq. The method of claim 14, And a fourth phase shift in the first phase shift is QPSK, ± 90 degrees DPSK, zero crossing, and ± 90 degrees DPSK. The method of claim 15, And a fifth process is repeated in the second process according to the chip period of the PNi and PNq columns to output Ci and Cq columns. An apparatus for generating a spread spectrum signal of a code division multiple access communication system, A PN code generator for generating a PN code string having PNi and PNq, A delay unit for delaying the previous spread code output by one chip unit and outputting it And an arithmetic unit which outputs the phase of the spread signal by calculating the output of the P-encoded signal and the delay unit by one chip unit. The method of claim 17, And a phase change of the spread signal is a continuation of zero crossing and ± 90 degrees DPSK. The method of claim 17, And a calculating unit outputting the encoded code string without a phase change. The method of claim 19, A spreading signal generator, characterized in that the output of the operation unit is a series of zero crossing and QPSK. The method of claim 19, And the output of the operation unit is a continuous QPSK, ± 90 degrees DPSK, zero crossing, ± 90 degrees DPSK. The method of claim 19, And the output of the operation unit is a continuous signal of ± 90 degrees DPSK, QPSK, and ± 90 degrees DPSK. The method of claim 19, The output of the operation unit is a spread signal generator, characterized in that the successive QPSK, zero crossing, QPSK, ± 90 degrees DPSK. The method of claim 17, wherein the operation unit, A phase shifter having means for at least QPSK phase shift, zero crossing and hold, ± 90 DPSK phase shift, A control unit repeatedly generating a selection control signal in a predetermined order; And spreading out one of the phase shift signals of the phase shift unit according to the selection control signal. An apparatus for generating a spread spectrum signal of a code division multiple access communication system, A PN code generator for generating a PN code string having PNi and PNq, A first decimator for four-decimating the PNi signal and repeating it four times; A second decimator 4-decimating the PNq signal and repeating it four times; A first multiplier for multiplying the output of the first decimator by a first code sequence in units of chips; A second multiplier for multiplying the output of the second decimator by a second code string in units of chips; Means for outputting a spread signal Ci by multiplying the output of the first multiplier by another pien code, and outputting a spread signal Cq by multiplying the output of the second multiplier by the another pien code. Diffusion signal generator. The method of claim 25, And the first code string is (+-+-) and the second code string is (++-). An apparatus for generating a spread spectrum signal of a code division multiple access communication system, A PN code generator for generating a first PN and a second PN, A first multiplier for multiplying the first PN signal by a first code sequence in units of chips; A second multiplier for multiplying the first PN signal by a second code string in units of chips; A serial-to-parallel converter for dividing the second PN signal into an odd-numbered input and an even-numbered input; A first decimator which repeats the second input by two-decimating the odd-numbered input, A second decimator which repeats the second even number by two-decimating the even-numbered input; Means for multiplying the output of the first multiplier by the output of the first decimator and outputting a first spreading signal; Diffusion signal generator, characterized in that. The method of claim 27, The first signal sequence is orthogonal code (+-+-) and the second code sequence is orthogonal code (++-) characterized in that the spreading signal generator An apparatus for generating a spread spectrum signal of a code division multiple access communication system, A PN code generator for generating a first PN and a second PN, A first multiplier for multiplying the first PN signal by a first code sequence in units of chips; A second multiplier for multiplying the first PN signal by a second code string in units of chips; A decimator which repeats the second PN signal by two-decimation and repeats it twice; Means for outputting a first spreading signal by multiplying the output of the first multiplier with an output of the decimator, and outputting a second spreading signal by multiplying the output of the second multiplier with the output of the decimator. Diffusion signal generator. The method of claim 29, And a first code string is an orthogonal code (-+-+) and a second code string is an orthogonal code (++-). A method for generating a spread spectrum signal in a code division multiple access communication system, A first step of comparing a PN code having PNi and PNq with previous spread signals Ci and Cq; Comparing the phases of the spread signal with +90 degrees if the phases of PNi and Ci are different and the phases of PNq and Cq are different; Comparing the phases of the spread signal with -90 degrees if the phases of PNi and Ci are the same and the phases of PNq and Cq are the same. The comparison signal generation method of the spread signal having a phase of PNi and PNq if any one of the phase of PNi and Ci and the phases of PNq and Cq is the same and different.