JP4574440B2 - Spread spectrum communication equipment - Google Patents

Description

  The present invention relates to a spread spectrum communication apparatus used for spread spectrum such as mobile communication and wireless LAN, and more particularly to a spread spectrum communication apparatus capable of a simple and small-scale configuration.

In a spread spectrum (SS) communication system generally used for mobile communication or wireless local area network (LAN), narrow band modulation (primary modulation) is performed on transmission data on the transmission side, and then spread modulation is performed. (Secondary modulation) Performs two-stage modulation and transmits data. On the receiving side, the received data is despread and returned to the primary modulation, and then the baseband signal is output by a normal detection circuit. To play.

A transmission data spreading method will be described below. In the transmission data, each pair of continuous symbol data is first serial-parallel converted and classified into an in-phase component and a quadrature component, respectively. Here, when the in-phase component is Ti, the quadrature component is Tq, the in-phase component of the spreading code is Ci, and the quadrature component is Cq, the spread signal D obtained by spreading is D = (Ti + jTq) × (Ci + jCq) (Equation 1)
= (Ti * Ci-Tq * Cq) + j (Ti * Cq + Tq * Ci) (Formula 2)
It is expressed. From (Equation 2), the in-phase component Di and the quadrature component Dq of the spread signal are as follows: Di = Ti × Ci−Tq × Cq (Equation 3)
Dq = Ti × Cq + Tq × Ci (Formula 4)
It is expressed.

The configuration and operation of a spreading apparatus that implements the transmission data spreading method described above will be described with reference to FIG. FIG. 3 is a block diagram of a conventional spread circuit for spread spectrum communication. Symbol data 1 (I, Q), which is transmission data, is input to the spreader 3A. The code generator 32A outputs a spreading code obtained by multiplying the channelization code for each Ch (channel) and the common scrambling code (I, Q) (exclusive OR operation), and the complex multiplier 33A (Expression 3) ) And (Equation 4) are performed. In addition, the complex multiplier 34A multiplies the transmission gain for each channel to produce the output of the spreader 3A. The spreaders 3B to 3N of each Ch perform the same processing, add in the adder 35, and output as a multiplexed spread signal. The multiplexed spread signal is then D / A converted, quadrature modulated, frequency converted and amplified in common to each channel and transmitted from the antenna.

Also, it is known that the development period is shortened by adopting the same configuration in which a combiner for weighted addition of a plurality of channel signals for transmission and a despreader for reception can be used in common (for example, patents) Reference 1).
In addition, in order to amplify the power of a QAM (Quadrature Amplitude Modulation) signal with high efficiency, it is known that the signal is synthesized after being amplified in the state of QPSK (Quadrature Phase Modulation) (for example, see Patent Document 2).

JP 2003-234673 A Japanese Patent Application Laid-Open No. 09-200308

However, in the technique of Patent Document 1, although a part of the configuration of the circuit module can be made common for transmission and reception, when the number of taps is matched with the number required for the matched filter for reception, the number of channels for transmission is smaller than that for transmission. There was a problem that it was fixed at a value larger than necessary (for example, 512) and lacked flexibility. Also, for example, when developing mobile phone base stations with different capacity, it is not efficient to design and verify circuit modules that are suitable for each capacity. There was a problem of becoming high.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a spread spectrum communication apparatus that can be developed in a short period of time with a simple and small-scale configuration even for different specifications.

The spread spectrum communication apparatus of the present invention includes a data register for holding I and Q each having a plurality of bits, a code register for holding I and Q each having 1 bit, and outputs of the data register and the code register. A complex multiplier that performs a complex multiplication of M, M taps (M is a natural number of 2 or more), an adder that adds the outputs of the M taps, an output register that stores the output of the adder, N + 1 signal synthesizing means (synthetic spread signal generating circuit) having the same configuration (N is a natural number equal to or less than M), and each of the N signal synthesizing means has an I of each data register. , Q is input with a transmission power gain, and data obtained by spreading symbol data with a channelization code is input into each of the code registers I and Q. A signal synthesizing means inputs the outputs of the N signal synthesizing means to I and Q of each of the data registers, and each of the code registers is a signal obtained by giving an input to the data register of the same tap. A scrambling code common to the channels processed by the combining means is input, and the N + 1 signal combining means combines the spread signals of a plurality of channels.

Further, at least one of the N signal synthesis means inputs each bit of data obtained by spreading symbol data consisting of a plurality of bits I and Q with a channelization code to the plurality of code registers. A transmission power gain having a ratio of powers of 2 giving a weight corresponding to each bit is input to a plurality of corresponding data registers.

According to the present invention, it is possible to process a plurality of Ch diffusion processes at a time by configuring the composite spread signal generating circuit in a two-stage configuration. Also, the same module can be used for both the function unit of the spread data / transmission gain multiplication processing unit and the scrambling code diffusion processing unit, leading to improvement in development efficiency.

To summarize the best mode of implementation of the present invention, a data register holding multiple bits of I and Q, a code register holding 1 bit of I and Q, respectively, and a complex multiplication of the output of the data register and code register N + 1 signal synthesizing means (N is M), each comprising M complex taps, an adder for adding M tap outputs, and an output register for storing the adder outputs. And a two-stage configuration in which the output of another signal synthesis means is input to one signal synthesis means.
In the first-stage signal synthesis means, the transmission power gain is input to the data register, and the data obtained by spreading the symbol data with the channelization code is input to the code register. Channels using the same scrambling code are allotted to each first-stage signal synthesis means, and the scrambling code is input to the code register of the subsequent-stage signal synthesis means.

Hereinafter, the embodiments will be described with reference to the drawings, but the function realizing means described in each embodiment may be any circuit or device as long as it realizes the function. It is also possible to realize part or all of the above by software. Furthermore, the function realizing means may be realized by a plurality of circuits, and the plurality of function realizing means may be realized by a common circuit.
Further, any combination of the embodiments and a combination with the prior art such as Patent Document 1 can also be included in the present invention.

FIG. 1 is a block diagram of the combined spread signal generating circuit of this embodiment. Assuming that each set of the synthesis coefficient register 11, the code register 12, and the complex multiplier 13 is one tap, the four-tap composite spread signal generation circuit 1 is illustrated.
Each of the four synthesis coefficient registers 11A to 11D stores Ri and Rq data of 8 bits each for a total of 16 bits. Each of the four code registers 12A to 12D stores Ci and Cq codes by 1 bit for a total of 2 bits.

The complex multiplier 13A performs complex multiplication on the inputs from the synthesis coefficient register 11A and the code register 12A. That is, if the data of the synthesis coefficient register 11A is Ri + jRq and the code of the code register 12A is Ci + jCq, the output D of the complex multiplier 13A is
D = (Ri + jRq) × (Ci + jCq) (Formula 5)
= (Ri * Ci-Rq * Cq) + j (Ri * Cq + Rq * Ci) (Formula 6)
It is expressed. The real part and imaginary part of output D are
Di = Ri * Ci-Rq * Cq (Formula 7)
Dq = Ri × Cq + Rq × Ci (Formula 8)
It is expressed. However, in the above formula, the 1-bit code is calculated as “1” when “0”, and “−1” when “1”. The x operation in the above formulas 6 to 8 is only sign inversion, and when using signed int by a combination of a sign bit and an absolute value as a negative internal representation format, for example, the sign bit of Ri and Rq and the ExOR of Ci and Cq Can be realized. Similarly, the code and complex multipliers 13B to 13D output the results calculated using the corresponding synthesis coefficient registers 11B to D and code registers 12B to D, respectively.

Finally, the adder 14 adds four outputs Di and Dq from the complex multipliers 13A to 13D, and outputs the result as Ai: 11 bits and Aq: 11 bits.
The number of bits of each register of the complex correlator described above does not necessarily have the bit width as shown in the figure, and the bit width that can achieve the function to be realized or the synthesized spread signal generation circuit that can change the bit width Configure as.

Next, a spreading apparatus using the above-described combined spread signal generating circuit 1 will be described with reference to FIG. FIG. 2 is a configuration diagram of a diffusion device that diffuses and outputs data for 16 Ch. Although not shown, Ch to be processed by the control unit is distributed in advance for each scrambling code. In the case of FIG. 2, one scrambling code can be set for every 4Ch, and the common scrambling codes corresponding to Ch1 to 4 (Symbol Data1 to 4) processed by the synthesized spread signal generating circuit 1A are the scrambling codes. Set to the generator (Scr.Code generator) 2A. Similarly, common scrambling codes corresponding to the combined spread signal generating circuits 1B to 1D are set in the scrambling code generators 2B to 2D, respectively. Thereby, diffusion processing for 4 Ch × 4 Scrambling Code = 16 Ch becomes possible. Even if there is 3 Ch or less (less than 4 Ch) for one Scrambling Code, it can be processed without problems by setting Gain to 0 for empty Ch.

The code registers 12A to 12D of the composite spread signal generating circuit 1A multiply the channelization codes of each Ch output from the Channelization Code generators 4a to 4d and the symbol data of each Ch by multipliers 5A to 5D (ExOR). Set what you did. Each Symbol Data is assumed to be primarily modulated by QPSK (Quadrature Phase Shift Keying). In the composite coefficient registers 11A to 11D, transmission power Gain (effective tone 5bit / 8bit) of each Ch is set. For setting, a set value is input to the Ri side, and 0 is input to the Rq side. By setting in this way, the Rq term of the calculation results of the derivation equations (Equation 7) and (Equation 8) performed by the complex multipliers 13A to 13D becomes 0, and the code registers 12A to D have the set values. On the other hand, the Ri set value is multiplied as it is.
The set synthesis coefficient registers 11A to 11D and code registers 12A to 12D are respectively operated by the corresponding complex multipliers 13A to 13D in the derivation expressions (Expression 7) and (Expression 8). A value obtained by adding the in-phase component and the quadrature component for 4 Ch is output as Ai and Aq (7 bits / 11 bits).
Similarly, the other composite spread signal generation circuits 1B to 1D input [Channelization Code] ExOR [Symbol Data] of each Ch to the code registers 12A to D and input the transmission power Gain of each Ch to the synthesis coefficient registers 11A to 11D. , Output as Ai and Aq (7 bits / 11 bits), respectively.

Next, the outputs (lower 8 bits) of the respective synthesized spread signal generation circuits 1A to 1D are input to the synthesis coefficient register 11A of the synthesized spread signal generation circuit 1E. A scrambling code common to 4Ch processed by the combined spread signal generating circuit 1A is input from the scrambling code generator 2A to the code register 12A of the combined spread signal generating circuit 1E. Similarly, the outputs of the combined spread signal generating circuits 1B to D are input to the combined coefficient registers 11B to 11D of the combined spread signal generating circuit 1E. The scrambling code generators 2B to D input the common scrambling code for every 4Ch processed by the combined spread signal generation circuits 1B to D to the code registers 12B to D of the combined spread signal generation circuit 1E. The set synthesis coefficient registers 11A to 11D and code registers 12A to 12D are respectively operated by the corresponding complex multipliers 13A to 13D in the derivation expressions (Expression 7) and (Expression 8). The values obtained by adding the in-phase component and the quadrature component for 4 sets (16Ch) are output (11 bits) as spread data I_Out and Q_Out.

As the scrambling code generated by each of the scrambling code generators 2A to 2D, in addition to the primary scrambling code and secondary scrambling code of the base station, there is a possibility that different scrambling codes may be taken depending on the scrambling code change in the compressed mode. The number of scrambling code generators 2A to 2D may be the same scrambling code. Each of the scrambling code generators 2A to 2D and the channelization code generators 4a to 4p need not individually generate these codes in real time, but develops all possible codes in a common memory in advance. You may make it select as needed.

In the present embodiment, the number of taps of the combined spread signal generating circuit and the number of combined spread signal generating circuits 1A to 1D inputted to the combined spread signal generating circuit 1E are set to be equal, but the combined spread signal generating circuit is more than the number of taps. The number may be reduced, so that the required number of Ch can be flexibly met. Further, the combined spread signal generating circuit is not limited to the two-stage configuration, but may be a multi-stage configuration having three or more stages.
According to the present embodiment, the spread device is configured by combining a general-purpose functional block with high reusability such as a combined spread signal generation circuit, so that a complex multiplier is used to set the transmission output Gain. Although the scale seems to increase slightly compared to the individual design, the reuse rate of design assets increases, so the development man-hours can be greatly reduced while suppressing the increase in scale.

In the present embodiment, it will be described that the first embodiment can be applied to HSDPA (High Speed Downlink Packet Access) in the W-CDMA mobile phone system. In HSDPA, low-speed QPSK (Quadrature Phase Shift Keying) is used for transmission from the base station when the transmission line condition is bad, and high-speed 16QAM (16 Quadrature Amplitude Modulation) is used when the transmission line condition is good. It is necessary to support both modulation methods.

Further explaining each modulation method, in QPSK, a symbol data stream is divided into 2 bits when the head is right.
... I | Q I | Q I | Q I | Q I |
... 0 | 0 0 | 1 1 | 0 1 | 1 0 |
It is handled in the internal format. Then, it is divided into two phases of I and Q by bit shift, and mapping is performed with 2 bits as 1 symbol by plotting each bit from 0 → −1, 1 → 1. FIG. 4 shows QPSK symbol mapping with an intersymbol distance of 8a. In the figure, the horizontal axis represents the in-phase component I of the quadrature phase modulation method, and the vertical axis represents the quadrature component Q.

In 16QAM, the symbol data stream is divided every 4 bits.
_{... I | Q 2 I 2 Q} I | Q 2 I 2 Q I | ...
... 0 | 0 0 1 1 | 0 1 1 0 |
It is handled in the internal format. Then, 4, performs QPSK symbol mapping such as amplitude of I _2, Q ₂ is I, the one-half of the amplitude of Q for each I, Q and I _2, Q ₂ as shown in FIG. After that, 16QAM symbol mapping is completed as shown in FIG. 6 by adding and synthesizing the in-phase components I and I ₂ and quadrature components Q and Q _{2 of} each symbol. In FIG. 6, what is indicated by ◯ is mapping by only I and Q, and mapping by I ₂ and Q ₂ shown in FIG.

In this embodiment, when 16QAM is used, the symbol data stream is divided into I, Q and I ₂ and Q ₂ by 2-bit shift or the like to form two QPSK symbol formats, and each is multiplied by a common channelization code. In the above, for example, the data is input to the code registers 12A and 12B. In addition, amplitudes 2 / √5 and 1 / √5 of the amplitude for obtaining the same transmission power by QPSK, for example, are set in the synthesis coefficient registers 11A and 11B, for example.
Further, when 64QAM is used, similarly, a QPSK signal having an amplitude ratio of 4: 2: 1 may be generated and synthesized, and the same applies to multilevel modulation beyond that. FIG. 7 shows a flowchart of symbol mapping processing corresponding to QPSK, 16QAM, and 64QAM.

According to the present embodiment, a spread device can be realized with the same circuit module for multi-level modulation such as 16QAM by using an arbitrary plurality of channels for QPSK, and the modulation scheme can be changed according to the transmission path state. Can be easily accommodated. Further, compared with the case where QPSK and 16QAM are configured by separate circuit modules, the hardware utilization efficiency can be made extremely high.

FIG. 8 shows a configuration example of a complex correlator provided in the spread spectrum communication spread device according to the present embodiment.
The complex correlator of this example includes a combined spread signal generation circuit 41, an output register 42, a common scrambling code register 43, a complex multiplier 44, and an output register 45.
The synthesized spread signal generation circuit 41 includes four synthesis coefficient registers 51A to D, four code registers 52A to D, two switches 53A and B, one complex multiplier 54, and one An adder 55 and one delay register 56 are provided.

As the combined spread signal generating circuit 41 of this example, assuming that each set of the combined coefficient register 51 and the code register 52 is one tap, an example in the case of four taps is shown.
In the 4-tap synthesis coefficient registers 51A to 51D, data of Ri and Rq are stored in a total of 16 bits, 8 bits each. Further, each of the 4-tap code registers 52A to 52D stores 2 bits in total for each of the codes of Ci and Cq.
In this example, the outputs from the synthesis coefficient registers 51A to 51D are sequentially switched by the switch 53A and input to the common complex multiplier 54. Similarly, the outputs from the code registers 52A to 52D are sequentially switched by the switch 53B and input to the common complex multiplier 54.

  Here, the transmission power Gain of each Ch is set in the synthesis coefficient registers 51A to 51D. As a setting, a set value is input to the Ri side, and 0 is input to the Rq side. The code registers 52A to 52D are preliminarily set by multiplying (EOR) the symbol data I and Q and the channelization code. By setting in this way, the Rq term of the calculation results of the derivation expressions (Expression 7) and (Expression 8) performed by the complex multiplier 54 becomes 0, and the set values of the code registers 52A to 52D Thus, the set value of Ri is multiplied as it is. However, in the above calculation formula, the code 1 bit is calculated as 1 when “0”, and as −1 when “1”.

The result calculated by the complex multiplier 54 is output in time division in the order of A to D, and is input to the adder 55. Then, values obtained by adding the in-phase component and the quadrature component for 4 Ch by the adder 55 and the delay register 56 are output to the output register 42 as Ai: 11 bits and Aq: 11 bits. At the time of cumulative addition by the adder 55 and the delay register 56, the delay register 56 is first cleared by a register clear signal, then the data for 4Ch input in time division is cumulatively added, and the result is output. After the output to the register 42, a series of operations of clearing the delay register 56 with the register clear signal and accumulating again is repeated.
The output data Ai, Aq from the output register 42 is spread by the complex multiplier 44 with the common scrambling code, and the result is output to the output register 45 as output data Bi, Bq. The complex multiplier 44 receives the I and Q components of the common scrambling code stored in the register 43.

  As described above, the complex correlator according to the present embodiment has a plurality of multi-bit synthesis coefficient registers 51A to 51D for each of I and Q, and the switch 53A for switching the inputs of the plurality of synthesis coefficient registers 51A to 51D in a time division manner. A plurality of 1-bit code registers 52A to 52D, a switch 53B for switching the inputs of the plurality of code registers 52A to D in a time-sharing manner, and outputs from the two switches 53A and 53B. It has a complex multiplier 54 that performs complex multiplication as an input, an adder 55 that accumulates the outputs of the complex multiplier 54, a delay register 56, and an output register 42 that stores the output.

  In the spreading apparatus according to the present embodiment, in the complex correlator as described above, the transmission power Gain is input to the I side of each of the multi-bit synthesis coefficient registers (data registers) 51A to 51D and the Q side is input to the Q side. 0 is input, data obtained by spreading (EOR) the symbol data by channelization code is input to the 1-bit code registers 52A to 52D of I and Q, and the plurality of synthesis coefficient registers 51A to 51D and code registers 52A to 52D are input. A plurality of channels are respectively set, and a calculation result obtained from the complex multiplier 54 or the like is subjected to complex correlation calculation using a common scrambling code to obtain a spread output.

Therefore, in this embodiment, when the data for 4 Ch is diffused and output, the circuit scale can be reduced by using the complex multiplier 54 of the combined spread signal generation circuit 41 in a time division manner.
For example, a simple and small-scale configuration can be realized in a correlation circuit, a modulation / demodulation circuit, and a transmission device for spread spectrum communication used in a transmitter of a spread spectrum communication system.

Note that, in the combined spread signal generating circuit 41 according to the present embodiment, for example, the same processing as that of the combined spread signal generating circuit 81 shown in FIG. 10 can be executed.
FIG. 10 shows a configuration example of a spreader for spread spectrum communication.
In the spreading apparatus of this example, a transmission data spreading method is realized by the following configuration and operation.
In this example, data for 4 Ch is diffused and output. The 4-tap synthesis coefficient registers 51A to 51D, the 4-tap code registers 52A to 52D, and the set values thereof are the same as those shown in FIG.

In this example, for each of A to D, the corresponding complex multipliers 91A to 91D derive derivation equations (Equation 7) for the set values of the synthesis coefficient registers 51A to 51D and the values of the code registers 52A to 52D. And the calculation of (Equation 8) is performed. Then, a value obtained by adding the in-phase component and the quadrature component for 4 Ch by the adder 92 is output to the output register 42 as Ai: 11 bits and Aq: 11 bits.
The output data Ai and Aq are diffused by the complex multiplier 44 with a common scrambling code and output to the output register 45 as output data Bi and Bq.

FIG. 9 shows a configuration example of a complex correlator provided in the spread spectrum communication device according to the present embodiment.
The complex correlator of this example has a combined spread signal generation circuit 61 and an output register 62.
The synthesized spread signal generating circuit 61 includes four synthesis coefficient registers 71A to 71D, four code registers 72A to 72D, two switches 73A and B, one complex multiplier 74, and one An adder 75 and one delay register 76 are provided. The synthesized spread signal generating circuit 61 of this example has the same configuration as the synthesized spread signal generating circuit 41 shown in FIG. 8, and performs the same operation.

  Here, in each of the synthesis coefficient registers 71A to 71D, a value obtained by multiplying the transmission power Gain of each Ch by the common scrambling code is set. In addition, the code registers 72A to 72D are set in advance by multiplying (EOR) the symbol data I and Q and the channelization code. With respect to the set values of the synthesis coefficient registers 71A to 71D and the values of the code registers 72A to 72D, the complex multiplier 74 performs operations of the derivation expressions (Expression 7) and (Expression 8), respectively. Further, a value obtained by accumulating the in-phase component and the quadrature component for 4 Ch by the accumulator including the adder 75 and the delay register 76 is output to the output register 62 as Ai: 11 bits and Aq: 11 bits to be spread data. . However, in the above calculation formula, the code 1 bit is calculated as 1 when “0”, and as −1 when “1”.

  As described above, in the spreader according to the present embodiment, in the complex correlator, the I and Q multi-bit combining coefficient registers (data registers) 71A to 71D multiplied by the transmission power Gain and the scrambling code are input. The data obtained by spreading the symbol data by channelization code is input to 1-bit code registers 72A to 72D for each of I and Q, and a plurality of channels are set to the plurality of synthesis coefficient registers 71A to 71D and code registers 72A to 72D, respectively. And thereby obtain a diffuse output.

Therefore, in this embodiment, when the data for 4 Ch is diffused and output, the circuit scale can be reduced by using the complex multiplier 74 of the combined spread signal generation circuit 61 in a time division manner.
For example, a simple and small-scale configuration can be realized in a correlation circuit, a modulation / demodulation circuit, and a transmission device for spread spectrum communication used in a transmitter of a spread spectrum communication system.

Note that, in the combined spread signal generating circuit 61 according to the present embodiment, for example, the same processing as the combined spread signal generating circuit 101 shown in FIG. 11 can be executed.
FIG. 11 shows a configuration example of a spreader for spread spectrum communication.
In the spreading apparatus of this example, a transmission data spreading method is realized by the following configuration and operation.
In this example, data for 4 Ch is diffused and output. The 4-tap synthesis coefficient registers 71A to 71D, the 4-tap code registers 72A to 72D, and the set values thereof are the same as those shown in FIG.

  In this example, for each of A to D, the corresponding complex multipliers 111A to 111D derive derivation formulas (Formula 7) for the set values of the synthesis coefficient registers 71A to 71D and the code registers 72A to 72D. And the calculation of (Equation 8) is performed. Then, a value obtained by adding the in-phase component and the quadrature component for 4 Ch by the adder 112 is output to the output register 62 as Ai: 11 bits and Aq: 11 bits to be spread data.

In the present embodiment, the following setting is made in the configuration as shown in FIG.
That is, in each of the synthesis coefficient registers 71A to 71D, a value obtained by multiplying the transmission power Gain of each Ch and the Channelization Code in advance and multiplying the multiplication result by the common scrambling code is set. Symbol data I and Q are set in advance in each code register 72A to 72D. Even with such a setting, the same processing as in the above-described fourth embodiment is possible.

  As described above, in the spreading apparatus according to the present embodiment, in the complex correlator, the I and Q multi-bit combining coefficient registers (data registers) 71A to 71D are multiplied by the transmission power Gain and the channelization code, and further the scrambling code. , The symbol data is input to the 1-bit code registers 72A to 72D for each of the I and Q, and a plurality of channels are set to the plurality of synthesis coefficient registers 71A to 71D and the code registers 72A to 72D, respectively. And thereby obtain a diffuse output.

  Note that the number of bits of each register of the complex correlator described in each of the above embodiments does not necessarily have the exemplified bit width, and has, for example, a bit width that can achieve the function to be realized. It is possible to configure a combined spread signal generating circuit or a combined spread signal generating circuit capable of changing the bit width.

FIG. 3 is a configuration diagram of a synthesized spread signal generating circuit according to the first and second embodiments. It is a block diagram of the spreading | diffusion apparatus of Example 1 and 2. FIG. It is a block diagram of the conventional spreading | diffusion apparatus. 6 is an I and Q symbol mapping diagram of Embodiment 2. FIG. FIG. 6 is an I ₂ and Q ₂ symbol mapping diagram according to the _second embodiment. 10 is a 16QAM symbol mapping diagram of Embodiment 2. FIG. 10 is a flowchart of symbol mapping processing according to the second embodiment. FIG. 10 is a configuration diagram of a composite spread signal generation circuit according to a third embodiment. FIG. 6 is a configuration diagram of a combined spread signal generating circuit according to Embodiments 4 and 5. It is a block diagram of a synthetic | combination spreading | diffusion signal generation circuit. It is a block diagram of a synthetic | combination spreading | diffusion signal generation circuit.

Explanation of symbols

1A to 1E, 41, 61, 81, 101: Composite spread signal generation circuits 11A to 11D, 51A to 51D, 71A to 71D: Synthesis coefficient registers 12A to 12D, 52A to 52D, 72A to 72D: Code registers 13A to 13D, 44, 54, 74, 91A to 91D, 111A to 111D: Complex multipliers 14, 55, 75, 92, 112: Adders 2A to 2D: Scrambling Code generator 3: Spreader (conventional)
4a to 4p: Channelization Code generators 5a to 5p: Complex multipliers 42, 43, 45, 56, 62, 76: Registers 53A, 53B, 73A, 73B: Switches

Claims (2)

A data register for holding I and Q each consisting of a plurality of bits, a code register for holding I and Q each consisting of 1 bit, a complex multiplier for complex multiplying the outputs of the data register and the code register, M taps (M is a natural number of 2 or more),
An adder for adding the outputs of the M taps;
N + 1 signal synthesizing means (N is a natural number equal to or less than M) having the same configuration composed of an output register for storing the output of the adder;
Each of the N signal combining means inputs a transmission power gain to either I or Q of each of the data registers, and symbol data is channelized to each of I and Q of the code registers. Enter the data spread in
The output of the N signal synthesizing means is inputted to each of the data registers I and Q to the one signal synthesizing means, and the input to the data register of the same tap is given to each of the code registers. Input a scrambling code common to the channels processed by the signal synthesis means,
The spread spectrum communication apparatus, wherein the N + 1 signal combining means combines spread signals of a plurality of channels. In at least one of the N signal combining means,
Each bit of data obtained by spreading symbol data consisting of a plurality of bits I and Q with a channelization code is input to the plurality of code registers,
2. The spread spectrum communication apparatus according to claim 1, wherein a transmission power gain having a power-of-two ratio that gives a weight corresponding to each bit is input to a plurality of corresponding data registers.

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