KR19990076182A - Synchronous dynamic RAM controller device and its connection method - Google Patents

Abstract

Disclosed are a synchronous dynamic RAM controller device and a method of connecting the same. A preferred embodiment of the synchronous dynamic RAM controller device includes n processor access blocks having a function of receiving a signal from a processor and sending a signal requesting SDRAM read / write to a regulator block, each of which is connected to each processor access block to write an SDRAM N write memory that temporarily holds the data to write to the SDRAM, the regulator block that receives the SDRAM access control signals from the n processor access blocks and selects one of them to send to the SDRAM access block, every predetermined time Regeneration interrupt generator that generates a signal to regenerate the SDRAM, a power-on initialization block that generates initial values to be written to the SDRAM when the power is turned on, and an SDRAM connection block that generates data for writing to or reading from the SDRAM and accesses data. It includes.

Description

Synchronous dynamic RAM controller device and its connection method

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a synchronous dynamic random access memory (SDRAM) controller device and a method of connecting the same, particularly when a plurality of processors or controllers want to write or read data in one SDRAM. The present invention relates to an SDRAM access method for performing coordination between devices and minimizing time loss during each central processing unit (hereinafter referred to as CPU) or control device adjustment period.

Generally, there are one memory 10, one CPU 12, and processors 14 and 16 that want to access several memories. In this case, as shown in the connection diagram, processors that share CPU local buses and access memory as shown in FIG. 1 indicate that they want to access memory by sending bus request signals to the CPU. In addition, the CPU takes this signal, adjusts it, and sends a signal to the processor that sent the bus request signal to the processor that sent the bus request signal so that the processor can use the CPU local bus to write to or read data from the memory.

In this case, the CPU must perform all the adjustments, and while the processor is using the local bus to access the memory, the CPU uses the local bus to do something else (that is, access to memory other than the memory access shown in Figure 1). By not doing so, the CPU's efficiency can be reduced.

In addition, various priorities may be required to access the memory. In this case, if there is a coordinator in the CPU, it is impossible to support various priorities.

Accordingly, the present invention was devised to solve the above problems, and to minimize the time to adjust and adjust the connection order of processors or control devices in order to connect a plurality of processors or control devices to one SDRAM. An object of the present invention is to provide an SDRAM controller and a connection method thereof.

It can also provide a variety of priorities, reduce CPU load by leaving the CPU's regulator function outside of the CPU, and allow independent processing of the CPU's local bus completely independent while other processors access SDRAM. An object of the present invention is to provide an SDRAM controller and a connection method thereof.

Other objects and advantages of the present invention will become more apparent from the following detailed description of the invention and the accompanying drawings.

1 is a board for control applied in the present invention.

2 illustrates an SDRAM controller structure in accordance with the present invention.

3 is a flow chart for the arbitration function for SDRAM connection in a regulator block in accordance with the present invention.

In order to achieve the above object, a preferred embodiment of the SDRAM controller device according to the present invention,

N processor access blocks having a function of receiving a signal from a processor and sending a signal requesting SDRAM read / write to a regulator block;

N write memories connected to each processor access block to temporarily hold data to be written to SDRAM during an SDRAM write operation;

a regulator block for receiving SDRAM access control signals from the n processor access blocks and selecting one of the signals to be sent to the SDRAM access block;

A reproduction interrupt generator for generating a signal for reproducing the SDRAM every predetermined time;

A power-on initialization block that generates initial values that should be written to the SDRAM when the power is turned on; And

It contains SDRAM access blocks that generate signals for writing to and reading from SDRAM and access data.

In the present invention, the predetermined time is preferably 2.56 µs.

In order to achieve the above object another preferred embodiment of the SDRAM connection method according to the present invention,

Setting initial values of SDRAM when power is first turned on;

The playback interrupt generator block may include: generating a interrupt by turning a timer every predetermined time so that playback may be performed first in the regulator block;

when n processors or control devices share SDRAM data, each processor sends and receives signals to a processor access block in the SDRAM controller;

Transferring the start address and byte length to be written to the processor access block when reading data, and transmitting the start address and byte length to be written and data to be written to the processor access block when writing data;

When data is written in the above process, the processor access block temporarily stores the data in the write memory block, transmits a signal requesting the SDRAM write connection to the coordinator block, and transmits a signal indicating that writing is completed to the processor. To allow others to do other things;

When reading data, the process access block sends a signal requesting an SDRAM read connection to the coordinator block, waits for a read signal to be accepted and read data to be transmitted, and then transfers the data to the processor when the data is transmitted. Completing a data read connection by transmitting a signal indicating that the data read connection is completed;

A regulator block receiving an SDRAM write request or read request signal from each processor access block determines which one to send from the processor access block to the SDRAM access block;

If it is determined in the process that the processor's SDRAM write signal, the regulator block reads the first address for SDRAM write and data to be written from the temporarily written write memory to the SDRAM access block;

If it is determined that the processor is an SDRAM read signal, the regulator block transmits an address for reading to the SDRAM access block, waits for data to come in, and then transfers the data to the corresponding SDRAM access block when data comes in;

The SDRAM access block includes a process of receiving a SDRAM read or write signal and a destination address from the regulator block to generate an SDRAM control signal acceptable to the SDRAM, and simultaneously write or read data to or from the SDRAM.

In the present invention, the predetermined time is preferably 2.56 μs,

The process of setting initial values of the SDRAM when the first power is turned on,

Generating an initial value in the power-on initialization block;

SDRAM write to send the initial value generated in the process to the SDRAM access block to write to the SDRAM; And

And transmitting a signal to the regulator block to prevent the processor from accessing the SDRAM during the power-on initialization state.

The method of determining whether to receive the SDRAM write request or read request signal and to send the SDRAM access block to the SDRAM access block includes the order of SDRAM read / read sequentially from the signal from the processor access block after the processor access block that finally performed the SDRAM write or read. It is desirable to process the first encountering processor access block by checking for a write request signal.

Hereinafter, the configuration and operation principle of the present invention with reference to the accompanying drawings in detail as follows.

2 is a diagram illustrating an SDRAM controller structure according to the present invention. Referring to FIG. 2, the SDRAM controller receives a signal from the processor and sends n processor connection blocks 20a, 20b, having a function of sending a signal requesting SDRAM read / write (R / W) to the regulator block 24. 20c) and n write memory (22a, 22b, 22c) connected to each processor access block temporarily holding data to write in SDRAM and SDRAM access control signals from n processor access blocks are selected and one of them is selected. A regulator block 24 that functions to send to the SDRAM access block 26, a refresh interrupt generator 28 that generates a signal for refreshing the SDRAM every 2.56us, and a power on. A power-on initialization block 30 for generating initial values that should be written to the SDRAM at the time and an SDRAM connection block 26 for generating a signal for writing or reading to the SDRAM and for connecting data. .

SDRAM is a type of memory designed to operate at a high speed clock while having DRAM characteristics. The data can be transferred by sharing the memory between the processor and the processor or a plurality of peripheral control devices. In this case, multiple processors or controllers simultaneously require access to the SDRAM, which is an SDRAM controller that eliminates this situation and eliminates processor time loss that may occur during the sequential and coordination of all processors. Will be described.

When the power is turned on for the first time, the initial values of the SDRAM should be set. The power-on initialization block generates this initial value and sends it to the SDRAM access block for writing to SDRAM, and sends a signal to the regulator block to prevent the processor from accessing the SDRAM during power-on initialization. And, because of the characteristic of SDRAM, play should be done once every 2.56μs. For this purpose, the play interrupt generator block turns timer to generate an interrupt every 2.56μs so that the regulator block can perform the play first.

Assume that n processors or control devices share SDRAM data as shown in FIG. 2. At this time, each processor communicates with the processor access block in the SDRAM controller. Each processor transmits a start address and byte length to be written to the processor access block when reading data, and a start address and byte length to be written and data to be written to the processor access block when writing data. When the data is written, the processor access block temporarily stores the data in the write memory block, transmits a signal requesting the SDRAM write connection to the coordinator block, and sends a signal to the processor indicating that the write is completed. To do this. When reading data, send a signal to the regulator block requesting an SDRAM read connection and wait for the read signal to be accepted and the read data to be transferred. When data is transmitted, it is transmitted to the processor and the data read connection is completed by transmitting a signal indicating that the data read connection of the processor is completed.

The coordinator block receives SDRAM write request or read request signals from each processor access block and decides which one to send to the SDRAM access block. The decision method is basically processed by the round robin method as shown in the flowchart of FIG. 3. That is, the first processor access block is processed by checking whether there is an SDRAM read / write request signal in order from the signal from the processor access block next to the processor access block that finally performed the SDRAM write or read. If the decision thus made is the processor's SDRAM write signal, the regulator block reads the first address for the SDRAM write and the data to be written from the temporarily written write memory and transfers it to the SDRAM access block. If it is a read signal, it transfers the address for reading to the SDRAM access block, waits for data to come in, and then sends it to the corresponding processor access block.

The SDRAM access block receives the SDRAM read or write signal from the power-on initialization block or regulator block and the destination address to produce an SDRAM control signal that can be accepted by the SDRAM, while simultaneously writing or reading data into the SDRAM. The detailed operation of this part is done according to the timing chart in the SDRAM databook.

While the invention is susceptible to various modifications and alternative forms, the disclosure thereof has been described with reference to specific embodiments only. It is to be understood, however, that the present invention is not limited to the specific forms referred to in the specification, but rather that the invention is intended to cover all modifications, equivalents, and substitutions within the spirit and scope of the invention as defined by the appended claims. It should be understood to include.

The present invention operating as described above provides a function to read or write data from and to the SDRAM without conflicting with each other when a plurality of processors or control devices share a single SDRAM and internally writes a write memory associated with each processor. In other words, by sending the completion signal for the write signal of each processor more quickly, the processor can reduce the waiting time.

Claims (6)

N processor access blocks having a function of receiving a signal from a processor and sending a signal requesting SDRAM read / write to a regulator block; N write memories connected to each processor access block to temporarily hold data to be written to SDRAM during an SDRAM write operation; An adjuster block for receiving SDRAM access control signals from the n processor access blocks and selecting one of the signals to be sent to the SDRAM access block; A reproduction interrupt generator for generating a signal for reproducing the SDRAM every predetermined time; A power-on initialization block that generates initial values that should be written to the SDRAM when the power is turned on; And And said SDRAM connection block for generating signals for writing to or reading from SDRAM and for connecting data. 2. The SDRAM controller device of claim 1 wherein the predetermined time is 2.56 μs. Setting initial values of SDRAM when power is first turned on; The playback interrupt generator block may include: generating a interrupt by turning a timer every predetermined time so that playback may be performed first in the regulator block; when n processors or control devices share SDRAM data, each processor sends and receives signals to and from a processor access block in the SDRAM controller; Transferring the start address and byte length to be written to the processor access block when reading data, and transmitting the start address and byte length to be written and data to be written to the processor access block when writing data; When data is written in the above process, the processor access block temporarily stores the data in the write memory block, transmits a signal requesting the SDRAM write connection to the coordinator block, and transmits a signal indicating that writing is completed to the processor. To allow others to do other things; When reading data, the process access block sends a signal requesting an SDRAM read connection to the coordinator block, waits for a read signal to be accepted and read data to be transmitted, and then transfers the data to the processor when the data is transmitted. Completing a data read connection by transmitting a signal indicating that the data read connection is completed; A regulator block receiving an SDRAM write request or read request signal from each processor access block determines which one to send from the processor access block to the SDRAM access block; If it is determined in the process that the processor's SDRAM write signal, the regulator block reads the first address for SDRAM write and data to be written from the temporarily written write memory to the SDRAM access block; If it is determined that the processor is an SDRAM read signal, the regulator block transmits an address for reading to the SDRAM access block, waits for data to come in, and then transfers the data to the corresponding SDRAM access block when data comes in; The SDRAM access block includes a process of receiving an SDRAM read or write signal from a regulator block and a destination address to generate an SDRAM control signal acceptable to the SDRAM, and simultaneously performing a function of writing or reading data to the SDRAM. Way. 4. The method of claim 3, wherein said predetermined time is 2.56 mu s. The method of claim 3, wherein the initial values of the SDRAM are set when the first power is turned on. Generating an initial value in the power-on initialization block; SDRAM write to send the initial value generated in the process to the SDRAM access block to write to the SDRAM; And And sending a signal to a regulator block to block the SDRAM connection of the processor during the power-on initialization state. 4. The method of claim 3, wherein the method of determining whether to receive the SDRAM write request or read request signal and transmit the coming from the SDRAM access block is from a processor access block after the processor access block that finally performed the SDRAM write or read. An SDRAM access method that processes a processor access block for the first time by checking whether there is an SDRAM read / write request signal in order from a signal.