JPS60151894A - Refresh circuit of dynamic ram - Google Patents

Abstract

PURPOSE:To simplify constitution of a leased refresh circuit which is provided in order to refresh memory consisting of a dynamic RAM to require regular refresh by providing a means to refresh a dynamic RAM by utilizing a controller. CONSTITUTION:An exclusive circuit 22 decides competition of CPU1 access along with a refresh action of a memory consisting of dynamic RAMs and used at the time of generation of a refresh address, etc. A dynamic RAM refresh circuit is constituted so that competition can be decided and a refresh address can be generated by utilizing a function which a DMAC3 has in order to transfer data between an I/O 6 and a memory 4 without mediation of the CPU1. An exclusive circuit to be used at the time of refreshing the dynamic memory 4 consisting of dynamic RAMs is only a refresh counter 5, and others can share the DMAC3 and a bus arbitor 2 which are necessary to transfer data directly between the I/O 6 and the dynamic memory 4.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a refresh circuit that performs a refresh operation of a dynamic RAM that is used in a computer system and the like and which requires periodic refresh in order to retain its memory contents. be.

[Background of the invention]

Figure 1 shows the configuration of a control unit using a conventional dynamic RAM refresh circuit, and the data held inside the dynamic memory 4 configured by the dynamic RAM is connected to the CPU without intermediary between the CPUI. The data is written or read by the direct memory access controller 3 (hereinafter referred to as DMAC) which performs the process of directly transferring data between the dynamic memory 4 and l106 (hereinafter this operation is referred to as access). At the time of this access, a signal instructing memory access is given to the dynamic memory 4 via the signal line 18, and the dynamic memory 4 performs a memory access operation based on this signal to store data or to retrieve data that has already been stored. The signal is sent onto the signal line 22. On the other hand, the data stored in the dynamic memory 4 is held [2
In order to continue, the timing of the refresh request signal periodically sent out via the signal line 15 by the refresh counter 5 is adjusted in the conflict determination section 9, and sent out to the dynamic memory 4 via the signal line 17 as a refresh signal. . In response to this refresh signal, the dynamic boxes A and M that make up the dynamic memory 4 perform a refresh operation based on the address generated by the refresh address generator 25, which counts up every time a refresh operation is performed, and the data stored inside is refreshed. Continue to hold.

Since a dynamic RAM cannot perform a memory access operation and a refresh operation at the same time, the conflict determination unit 9 does not immediately send a refresh request to the dynamic memory 4 even if a refresh request is sent from the refresh counter 5 during a memory access operation. The timing is adjusted so that a refresh request is sent after the access operation is completed, and when a memory access request is sent from the decoder 16 during the refresh operation, the memory access signal is not sent immediately and the memory access signal is sent to the CPU 1 or T) MAC.
Wait for the completion of the refresh operation while sending a signal to extend the incomplete memory access operation in step 3 via the signal line 19, and after the refresh operation is completed, send a memory access signal and allow the CPUI or DMAC 5 to access the memory. The timing is adjusted to complete the operation.

As described above, the conventional dynamic RAM refresh circuit 100 requires a refresh counter 5, a refresh address generator 25, and a conflict determination section 9, and requires a large number of ICs and a large mounting area on the board. Since a complicated circuit such as a conflict determination section 9 is required, the dynamic RAM refresh circuit is expensive and complicated.

In addition, to simplify the refresh circuit configuration, the CPU
A refresh method is known in which the CPU 1 performs refresh by accessing the dynamic memory periodically using cyclic addresses. This method uses C
The PUI performs so-called interrupt processing in response to a refresh request signal from the refresh counter 5, temporarily interrupting the processing being executed, and performs a refresh operation.

Therefore, in a system having a plurality of dynamic memory units 100 as shown in FIG. 2, refresh requests from each dynamic memory unit 100 are complicated on the CPU.
Since this is processed by one CPU, as the number of dynamic memory units 100 increases, most of the processing performed by the CPU will be spent accessing memory for refresh purposes, and the original processing of the system will not proceed at all. It has the disadvantage that it can sometimes disappear. 1 every 2ms
In a system where the dynamic memory 4 is configured using a dynamic RAM that requires 28 refreshes, and a CPU that takes 1 μs for one memory access, if a refresh method by the CPU is used, a simple calculation shows that the dynamic memory 4 is a dynamic RAM that requires 16 refreshes. With memory section 100, C
The PU only performs refresh operations, and the original processing of the system does not proceed at all. In order to eliminate this drawback, each dynamic memory section 100 must independently
It is necessary to perform refresh without using the PU, and a conventional expensive and complicated dynamic RAM refresh circuit has to be used, making a system having a plurality of dynamic memories expensive.

Note that other circuit configurations will be explained in the embodiments of the present invention.

[Purpose of the invention]

An object of the present invention is to solve these problems of conventional dynamic RAM refresh circuits and to provide a dynamic RAM refresh circuit that is inexpensive and has a simple configuration.

[Summary of the invention]

The present invention provides a dedicated circuit for determining access conflicts with the CPU and generating refresh addresses, etc., associated with the refresh operation of a memory composed of dynamic RAM.
In order to transfer data between Ilo and memory without the intervention of the CPU, I) configure a dynamic RAM refresh circuit to use the functions of the MAC to determine conflicts and generate refresh addresses. The point is that the cinema is important. .

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. Third
The figure shows the configuration of a control section using an embodiment of the present invention. C
The PUI controls the entire control unit. The dynamic memory 4 is composed of a dynamic RAM that requires periodic refreshment to maintain its memory contents, and stores data transmitted and received via the peripheral device 7 and the DMAC bus 22, as well as programs for operating the CPUI. Store data. The DMAC 5 transmits and receives data stored or to be stored in the dynamic memory 4 to the peripheral device 7 via the DMAC bus 22 and l106 without the intermediary of the CPUI. Continuous memory addresses and their read/write control signals, which perform direct data transfer processing via the DMAC bus 22, and a response to one of the Ilo's for multiple Ilo's requesting data transfer. It has a function of generating signals and read/write control signals, and sends separation request signals H1'l and EQ through the signal line 11 to instruct the bus arbiter 2 to disconnect the DMAC bus 22 from the CPU bus 21 during data transfer. D
After confirming the separation completion signal HACK sent from the bus arbiter 2 via the signal line 12 indicating that the MAC bus 22 has been separated from the CPU bus 21, the data transfer operation is performed. The controller 106 transfers data to the peripheral device 7 via the signal line 23. The decoder 8 includes the dynamic memory 4
is accessed by the CPUI or DMAC 5 based on the signal on the DMAC bus 22, and when the refresh request signal DACKI is not being sent, sends a memory access signal to the dynamic memory 4 via the signal line 16. do. The refresh counter 5 detects the periodic refresh period of the dynamic memory 4 and sends a refresh timing signal via the signal line 15.
) Send to MAC3. The bus arbiter 2 receives the D signal from the CPU bus 21 sent from the CPU via the signal line 20.
Connection request signal to MAC bus 22 CREQ -? l)
Separation request signals HIf and E for the CPU bus 21 and DMAC bus 22 sent from the MAC 3 via the signal line 11
Q controls the connection and separation of the CPU bus 21 and r) MAC bus 22, receives the C) tEQ signal, and sends a connection completion signal ratio DY to the CPU 1 when the CP[J bus 21 and DMAC bus 22 are connected. Sending out via line 10, C
I (CPU bus 21 and L' from EQ double signal) When MA and C bus 22 are connected, Hl (when EQ double signal is received, CPU bus 21 and DMA until CRBQ signal ends)
The C bus 22 is continued to be connected, and after the CH and EQ double signals are completed, the CPU bus 21 and the DMAC bus 22 are separated, and the separation completion signal HACK is sent to the DMAC 5 via the signal line 12, and conversely, the HfLEQ signal is CPU bus 2
When the CPU bus 21 and the DMAC bus 22 are separated (9), the HA CK signal is sent, and even if the C and REQ signals are received when the CPU bus 21 and the DMAC bus 22 are separated by the HREQ signal, the HREQ signal ends. Continue to separate the CPU bus 21 and DMAC bus 22 until H
After the REQ signal ends, the CPU bus 21 and DMAC bus 22
is connected and operates to send R and DY multiplied signals. I)M
The AC bus 22 is used to connect the DMAC 5, the bus arbiter 2, the decoder 8, the dynamic memory 4, and the 1106, and to transmit and receive read/write control signals, addresses, data signals, and the like. The CPU bus 21 is used to connect the CPU 1 and the bus arbiter 2 and send and receive control signals, and the signal line 10
, 11, 12, 13, 14, 15° 16, 17, 19 are used for transmitting and receiving the various signals mentioned above. The DMAC 5 constituting this embodiment is generally known as an LSI, and the configuration of the bus arbiter 2 is also common in control circuits having I) MAC, so a detailed explanation thereof will be omitted.

Next, the refresh operation in the control section having a one-piece configuration will be explained using FIG. 4. Refresh (10) Refresh timing signal DREQ1 from counter 5
is input to I) MAC3 via the signal line 15, J
) MAC3 sends the H1tEQ signal to the bus arbiter 2 via the signal line J1. The two bus arbiters that received the HRE Q signal perform the operations described above, and after confirming that there is no connection request for the CPU bus 21 of CPU 1 and MAC bus 22, or that the connection request has been completed, the CPU buses 21 and 1
) Separate the MAC bus 22 and send the HACK signal to the signal line 12.
r) to MAC3. T) MAC3 is HA
, J,)R, upon receiving the CK signal, sends out a response signal 1)ACKl to EQIVc via the signal line 17. This l) A CK signal is input to the dynamic memory 4 as a refresh signal for the dynamic memory 4, and
By inputting it to the decoder 8 as a masking signal to prevent the generation of a memory access signal, and setting the memory address to which data is transferred by I) MAC 3 to DREQ1 as the address to which the dynamic memory 4 is allocated, A refresh signal and a refresh address input (11) are input to the dynamic memory 4, and the DMAC bus 22 is connected to the CPU bus 21.
Since the DMAC 5 only performs one data transfer operation at a time, this refresh operation does not conflict with memory access, and the dynamic memory 4 is refreshed periodically. .

Therefore, by adopting this configuration, dynamic R
The dedicated circuit used to refresh the dynamic memory 4 composed of AM is only the refresh counter 5, and all others are necessary for direct data transfer between Ilo and the dynamic memory 4.
The AC 3 and the bus arbiter 2 can be shared, and a dedicated circuit for refreshing the dynamic memory can be provided at low cost and with a simple configuration.

When a dynamic memory section using this dynamic memory refresh circuit is used as each dynamic memory section of a system having multiple dynamic memory sections, the refresh operation is performed independently in each dynamic memory section. Even if the number of dynamic memory refreshes increases, there is no longer a situation where the original processing of the system stops progressing at all, unlike when refresh is performed by the CPU, and the dedicated circuit for dynamic memory refresh is inexpensive and has a simple configuration. Therefore, a system having a plurality of dynamic memory sections can be provided at a lower cost than configuring a refresh circuit using the conventional method.

〔Effect of the invention〕

According to the present invention, the refresh-only circuit provided for refreshing the memory composed of dynamic RAM that requires periodic refreshing has a very simple configuration, and the number of ICC chips occupies less space on the board.
Furthermore, since it is small, an inexpensive refresh circuit can be provided.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of a control section using a conventional Noriflex circuit, and Fig. 2 is a circuit diagram of a control section of a system having multiple dynamic memories using refresh by the CPU.
FIG. 3 is an embodiment of the present invention (13) A circuit diagram of a control section using a certain refresh circuit, and FIG. 4 is an operation timing diagram of the refresh circuit which is an embodiment of the present invention. 1...CPU12...Bus arbiter, 3...DM
AC14...Dynamic memory, 5...Refresh counter, 8...Decoder, 10, 11, 12,
15゜1.6, 17.20...Signal line, 21...C
PU bus, 22...DMAC bus. Agent Patent attorney Akio Takahashi (14)

Claims (1)

[Claims] 1. Directly transfers data between the CPU, which controls the entire control unit, the dynamic RAM, which requires periodic refresh to maintain memory contents, and the memory and peripheral I10 without the mediation of the CPU. A controller that controls processing and a signal line used for data transfer when the controller directly transfers data between the memory and the peripheral I10 are separated from the control of the CPU and placed under the control of the controller. A control unit circuit comprising a bus arbiter and configured as a memory to which the controller transfers data using the dynamic RAM, characterized in that the dynamic RAM has means for refreshing the dynamic RAM using the controller. refresh circuit.