KR19980086988A - Spread spectrum signal reception method and spread spectrum signal reception apparatus - Google Patents

Abstract

The present invention relates to a spread spectrum signal receiving method for demodulating a received signal by performing a correlation operation with a spreading code, the method comprising the steps of: Power.

Solution

A spreading code and a baseband component are correlated with each other when performing a correlation operation between a spread spectrum signal baseband component and a spreading code so that the timing relationship between the spreading code and the baseband component is 1/2 Correlation arithmetic operation is performed at different timings, and a result of the correlation operation at a timing point whose timing relationship is 1/2 or less is estimated by using each calculation result.

Description

Spread spectrum signal reception method and spread spectrum signal reception apparatus

Technical field

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a spread spectrum signal reception method and a spread spectrum signal reception apparatus used in, for example, a communication system using a direct spread code division multiple access (DS-CDMA) system.

Conventional technology

Spread spectrum (SS) communication is a communication that spreads the spectrum of an information signal to a wide band using a spreading code. The communication is a direct sequence (DS), a frequency hopping (FH) Time spreading (TH) and the like. Among them, the direct diffusion is a method of performing spread spectrum by accumulating a spreading code in an information signal. The spreading ratio of the spectrum is determined by the speed ratio between the code rate of the spreading code and the information signal rate. This ratio is called spreading factor or processing gain (dB value of spreading factor).

SS communication has various advantages such as resistance to interference, coherence, low interference or low interference, resistance to multi-path fading, and multiple connectivity. These advantages are very favorable properties in mobile communication, and therefore mobile communications have been actively studied using SS communication, and practical use has also been carried out. In SS communication, a method of identifying a mobile station or a base station by a spreading code used for spread spectrum is adopted as a connection method between a mobile station and a base station. This connection method is a Code Division Multiplex Access (CDMA) .

Figs. 15 and 16 show the performance analysis of an all-digital BPSK Direct-Sequence Spread-Spectrum IF Receiver Architecture by BYYoung et al. (IEEE Jounal of Selected Areas in Communications, Vol. 11, No. 7, pp. ). ≪ / RTI > Fig. 15 shows a transmitter and Fig. 16 shows a receiver. Although the signal processing portion inherent to the spectrum spreading can be realized by an analog circuit, it can be realized by a digital circuit as in this conventional example in terms of circuit reliability, non-conditioning, hardware scale, mass productivity There are many.

The transmitter of Fig. 15 will be described. Input data (Data Input) corresponding to information data is input to a data spreader (1). The data spreader 1 performs data encoding (processing such as speech coding, error correction coding, and framing) in a data encoder 2, outputs coded data (symbols) (PN generator) 4 in the spreading code generator 3 and becomes a data diffusion unit output. The output of the data spreader is input to a modulator (5) and is multiplied and carrier-modulated by a multiplier (7) and a carrier given by a local oscillator (RF OSC) The output of the multiplier 7 is amplified by the amplifier (AMP) 9 and becomes a high-frequency output (RF 0putput) after the modulation component is extracted in the band-pass filter (BPF) do.

In addition, in order to distinguish between the information data and the data encoded by the data encoder 2, the encoded data is referred to as a symbol. The symbols are signal formats such as BPSK (two-phase digital phase modulation), QPSK (quadrature digital phase modulation), and QAM (quadrature amplitude modulation) according to the carrier modulation scheme.

Next, the receiving section of Fig. 16 will be described. The high frequency signal is received by the antenna 11 and becomes a high frequency input RF Input and the received signal component is extracted from the BPF 12 and given to the multiplier 13 in the local oscillator RF 0SC 14 The baseband received signal is obtained by performing quasi-synchronous detection by extracting a low-frequency component by a low-pass filter (LPF) Here, quasi-synchronous detection refers to detection in which a deviation component remains in the baseband received signal because there is a deviation between the carrier wave of the reception local oscillator 14 and the carrier wave of the reception signal. Usually, the local oscillator 14 having sufficient accuracy to compensate by signal processing is used, and the influence of the deviation is often such that the quasi-synchronized detection signal rotates sufficiently slowly compared to the symbol interval. In this case, synchronous detection is realized in such a manner that the phase difference between carrier waves is detected to perform phase compensation.

Next, the quasi-synchronous detection signal is gain-controlled by an automatic gain controller (AGC) 16 so that the average power is constant, and becomes a digital signal through an analog-to-digital (A / D) The A / D converted baseband received signal is input to an SS receiver (Spread Spectrum IF Receiver) 18 to demodulate the data. The SS receiver 18 includes a demodulator 19, a PN acquisition loop 20, a PN tracking loop 21, a data decoder 22). SS communication uses a different spreading code for each channel to distinguish it from other channel signals. Therefore, in order to demodulate the SS signal, it is necessary to extract the desired component by multiplying the same spreading code as the spreading code used in the transmitting side . It is also necessary to match the timing of acquiring the spreading code to the timing of the received signal.

For this reason, the SS receiver 18 first acquires the synchronization timing in the synchronization acquisition unit 20. More specifically, the synchronization timing is detected by changing the phase of the spreading code. Next, the synchronous timing section 21 tracks the synchronization timing obtained by the synchronous acquisition section 20. Specifically, the timing of the spreading code to be multiplied is controlled so that the timing of the received signal coincides with the timing of the spreading code to be multiplied. The timing trace is necessary in order to cope with a temporal fluctuation of a communication path or a deviation between transmission and reception of a clock generating a spread code. In the demodulation unit 19, the same spreading code as that on the transmission side is added to the baseband reception signal according to the timing given by the synchronization tracking unit 21 and integrated over the symbol duration. By this integration result, the symbols are demodulated according to the respective modulation schemes. The demodulator 19 also performs an operation of estimating and compensating for the transmission / reception carrier frequency deviation (phase difference) included in the baseband reception signal at the same time. The demodulation symbol is decoded (frame decomposition, error correction decoding, voice decoding) by the data decoder 22 and the transmission information is restored and sent out as output data (Data Output).

An operation for obtaining a spreading code for a received signal in the demodulator 19 is referred to as despreading and an operation including up to an integration operation over a symbol duration is called a correlation operation. The circuit for performing the correlation operation is called a correlator. Since the desired signal component is obtained by the correlation characteristic of the code in the CDMA system, the correlation calculation is used not only in the demodulating unit 19 of the symbol but also in the synchronous acquisition unit 20 and synchronous tracking unit 21. [ Therefore, it can be said that the correlation operation is a basic operation operation in the demodulation process of the SS signal. The method of performing this correlation operation is roughly divided into an active correlation method and a manual correlation method. The difference between the two is due to the active or passive method of assigning the winning spreading codes.

17 and 18 show a conventional configuration example of the active correlation method and the manual correlation method. 17 is a conventional configuration by the active correlation method shown in "Digita1 Communications" (Second Edition Chapter 8, McGraw-Hill Company, 1989) written by JG Proakis and the portion surrounded by the dotted line corresponds to the correlation computing unit 25 do. In the active correlation method, a baseband received signal (Rx Baseband Signal) is multiplied with a spreading code generated by a spreading code generator (PN Generator) 26 to integrate a multiplication result over a symbol duration Tb to perform a correlation operation . This correlator 25 is referred to as a sliding correlator. The spreading code input to the multiplier 27 is given in time series and the integration time of the integrator 28 coincides with the symbol duration. The integrated symbol is output at the timing of the sample rate clock 31 through the sampler 30. [ The generation timing of the spreading code is controlled by a chip rate clock (29). Figure 17 shows a simple circuit configuration, while only one correlation value is obtained for the symbol duration. That is, correlation values are output at symbol intervals.

Fig. 18 shows a conventional basic configuration by passive correlation. This circuit configuration is called a matched filter. Particularly in the case of a digital circuit, it is called a digital matched filter (DMF). In the figure, a portion surrounded by a dotted line corresponds to the correlation computing unit 35. [ In the case of the matched filter, the baseband received signal (Rx Baseband Signal) is sampled at each spreading code rate (chip rate) and input to the shift register 36. The baseband reception signals stored in the stages of the shift register 36 are respectively input to the multiplier 37 and multiplied with spreading codes PN1 to PN7 and 38 which are stored in a fixed manner, ) And added to the other winning results.

The spreading code is fixed for at least one data duration, unlike the case of the active correlation. In the case of Fig. 18, correlation calculation is performed in the case where one piece of data is spread by seven-chip spreading codes (PN1 to PN7). However, the spreading code to be multiplied with the first shift register sample is always spread (PN7). In the configuration using the matched filter, since one correlation result is outputted every time one received sample is inputted (that is, at the chip interval), the calculation speed is higher than that of the sliding correlator and the calculation efficiency is improved as the sequence length is longer . However, power consumption and hardware scale increase. This tendency becomes remarkable as the code length of the spreading code for spreading the transmission symbol becomes longer (the spreading rate becomes larger).

As described above, the correlator for performing the correlation operation in the receiver of the SS signal mainly has two kinds of correlators, and any one of them is selected in relation to the circuit scale, power consumption and operation speed. The configuration of the symbol demodulation unit 19 in FIG. 16 is the same as that in FIG. 17 and FIG. 18, and the correlator output may be sampled at the timing at which the correlation calculation result is obtained. The synchronization acquiring unit 20 and the synchronization tracking unit 21 perform synchronization acquisition and synchronization tracking using the time correlation characteristics of spreading codes.

The time correlation characteristic means that when the code timing of the spreading code to be multiplied in the correlation calculation coincides with the timing of the spreading code included in the baseband received signal, the time correlation characteristic becomes a large level as a result of the correlation calculation, Characteristics. FIG. 19 shows the time correlation characteristic of the spreading code in an enlarged manner in FIG. In both drawings, the abscissa represents the time, the ordinate represents the correlation value, and the case where the data is not modulated is shown. In the case of symbol modulation by BPSK, the polarity of the correlation value also changes in accordance with the polarity of the transmission symbol.

In Fig. 19, the correlation value has a value only in the vicinity of " 0 " Of course, this characteristic depends on the nature of the spreading code, and a spreading code is generally used which can be regarded as "0" although it has some value even if the time difference is not near "0". Also, T _p is the sequence period of the spreading code. When a spreading code having the same correlation characteristic as that of the same drawing is used, the synchronization acquiring unit 20 performs the correlation calculation on the assumption of the timing of the spreading code. As shown in the figure, when the assumed timing is correct, a large correlation value is obtained. When the assumed correlation value is not correct, the correlation value is not obtained, so that the timing can be detected by the magnitude of the correlation value.

20 shows an example of the correlation characteristic of the time difference "0" neighborhood spreading code. If the spreading code has sufficiently arbitrary characteristics, the correlation characteristics of this region are, on average, equal to the impulse response given by the synthesis characteristics of the waveform-shaping filter. That is, when Nyquist transmission is performed on the chip waveform, the impulse response of the Nyquist waveform becomes a correlation characteristic in the vicinity of " 0 ". Therefore, as the timing difference becomes larger, the correlation value decreases, and when the timing difference becomes one chip interval Tc, the correlation value output becomes " 0 ". The synchronism tracking unit 21 performs synchronous tracking so that the correlation value for symbol demodulation always becomes the maximum, that is, the timing error becomes small.

Next, the configuration of the synchronous acquisition unit 20 will be described. First, as a conventional example of a method of acquiring a synchronization by a sliding correlator, there is a configuration shown in FIG. 21, for example. This is the method disclosed in PCT International Publication No. WO96 / 04716 (PCT / US95 / 08659). A portion surrounded by a dotted line in the figure is the correlation calculating unit 41. [ In this example, the transmitting side shows a synchronization acquisition circuit for a signal in which transmission symbols are spread by QPSK using an in-phase-axis spreading code and two kinds of spreading codes of orthogonal spreading codes. That is, assuming that the transmission symbol is d, the in-phase axis spreading code is Pi, and the orthogonal axis spreading code is Pq, the baseband transmission signal Tx is

Tx = d? (Pi + jPq)

Lt; / RTI > Where j is an imaginary unit. Also, the transmission symbol and the spreading code are all time functions, and the transmission symbol is a time function that changes the spreading code every chip interval for each symbol interval, but is omitted here.

The baseband reception signal is a semi-synchronous detection signal Rx output through an antenna 42 and a receiver 43, and includes a phase difference (phi)

R _x = d 揃 (Pi + jPq) 揃 exp (jφ)

= d? (Pi + jPq) (cos? + jsin?)

. The real component of Rx is the inphase component reception signal and the imaginary component is the orthogonal component reception signal and is input to the correlation operation part 41. [ Here, in the QPSK despreader 41A, Pi 'and Pq' assuming the timings of Pi and Pq inputted from the spread code generator 44 with respect to the quasi-synchronous detection signal Rx are denoted by Rx × (Pi'-jPq '), And an adder / subtracter. Next, in the coherent accumulators 41B and 41C, the correlation power is output by taking the integral of the real and imaginary components over the symbol interval and taking the square sum of the integral results as the square-sum unit 45, respectively. do. That is, if the timing of Pi and Pq coincides with the timing of Pi 'and Pq', Pi = Pi 'and Pq = Pq', so that the QPSK despreader outputs are real and imaginary components of d · (cosφ + jsinφ) d ² is obtained to obtain the received symbol power. When the timings do not coincide with each other, a correlation power of a small level is obtained due to the randomness of the spreading code.

Since the timing of the spreading code is unknown in the step of acquiring the synchronization, the correlation power with the received signal is obtained at the timing assumed at the receiving side, and the synchronization acquisition of the spreading code is completed when the output level is higher than a predetermined level . In addition, the use of the correlation power as the detection of the synchronization acquisition is difficult to grasp the phase? Of the carrier wave at the stage of acquisition of the synchronization, and the correlation amplitude of the reception signal in the case where data modulation is performed, The polarity changes randomly and is canceled by the averaging operation.

Further, in order to reduce the influence of noise, it is often the case that the correlation power obtained at the same timing is usually averaged and the acquisition of the synchronization is determined by the average correlation power. In FIG. 21, the correlation power obtained for each symbol interval in the averaging unit (non-coherent accumulator) 46 is integrated for a predetermined time (number of times) and averaged to reduce the influence of noise. 47, and is compared with the threshold level, and the comparison result is transmitted to the control unit (Search Controller) 48 to perform the synchronization acquisition determination. If it is determined to be a synchronous acquisition, synchronization tracking and symbol demodulation are performed. However, if synchronization acquisition is incomplete, the same operation is repeated assuming a new timing.

The sliding correlation method is simple in circuit configuration, however, since only one correlation value is obtained in the symbol interval, it takes a lot of time to acquire the motions. Therefore, a plurality of synchronization acquisition circuits are provided to shorten the synchronization acquisition time, a plurality of integration times and threshold levels for averaging are set, primary evaluation is performed with a short integration time and a low threshold level, If the probability is high, a second evaluation is performed at a longer integration time.

When the reception timing is changed to the chip interval, only the correlation value of the chip interval precision is obtained. Therefore, when the accurate reception timing is, for example, (n + 0.5) chips, And the chip phase (n + 1), only the correlation power according to the correlation value shifted by 0.5 chip from the correct timing is obtained, so that the acquisition performance deteriorates. That is, although timing is close, timing detection becomes difficult due to a low correlation value. In order to cope with this problem, it is often the case that the reception timing is subjected to the synchronization acquisition test with 0.5 chip intervals ([1/2] Tc) precision, that is, changing the assumption timing by 0.5 chips.

An example of the method using the digital matched filter of the synchronous acquisition circuit is shown in Fig. 22, for example. This is described in "Journal of the Institute of Electronics, Information and Communication Engineers, Vol. 69-b, No.11, pp.1540-1547," Spectrum Diffusion Communication Device for Satellite Communication Using Direct Matching Filter for Data Demodulation "(Hamamoto et al. It is the composition shown. The digital matched filter output giving the result of the correlation operation on the in-phase signal and the orthogonal axis signal is added to the adder 51 after passing through the squarers 50A and 50B, respectively. In Fig. 21, correlation power is given for each symbol interval, whereas in Fig. 22, [1/2] is given for each chip interval (two constituent methods are given, not one for each chip). That is, for example, when the PN code period coincides with the symbol duration, in the case of FIG. 21, the correlation power is obtained at a resolution of [1/2] chip interval by observing the square sum of the symbol intervals. In addition, the averaging operation by the cyclic addition is performed by the recursive integrator 52, and the influence of the noise is reduced. This cyclic adder 52 is composed of an adder 52A, a frame memory 52B for 1 PN frame and a multiplier 52C for multiplying the output of the adder 52A by a predetermined coefficient and outputs the multiplied output to an adder 52A ) To realize cyclic addition. Averaging operation is performed without confusing the correlation power between different sign phase timings by storing the result of cyclically adding the correlation power obtained every [1/2] chip interval in the frame memory in symbol period units. The maximum value hold unit 53 holds the point at which the maximum average correlation power is given from the frame memory 52B to set the reception timing.

In order to prevent the deterioration of the synchronization acquisition performance due to the correlation value verification of the chip interval precision as in the sliding correlation, the digital matched filter of Fig. 22 is the same as the corresponding portion of Fig. 18, The configuration shown in Fig. 23 is adopted.

In Fig. 23, the portion surrounded by a dotted line is the correlation calculating section 35A. That is, the input to the digital matched filter is sampled at twice the PN clock (2 times oversampling per chip), and the PN code 38 to be multiplied with the input signal is made to correspond to two consecutive samples per chip. In this way, a correlation value of one sample per [1/2] chip is output to improve the accuracy of acquisition of synchronization.

The correlation calculation results of FIG. 23 are shown in FIGS. 24A and 24B. 24A is a result of normal correlation calculation. Assuming that S ₀ is a correlation calculation result at an appropriate sample timing, the correlation calculation result at the adjacent sample timings (S _-1 , S ₁ ) is smaller than S ₀ . In the case of the configuration of FIG. 23, since the received samples are input at twice the chip rate, the correlation calculation result is also obtained at twice the chip rate. However, since the correlation results are all added after the same code bits are multiplied over the two samples in the spread code, the result of the correlation operation performed twice as high as the chip rate as shown in Fig. (FIG. 24 shows a case in which averaging is further divided into two). That is, the maximum correlation value A ₀ is the correlation value S ₀ of the sample input before [1/4] Tc with respect to the synchronization timing and the correlation value S ₁ ) is added.

For the theoretical analysis of this method, Kataoka et al., Which also includes the influence of the transmission and reception waveform shaping filters, have proposed the "Performance-Soft Decision Digital Matched Fi1ter in Direct-Sequence Spread-Spectrum Communication Systems" (IEICE Transactions, Vol. E74 , No. 5, pp. 1115-1122, May 1991). According to this, the deterioration is slight in the S / N ratio at the optimum sample point, but the deterioration is slight (0.06 dB in the case of an equally-divided roll-off rate of 40% and a root Nyquist filter) It can be confirmed that the amount of deterioration of S / N (signal-to-noise power ratio) due to the timing error is reversely reversed at a portion where the timing error is large (about 1/2 Tc).

Next, a conventional configuration example of the synchronization trace section will be described. The synchronization trace section is based on a configuration called a code synchronization loop (DLL). Figs. 25 and 26 show a conventional code synchronous loop by a sliding correlator, Fig. 25 shows a configuration called an asynchronous DLL, and Fig. 26 shows a configuration called an inverse modulated synchronous DLL. In the drawings, the parts surrounded by dotted lines are the correlation calculating units 58, 59, 70, 71, and 72. FIG. 25 shows an example of an asynchronous DLL, and RDGaudenzi et al., "A Digital Chip Timing Recovering Loop for Band-Limited Direct-Sequence Spread-Spectrum Signals" (IEEE Transactions on Communications, Vol. 41, No. 11, pp. 17601769 , Nov. 1993). In this figure, a complex baseband reception signal (in-phase axis received signal and orthogonal axis received signal) is waveform-shaped by a low-pass filter LPF 55 and sampled at a sampler 56 at an oversample rate twice And is input to a serial / parallel converter (S / P) 57. The output of the S / P is divided into a sampler O (On Timing) used for symbol demodulation and a sampler (E and L: Ear1y and Late Timing) used for timing error detection for synchronous tracking. That is, the detection of the timing error uses a baseband received signal shifted by [1/2] chip intervals from the symbol demodulation timing.

In the figure, the sample E among the input samples to the timing tremendometer is directly subjected to the correlation calculation in the multiplier 59A, and one sample L is delayed by one chip in the delay 58A and then multiplied by the multiplier 58B ). Further, Hb (z) is a low-pass filter 58C, 59C corresponding to digital integration. Then, the correlation results of the two systems are squared by the squarers 60A and 60B, respectively, so that influences such as carrier phase, symbol modulation, and the like are removed and a correlation power is obtained. Next, the error signal is input to the numerical control clock (NCC) The NCC 62 performs an averaging operation on the error signal to reduce the influence of noise components and the like, and then controls the sample clock of the received signal so that the error signal becomes zero.

Figs. 27A and 27B show correlation power characteristics and error characteristics, respectively. In Fig. 27A, the ordinate indicates the correlation power and the abscissa indicates the time difference. This characteristic is called the autocorrelation characteristic of the SS signal. As shown in Fig. 20, a typical example of the shape is shown. When the influence of noise is sufficiently small, the correlation power of the symbol sampled at the precise timing (time difference 0) in the same figure becomes the maximum, and the correlation power decreases as the time difference increases. 25, since the timing of the sample E is set so as to be faster than the timing of the sample O used for symbol demodulation [1/2], the sample E is delayed by one chip interval The correlation powers become values shown in Fig. 27A, respectively. In this case, if the timing of the sample O is ideal, the correlation characteristic is symmetrical, and therefore the correlation power by the sample E and the sample L becomes equal and the error signal becomes zero. When the timing of the sample O is slightly later than the correct timing, the correlation power by the sample E becomes larger than the correlation power by the sample L, and as a result, the error signal becomes a negative value. Fig. 27B shows the relationship between the timing shift and the error signal from the correct timing of the sample O. Fig. In the figure, the horizontal axis is time difference and the vertical axis is error signal. That is, when the error signal is negative, it indicates that the timing is late, and when it is positive, it means that the timing is fast.

25, squared operation is required after correlation calculation because a symbol modulation signal is used. However, when an error signal is generated from, for example, a pilot signal whose synchronization detection is ideal and symbol modulation is not performed, , 60B become unnecessary. In this case, the squarers 60A and 60B in Fig. 25 are omitted and a configuration called a synchronous DLL can be expected and an improvement in synchronous tracking performance can be expected. Even if an SS signal with symbol modulation is used, the configuration of the synchronous DLL can be realized by restoring the polarity of the symbol modulation to the original if the ideal synchronous detection can be performed. The DLL configuration by this operation is called an inverse modulated synchronous DLL.

Fig. 26 shows a conventional configuration called an inverse-modulated synchronous DLL, in which Sawahashi et al. "Inverse Modulated Coherent DLL in DS-CDMA" (Technical Report of the Institute of Electronics, Information and Communication Engineers, RCS94-50, pp. 18, February 1995). In FIG. 26, the portions surrounded by the dotted lines are the correlation calculating units 70, 71, and 72, the portion enclosed by the one-dotted chain line is the synchronizing key portion 68, and the portion surrounded by the two-dot chain line is the symbol demodulating portion 69. The voltage controlled spread code generator VCCG (78) included in the correlator is a spread code generator whose generation timing is controlled by a voltage control signal, which is an error signal. Fig. 25 shows a synchronous trace by controlling the sample timing of an input sample, while Fig. 26 shows synchronous trace by controlling the timing of occurrence of a spread code. In timing control, equivalent performance is obtained when the relative timing relationship between the received signal and the spreading code is controlled. Therefore, this is not the difference between an asynchronous DLL and an inverse-modulatable DLL. In the RAKE receiver described later, when the A / D converter is shared and the timing of each reception path signal is synchronously tracked and demodulated independently, a method of controlling the generation timing of the spread code is advantageous. However, in the case of using DMF described later, since the sign phase is fixed, a method of controlling the input sample timing such that the timing of the peak value is at the center is adopted.

26, the Spreaded Signa1 received signal is quasi-synchronously detected by a QPSK quasi-quadrature detector 65, sampled at an integer multiple of a chip interval by a sampler 67, and then subjected to a symbol demodulator 69, Respectively. The symbol demodulator 69 performs a correlation operation with the spread code of the timing synchronized with the received signal. However, since it is a quasi-synchronous detection signal, influence of the carrier wave phase difference? If the symbol is now d, this effect is expressed by dx exp (jφ). φ is estimated by a carrier phase estimator 79, and exp (- jφ ') is generated from the estimation result φ', and symbol demodulation is performed using the correlation result and the result of multiplication.

In the sync seeking unit 68, a correlation operation is performed between a spreading code at a timing earlier than the symbol timing and a spreading code at a later timing, and the difference between the calculation results of the two is calculated. The correlation calculation result includes the influence of the modulation symbol (d) and the carrier phase difference (?) In addition to the error signal component. If the error signal is ε, this influence is described as ε × d × cos (φ). The modulation symbol d and the carrier phase difference phi are removed using the phase difference phi 'estimated by the carrier phase estimator 79 and d' estimated by the symbol demodulator 81 and the error signal? '). The work of removing the influence of d by d 'is inverse modulation. is inputted to the loop filter 76 and averaged to reduce the influence of the noise, and is then input to the voltage controlled spread code generator (VCCG) 78 as? to be timing controlled. Since squaring loss is not required and the influence of noise components can be lowered, it is possible to improve the synchronous tracking performance because there is no need of a square sum circuit for eliminating the influence of the carrier phase difference and the modulation symbol by the inverse modulation have.

FIG. 28 shows an example of a timing trace section by a digital matched filter. This is based on Kataoka et al., "Digital Synchronization Method for Spectrum Diffusion Communication Using Soft-decision Matching Filter" (Technical Report of the Institute of Electronics, Information and Communication Engineers, RCS91-4, pp. 23-30, May 1991) . In the same figure, the outputs of the two low-pass filters (LPF) 87A and 87B, which are quasi-synchronous detection signals, are A / D-converted by the A / D converters 88A and 88B to double the chip speed, (89A, 89B).

The basic configuration of the digital correlator is shown in FIG. That is, the digital correlators 89A and 89B output correlation calculation results at twice the chip interval. When two correlator outputs are taken out at symbol timing and phase compensation is performed, the received symbols are demodulated. Further, the correlation outputs of the two correlator outputs are detected by the squaring circuits 90A and 90B and the adder 91, and the correlation power in which the influence of the carrier phase and the modulation symbol is removed. The correlation power is divided into two, and the difference between the correlation power delayed by the delay circuit 92 of one chip interval and the one not passing through the delay circuit 92 is obtained by the subtracter 93 and the error signal is outputted. When the digital matched filter of Fig. 28 is used, the subtracter output of the timing (symbol timing) at which a meaningful error signal is included is extracted by the latch circuit 94.

The error signal is averaged by a loop filter 95 to reduce the influence of noise, and then input to a voltage controlled oscillator (VCO) 96 to control the reception timing of the quasi-synchronized detection signal. The correlation between the symbol timing of the correlation value and the timing of giving an error signal is as shown in Fig. 25 and Figs. 27A and 27B. That is, the timing at which the error signal is latched is the next sample (after one-half chip interval) of the symbol timing.

In the example of FIG. 28, the voltage controlled oscillator (VCO) 96 is constituted by an analog circuit to perform A / D conversion of the VCO output. However, from the viewpoint of miniaturization of the device scale and mass production, Circuit. In this case, a configuration in which clock control is performed digitally as shown in Fig. 25 is conceivable.

29 is a block diagram of a conventional digital control clock generator (hereinafter referred to as " digital control clock generator ") reported by Takakusaki et al. In " Development of a Digital Control Clock Oscillator for DLL " FIG. In the case of a voltage controlled oscillator (VCO), the output frequency is directly changed by the analog control voltage. On the other hand, in the configuration shown in the figure, the fixed clock 97, which is faster than the chip speed, is prepared and the phase of the output clock is directly changed by the digital control signal 98. That is, a programmable delay element 99 is provided to change the phase of the clock by changing the delay time according to the control value of the digital control signal 98. [ An output signal whose delay time is controlled digitally performs clock control via a frequency divider circuit. In this case, since the update unit of the timing is discrete, it is necessary to prepare a clock that is faster than the chip speed as the basic clock in order to realize the synchronous tracking performance with high accuracy. For example, if the fixed clock 97 is n times the chip speed, the control unit of the chip timing is 1 / n chip interval.

Here, since the chip rate is considerably faster than the symbol rate and is usually designed at a spreading rate of several tens times to several hundreds times, high-speed operation is required. In order to realize synchronous tracking performance with high accuracy, the control unit in Fig. 28 is required to operate at a speed n times the chip speed. Since the power consumption of the digital circuit depends heavily on the high-speed operation speed, it is a problem of the digital synchronization trace section to reduce the operation speed without deteriorating the synchronous trace characteristics.

Fig. 30 shows another conventional configuration of the clock generator by digital control. This concept is reported in Cessna, et al., "Phase Noise and Transient Times for a Binary Quantized Digital Phase-Locked Loop in White Gaussian Noise" (IEEE Transaction on Communication, COM-20, No. 2, pp. 94, 1972). In the figure, timings are controlled by the timing control signal in the pulse insertion / deletion circuit 101 in the frequent clock 100 which is an integral multiple of the chip speed. To increase the timing, a pulse is inserted into the clock signal. Since the digital circuit operates by, for example, a pulse rise, timing is relatively advanced when a pulse is inserted. Conversely, when delaying the timing, the clock pulse of the clock signal is erased. If the clock lOO is n times the chip rate, the timing controlled by insertion / deletion of one pulse is [1 / n] chip interval.

In Fig. 30, the circuit scale is reduced as compared with Fig. 29, but the pulse insertion operation must be realized at a speed higher than the clock frequency frequently. Therefore, from the viewpoint of low power consumption, it is a problem of the digital synchronous tracking unit to reduce the operating speed without deteriorating the synchronous tracking characteristic.

However, in mobile communication, it is affected by multipath fading. As a result, the received signal is received as a plurality of received path signals at different timings at which the carrier phase and amplitude change independently. Since the SS signal utilizes the time correlation characteristic by the spreading code, it is possible to discriminate and receive the signal when the arrival time difference of the received path signal is one chip or more. In addition, it is possible to improve the reception characteristic by combining the reception path signals which are separately identified. This type of reception is called RAKE reception.

31 is a configuration of a conventional RAKE receiver disclosed by U.S. Patent No. 5,490,165. The RAKE receiver in FIG. 31 includes a searcher element 105 for searching for a transmission signal at a neighboring base station and for detecting a reception state (timing, signal power) of a reception multipath signal that varies with time, A symbol combining unit (SYMBOL COMBINER) 107 for combining the symbol demodulation results of the respective demodulating units 106, a search unit 105 for searching the search base 105, And a controller 108 for controlling allocation of a reception path signal to be demodulated by the demodulation unit 106 based on the result of the synchronization and demodulation symbol power of the demodulation unit 106.

In Fig. 31, the search performed by the searcher unit 105 is a synchronous acquisition operation, and the device configuration is realized in the configuration of Fig. However, it differs slightly in that the received path signal is searched while synchronous estimation and symbol demodulation are performed. That is, before the demodulating section 106 is unable to demodulate due to the level fluctuation of the fading, all of the synchronous tracking and symbol demodulating signals are retrieved and reassigned to the demodulating section 106 and a complete synchronous deviation I need to prevent it from happening.

Therefore, as the operation of the search base unit 105, it is necessary to perform signal search with high accuracy in a short time. Particularly, in order to enable the demodulator 106 to operate in a short time after the reception path signal is allocated to the demodulator 106, it is necessary to shorten the acquisition time of the synchronization, and a high time accuracy is required at the time of acquisition of the synchronization . In such a case, in the case of the sliding correlator, it is also conceivable to increase the number of correlations to be prepared in parallel and simultaneously measure the correlation power at different timings, but there is a problem that the hardware size becomes large as the number of parallelism increases.

Fig. 32 is a detailed configuration of the demodulating unit 106 of Fig. 31, and is disclosed by the same U.S. Patent 5,490,165. In the same figure, a portion surrounded by a dotted line is a correlation calculation unit 110. [ In the drawings, filters (Fi1ter) 110B and 110C extract pilot signals (only for spreading modulation) included in the in-phase and quadrature-axis received signals and average them. In the conventional example, a RAKE receiver configuration for a signal in which an information signal is code-multiplexed to a pilot signal on a transmission side, and an unmodulated pilot signal and an information signal are code-multiplexed by an orthogonal code (Walsh Function). That is, since the information signal is multiplexed with the orthogonal code with the pilot signal, the pilot signal is supplied to the output of the QPSK despreader 110A through the output of the orthogonal code generator 111 and the output of the multiplier 110D And 110E and accumulators 110F and 110G, and can perform channel estimation by separating from the information signal. Since the RAKE reception is realized by maximum-ratio combining, the phase difference of the carrier wave and the received signal amplitude are also estimated in the Data Scale Phase Rotation 112, and the phase compensation and the weighting by the estimated amplitude And outputs a weighted synchronous detection symbol. Then, the signal is input to the symbol storage register (FIFO) 113, and timing is adjusted so that it is output to the symbol combining unit 107 (Fig. 31) at the same timing as other receiving path signals.

Quantitatively, it is assumed that the reception amplitudes are in the order of ρ ₀ , ρ ₁ , ρ ₂ , carrier phase, φ ₀ , φ ₁ , φ _2, Assuming that the delay time is 0, t ₁ , and t ₂ , the baseband reception signal MRx is

_{MRX = ρ 0 · d (t} ) · exp (jφ 0) + ρ 1 · d (t + t l) · exp (jφ 1) + ρ 2 · d (t + t 2) · exp (jφ 2)

. The output of each demodulator 106 (FIG. 31) subjected to phase compensation and weighting is denoted by ρ ₀ ² d (t), ρ ₁ ² d (t + t ₁ ), ρ ₂ ² d It is a + t _2). When the storing time of the symbol storage register 113 is set to τ ₀ , τ ₀ -t ₁ and τ ₀ -t ₂ respectively (τ ₀ ≥t ₂ ), the output of each demodulator 106 is ρ ₀ ² (T + τ ₀ ), ρ ₁ ² d (t + τ ₀ ), and ρ ₂ ² d (t + τ ₀ ), they are synthesized by the symbol synthesizer 107 The symbols weighted by power (rho ² ) are synthesized.

The synchronization trace portion in FIG. 32 is also configured as a DLL. That is, the spreading code given by the pilot PN code generator 114 is adjusted by a timing adjustment means (Time Skew) 115 so that an error signal is obtained. Thereafter, the QPSK despreader 116A and the integrator And a correlator 116 composed of a correlation block 116B to generate an error signal from the selected result. In the timing control section (Time Tracking) 117, the error signal is averaged to reduce the influence of noise, As shown in FIG.

29 to 30, it is necessary to operate the timing control section 117 at a speed higher than the chip speed at a high speed, to reduce the operation speed without deteriorating the precision and to reduce the power consumption . In addition, in the RAKE receiver of FIG. 31, since there are a plurality of demodulation units 106 including the timing control unit 117 which requires high-speed operation, the reduction of power consumption becomes a particularly large problem in the RAKE receiver. In Fig. 32, the timing adjusting means 113 for constituting a symbol combining section is constituted by a FIFO, and the higher the speed, the larger the size and power consumption of the FIFO.

FIG. 33 shows the configuration of a RAKE receiver under a multipath fading environment when a digital matched filter is used. This is a composition reported by G. L. TURIN as PR0CEEDING OF THE IEEE, Vo1.68, March, 1980, in Introduction to Spread-Spectrum Antimultipath Techniques and Their Application to Urban Digital Radio. The synchronously detected correlator output signal is input to a delay circuit (Delay Line) 118, and the timing is adjusted so that the combined timings of the multipath reception signals coincide. Then, a weighting corresponding to the reception amplitudes of the multipath reception signals is added, and then added by a summing bus 119. The weight corresponding to the timing at which the reception multipath signal is not detected is set to 0, thereby preventing the mixing of unnecessary noise. In the example of FIG. 33, the input signal to the RAKE receiving section is a synchronous detection signal, but it is also possible to input the correlation calculation output in which the carrier phase difference remains, and to perform phase compensation at the weighted portion at the same time. The reception amplitude p and the carrier phase phi for weighting and phase compensation can be estimated by the method shown in Fig. 26, Fig. 32, or the like.

In the case where the digital matched filter is used as described above, since the correlation value or the correlation power is given every input sample interval (i.e., chip rate or more) of the digital matched filter, the synchronization acquisition and synchronous estimation are relatively easy. However, Only the correlation value can be detected. To increase the timing accuracy, it is considered to simply extend the configuration of FIG. 23 to the configuration of FIG. 34 in which the same letter and similar portion of the configuration are replaced with the same letter. However, the increase in the circuit scale and the power consumption due to the high precision also becomes very large, which is difficult to realize. Therefore, the input sample rate is limited by itself, and it is difficult to obtain a high timing accuracy. As a result, the problem that the signal power is lowered due to the timing error remains.

The configuration shown in Fig. 35 is reported for the above problem. This configuration is shown in Japanese Laid-Open Patent Publication No. 95-95125, and the n digital matched filters 121 are operated in parallel at low speed to reduce power consumption. This is similar to the configuration in which the sliding correlator is operated in parallel, and the operating speed can be reduced by only a few in parallel. In the same figure, a plurality of digital matched filters 121 operating with clocks 122 having different phases from each other are prepared in the same manner as chip clocks, and the correlation values or the correlated powers are continuously output through the multiplexer 123 And the operation speed of the digital matched filter 121 is a structure that obtains a high timing accuracy in accordance with the chip speed.

However, although the increase of the hardware scale due to the parallelization of the digital matched filter 121 is considerably large and the maximum operation speed is suppressed to be low, the amount of power consumption due to the parallelization also increases, The challenge remains.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems and provides a spread spectrum signal reception method and a spread spectrum signal reception apparatus capable of downsizing and lowering power consumption without damaging the symbol (or data) demodulation characteristic, the synchronization acquisition characteristic and the synchronization tracking characteristic The purpose is to do.

BRIEF DESCRIPTION OF THE DRAWINGS FIGURES 1A-1D are signal waveform diagrams used to illustrate the principles of the present invention.

2 is a block diagram illustrating a configuration of a sliding correlator of a symbol demodulator according to the present invention;

Fig. 3 is a block diagram showing the configuration of a high-definition unit according to the present invention; Fig.

4 is a block diagram showing a configuration of a digital matched filter of a symbol demodulator according to the present invention;

5 is a block diagram showing a configuration of a sliding correlator of a synchronous acquisition unit according to the present invention;

6 is a block diagram showing a configuration of a digital matched filter of a synchronous acquisition unit according to the present invention;

7 is a block diagram showing a configuration of a continuous high-precision image forming unit according to the present invention;

FIG. 8 is a block diagram showing a configuration of a symbol correlator for a RAKE reception and a sliding correlator of a synchronous estimator according to the present invention; FIG.

FIG. 9 is a block diagram showing another configuration of a symbol correlator for RAKE reception according to the present invention and a sliding correlator of a synchronous tracker. FIG.

FIG. 10 is a block diagram showing a configuration of a symbol correlator for RAKE receiving synchronous detection by the pilot signal according to the present invention and a sliding correlator of a synchronous tracking unit. FIG.

11 is a diagram for explaining the operation of the high-precision error signal generating means and the timing control means according to the present invention.

FIG. 12 is a block diagram showing a configuration of a symbol correlator for RAKE reception according to the present invention and a sliding correlator of an inverse-modulated synchronous DLL; FIG.

13 is a block diagram showing another configuration of a symbol correlator for RAKE reception according to the present invention and a sliding correlator of an inverse modulated synchronous DLL;

FIG. 14 is a block diagram showing a configuration of a digital matched filter of a RAKE receiver according to the present invention; FIG.

15 is a block diagram showing a conventional configuration of a transmission unit of a spread spectrum signal;

16 is a block diagram showing a conventional configuration of a digital receiving section of a spread spectrum signal;

17 is a block diagram showing a conventional configuration of a symbol demodulator by a sliding correlator;

18 is a block diagram showing a conventional configuration of a symbol demodulation circuit by a digital matched filter;

19 is a signal waveform diagram provided for explaining a time correlation characteristic of a spread spectrum code;

20 is a signal waveform diagram for explaining time correlation characteristics of a spread spectrum code;

21 is a block diagram showing a conventional configuration of a synchronous acquisition unit by a sliding correlator;

22 is a block diagram showing a conventional configuration of a synchronous acquisition unit by a digital matched filter;

23 is a block diagram showing a conventional configuration of a digital matched filter having a 2-times oversampling precision;

24A and 24B are signal waveforms for explaining a procedure for obtaining correlation values at a central point from normal correlation characteristics and adjacent correlation values;

25 is a block diagram showing a conventional configuration of a symbol demodulator and a synchronization estimator by a sliding correlator;

26 is a block diagram showing a conventional configuration of a symbol demodulator and an inverse modulated synchronous DLL by a sliding correlator;

27A and 27B are diagrams of signal waveforms showing the relationship between the sample timing and the correlation power used in the synchronous tracking unit and the relationship between the sample error and the error signal;

28 is a block diagram showing a conventional configuration of a symbol demodulation unit and a synchronization trace unit by a digital matched filter;

Fig. 29 is a block diagram showing a conventional configuration of a timing control circuit in a synchronism tracking section; Fig.

30 is a block diagram showing another conventional configuration of the timing control circuit in the synchronism tracking section;

31 is a block diagram showing a conventional configuration of a RAKE receiver;

32 is a block diagram showing a conventional configuration of a symbol demodulator for a RAKE reception by a sliding correlator and a synchronous estimator;

33 is a block diagram showing a conventional configuration of a RAKE combining section by a matched filter;

34 is a block diagram showing a conventional configuration of timing accuracy enhancement by a matched filter;

Fig. 35 is a block diagram showing a conventional configuration of high-accuracy timing matching of a matched filter by a parallel arrangement of digital matched filters. Fig.

Description of the Related Art [0002]

1: Data spreading section 2: Data coder

3: spreading unit 4, 26, 44, 66: spreading code generator

5: modulation section 6, 14: local oscillator

7, 13: Multiplier 8, 12: Bandpass filter

9: amplification unit 10, 11, 42: antenna

15, 55: Low pass filter (LPF) 16: Automatic gain controller

17: analog-to-digital converter 18: SS receiver

19: demodulation unit 20:

21: Synchronization tracking unit 22: Data decoding unit

25, 35, 41, 35A, 58, 59, 70, 71, 72:

27, 37, 37A: multiplier 28: integrator

29: chip rate clock 30, 40, 40A, 56: sample

31: sample rate clock 36, 36A: shift register

38: spreading code 39, 39A: adder

41A: QPSK despreader 41B, 4lC: digital integrator

43: receiver 45: square multiplier

46: averaging unit 47: comparator

48: Controller 50A, 50B: Squier

51, 52A: adder 52: cyclic adder

52B: frame memory 52C: multiplier

53: maximum hold unit 57: serial-to-parallel converter

58A: Delay device 58B: Multiplier

58C, 59C: Low pass filter 60A, 60B:

61: subtracter 62: numerical control clock

65: QPSK net synchronous detector 68:

69: Symbol demodulator 76: Loop filter

77: Delay device 78: Voltage controlled spreading code generator

79: Carrier phase estimator 81: Symbol demodulator

86A and 86B: multipliers 87A and 87B: low-pass filter

89A and 89B: digital correlators 90A and 90B:

91: adder 92: delay circuit

93: subtracter 94: latch circuit

95: Loop filter 96: Voltage controlled oscillator

97: Fixed clock 98: Digital control signal

99: programmable delay element 100: frequent clock

101: pulse insertion / deletion circuit 102: frequency divider

105: Search base 106: Demodulator

107: symbol synthesizer 108:

110: Correlation unit 110A: QPSK despreader

110B and 110C: filters 110D and 110E:

110F, 110G: accumulator 111: orthogonal code generator

11: weighted phase compensator 113: symbol store register

116: Correlator 116A: QPSK despreader

116B: integrator 117: timing controller

118: delay circuit 119:

120: analog-to-digital converter 121: digital-matched filter

122: clock 123: multiplexer

124: Absolute value calculation circuit 125: Maximum absolute value calculation circuit

126: Counter 201, 202: Sliding correlator

203: clock 204: spreading code generator

205, and 206, a delay circuit 207, a timing high-

208: selector 209, 210: amplifier

211: adder 212, 212A: high precision imaging means

213: Decoder 214, 215, 216:

220: analog to digital converter 221: serial to parallel converter

222A and 222B: digital matched filter (DMF)

223A and 223B: samples 225A and 225B: delay circuits

226: Comparators 230A and 230B: Serial-to-parallel converter

23lA, 231B, 231C and 231D: digital matched filter (DMF)

232: Continuous high-definition means 234: Receive path detection

In order to solve such a problem, a spectrum spread signal reception method according to the present invention is a spectrum spread signal reception method for demodulating a reception signal by performing a correlation operation with a spread code on a baseband component of a spread spectrum reception signal, A first correlation operation step of performing a correlation operation between a spreading code and a baseband component when performing a correlation operation between a baseband component and a spreading code of a spread spectrum signal; A second correlation calculation step of performing a correlation calculation at a timing different by ½ the spreading code interval from the timing relationship of the first and second stages, And an estimation step of estimating an operation result.

A method of receiving a spread spectrum signal according to the following invention is a method for receiving a spread spectrum signal by performing a correlation operation with a spread code on a spread spectrum received signal baseband component and demodulating the received signal, A second correlation operation step of performing a correlation operation between a spreading code and a baseband component in which a spreading code is offset by 1/2 of a code interval and performing a correlation operation with the spreading code and a baseband component; An estimation step of estimating a correlation calculation result of a central point of two timings by adding a second correlation calculation result to each of the first correlation calculation result and the first correlation weight calculation result, And an optimum timing line for selecting a correlation calculation result or an estimation result of an optimum timing from the calculation results of the estimation step, the first and second weighting steps, .

A spread spectrum signal receiving apparatus according to the present invention for receiving a spread spectrum signal for performing a correlation operation with a spread code on a spread spectrum received signal baseband component to demodulate the received signal, A plurality of correlation calculation means for performing correlation calculation between a baseband component and a spreading code and a spreading code delayed by a plurality of steps; A plurality of averaging means for obtaining an average correlation power by averaging each of the correlation powers, a plurality of averaging means for obtaining an average correlation power, a timing for adjusting a timing at which a plurality of average powers are obtained, And a plurality of average correlated powers whose timings are adjusted, Timing control means for performing timing control based on the high-precision average correlation power, and timing control means for setting a spread code clock in accordance with the control result of the timing control means Timing correcting means for selecting and outputting a maximum correlation calculation result among correlation calculation results of a plurality of correlation calculation results and a timing center point estimated from the calculation results in accordance with a control result of the timing control means Respectively.

Embodiments of the Invention

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Example 1)

Figs. 1A to 1D are diagrams for explaining the principle of obtaining high timing accuracy by the present invention. Fig. The curve in the figure shows the correlation value or correlation power characteristic of the SS signal. The following explanations are applied to correlation values, even if they are correlation values, but they are correlation values. The case where the sample is a double oversample will be described. In addition, a double oversample means that the sample is sampled at twice the chip rate. In the figure, the arrows S _-1 , S ₀ , S ₁ , and S ₂ indicate the results of correlation calculations performed on the sample values obtained at the respective sample timings. A _-2 , A _-1 , A ₀ , and A ₁ correspond to the correlation values described with the digital matched filter in Figs. 23 and 34, and correspond to correlation values obtained from the sample timing obtained by adding correlation values obtained from adjacent sample timings Is the correlation value corresponding to the central point.

FIG. 1A shows that the maximum correlation value is obtained at the sample timing where S ₀ is most appropriate. FIG. 1B shows that the most suitable sample timing exists between S ₀ and S ₁ , so that no correlation value can be obtained except for a correlation value lower than the maximum value. In Figure 1c is not, A _-1, A ₀ is also provided for which the correlation value is obtained outside than a lower level of the maximum value, because the presence, configuration best correlation value A _-1 and A ₀ intermediate is obtained as shown in Fig. 23 . FIG. 1D shows that A ₀ is obtained as the most appropriate correlation value.

In comparison between Fig. 1A, Fig. 1C and Fig. 1B and Fig. 1D, the state (a) of the optimum timing with the normal correlation value is the state (c) of the worst timing of the correlation value obtained by adding adjacent correlation values, , It is proved that the state (d) of the optimum timing of the correlation value obtained by adding the adjacent correlation values is the state of the worst timing (b) of the normal correlation value. This suggests that they are in a relationship that can interpolate with each other. That is, based on the correlation value obtained by double oversampling, the correlation value of the center point timing between the sample timings is estimated from the addition value between the adjacent samples as necessary, thereby corresponding to the time accuracy of the 4-times oversample Is obtained.

According to the present invention, demodulation precision, synchronous tracking accuracy, and synchronization acquisition accuracy with high accuracy in time are realized with a small amount of computation using the above-described principle. However, although A ₀ of FIG. 1B and A _-1 of FIG. 1C are correlation values corresponding to the same timing, since the values themselves are different from each other, coefficients for correcting these values are required. The correction factor depends on the shape of the waveform shaping filter. Further, in the case of handling the correlation value and the case of handling the correlation power, the correction coefficient also needs to be set separately for the coefficient for amplitude and the coefficient for power. The correction coefficient for the correlation value (amplitude) may be determined from an experiment or a computer simulation or the like so that the average error rate is minimized or the timing error is minimized. However, for example, as shown below, It may be decided in correspondence.

That is, if the chip impulse response (the synthetic impulse response of the transmission and reception waveform shaping filter) is h (t), which is the average correlation value at the time difference t, the sample center point g (t) Value.

(t) = h (t-Tc / 4) + h (t + Tc / 4)

This is because the correlation value for the sample of the center point is obtained from the correlation value by the sample before Tc / 4 and after Tc / 4 with respect to the center point. As is clear from Figs. 1A to 1D, if the timing error relating to S0 is _equal to or less than Tc / 8, the correlation value itself is used, and if Tc / 8 to Tc / 4, the addition of the correlation value is used in correlation with the timing error It is found to be valid from the relationship of teeth. That is, the correction coefficient G _A for the correlation value,

_{G A × h (Tc / 8} ) = g (Tc / 8)

. The correction coefficient (G _P ) for the correlation power is also set as a carriage branch,

^{_{G P × h 2 (Tc /}} 8) = g 2 (Tc / 8)

. If the chip impulse response is symmetrical in the left and right directions and has a shape that gradually decreases in accordance with the timing error, by using the above G _A and G _P , the effect equivalent to the timing accuracy at the time of 4 times oversampling can be realized.

(Example 2)

Fig. 2 is an embodiment of a symbol demodulator according to the sliding correlator of the present invention, which corresponds to Fig. The portions 201 and 202 surrounded by the dotted lines in the figure are sliding correlators, and the portion surrounded by the one-dotted chain line is surrounded by the timing high precision means 207 and the two-dot chain line is the high precision rendering means 212. A clock (Chip-rate Clock) 203 for driving a spread generator (PN Generator) 204 receives a double-clocked free-running clock and outputs a clock signal according to a timing control signal (Control) And controls the timing of the spreading code generator 204 in units of 1/2 chip. (1/2) chip interval ([1/2]) is performed by the sliding correlator 201 and the delay circuit 205 is subjected to the correlation calculation with the direct baseband received signal, 2] Tc), the sliding correlator 202 performs a correlation operation with the baseband received signal.

The integration start / end time of the correlation calculation of the sliding correlator 202 is set to be [1/2] Tc (t) with respect to the integration start / end time of the correlation calculation of the sliding correlator 201, Delayed. In order to absorb the delay, the above correlation value is delayed by [1/2] Tc to the delay circuit 206 and then input to the high-precision conversion means 230. Further, the sliding correlators 201 and 202 operate on a chip-by-chip basis, and their timings are shifted by [1/2] chips. Therefore, it is also possible to adopt a configuration in which the baseband received signal is subjected to serial / parallel conversion (parallel number is 2), one output to the sliding correlator 201 and the other output to the sliding correlator 202. In this case, the delay circuits 205 and 206 are omitted. This modification method is applied to all configurations using the sliding correlator described in the following embodiments.

As the high-precision image-forming means 212, the timing precision is made high with a correlation value twice as high as four times as high as the correlation value. In the high-precision method, the correlation values obtained are amplified by the amplifiers 209 and 210 in accordance with the correction coefficient C _A relating to the amplitudes, respectively, in the timing high-precision means 207, And the adder 211 adds the both input correlation values. In the selector 208, one of the three correlation values is selected and output in accordance with the selection signal. The selection signal is a signal corresponding to the optimum timing determined by the synchronization tracking unit, which will be described later. According to such a configuration, a correlation value of 4 times oversampling precision can be obtained even though the maximum speed is twice the chip clock and the control unit is [1/2] Tc. Therefore, the timing accuracy can be reduced and the power consumption can be reduced . The configuration of Fig. 2 has an increase in the number of correlations as compared with the configuration of Fig. 17, but since these correlators are also shared by the synchronous estimator, if the synchronous estimator is also taken into consideration, . Fig. 3 is another embodiment of the high-definition means 212 of Fig. A portion (A) surrounded by a one-dot chain line in the figure corresponds to the high-precision imaging means 212. In the embodiment of FIG. 2, the correlation value of the central timing is calculated from the obtained two correlation values, and the correlation value is selected by the selector 208 at the end. However, since only one correlation value is actually required, There is a tendency to be lengthened. (Functon Select) in which the selection signal is decoded by the decoder 213 and the amplification is performed and the addition log is selected because the amplification of a single correlation value or addition of both correlation values is performed arithmetically. In the case of amplification, Into a sample select signal for selecting which of the correlator 201 and the correlator 202 of the correlator 202 is to be amplified. The selector 1 (214) and the selector 3 (215) perform input / output selection of the arithmetic function and select the correlation value in the case of amplification by the selector 2 (216).

The function of the decoder 213 and the circuit configurations of the selectors 214, 215 and 216 are simple at the same time and the selector 1 214 and the selector 3 215 are also interlocked with each other. Power consumption can be reduced by omitting redundant arithmetic operations unnecessarily. Further, in the high-precision converters 212 and 212A, the target of high precision is not at the correlation value (amplitude), and at the time of correlation power, the correction coefficient GA is changed to G _p .

(Example 3)

Fig. 4 is an embodiment of a symbol demodulation unit using a digital matched filter according to the present invention, and corresponds to Fig. 35, for example. In FIG. 35, when the number of digital matched filters (DMF) is set to 4, for example, the received signals input with four times oversampling are input into four DMFs with different timing phases, 4 differs in that the two DMFs 222A and 222B shifted at a timing of [1/2] Tc are operated at chip speeds for signals input with double oversampling, respectively.

That is, the A / D converter 220 converts the baseband received signal into a digital signal at a chip rate two times higher than that of the two samples And are input to the DMFs 222A and 222B, respectively, and one correlation value is output for each chip. Only the correlation values of the sample timings corresponding to the vicinity of the double data timing are extracted from the samples 223A and 223B. The outputs of the samples 223A and 223B are input to the high-precision conversion means 212 or 212A, and the correlation value, which is highly accurate to the timing accuracy of the 4-times oversample, is selectively output according to the selection signal. Here, too, the correction coefficient is G _A since the amplitude is also made to be high-precision. As a result, a correlation value of 4 times oversampling accuracy can be obtained with a maximum speed of 2 times oversample and a DMF of 2 systems of chip speed operation, and the circuit scale and power consumption can be greatly reduced as compared with FIG. 35 It becomes. 23, the circuit scale is the same, but the DMF operation speed is halved (chip speed), and the timing accuracy is multiplied by four times compared with that in Fig. 23, and the reception correlation value with high precision timing is obtained There is an effect that can be.

(Example 4)

5 illustrates an embodiment of a synchronous acquisition unit or a searcher unit using the sliding correlator according to the present invention, corresponding to the search unit of FIG. 21 or FIG. 31, and the same reference numerals are assigned to corresponding parts . Fig. 21 shows a case in which the sliding correlator is one system, but in the present embodiment, the case of two systems is shown. Therefore, in order to satisfy the circuit scale and the performance condition, the effect obtained by the present invention will be described in comparison with the case where the correlator has two systems in Fig.

In FIG. 5, despreader 41A, digital integrators 41B and 41C, squarer 45 and non-coherent accumulators 46 are shown in FIG. 21 It operates in the same way. 21, the timing difference between the systems is preferably [1/2] Tc in order to shorten the acquisition time and improve the acquisition performance by using the two systems of correlators, and with respect to Fig. 5 Such a case is shown.

The difference from the operation in the case of two systems of correlators in Fig. 21 is that in Fig. 5, an average correlation power is obtained with a 4-times oversampling accuracy according to the timing high-precision means 207 and compared with a threshold level have. That is, a delay circuit 225 of [1/2] Tc time is provided for a system having a high timing with respect to the averaged correlation power, and the timing at which the average correlation power is obtained in a system with a slow timing is adjusted. Next, the timing correction unit 207 outputs the correlation value at the 4-times oversampling precision, and performs the acquisition check by comparing the obtained average correlation value output with the threshold level by the comparator 226. [ Although the timing high-definition unit 207 has the same configuration as that shown in Fig. 2, in Fig. 5, since the correlation power is handled, the correction coefficient is G _p corresponding to the power.

With this configuration, even if the correlator configuration corresponding to the timing accuracy of the double oversampling can be subjected to the synchronization acquisition test with a high timing accuracy of 4 times oversample, the influence of the S / N degradation due to the timing error is small, Can be improved. Since the timing high-precision unit 207 is processed with respect to the average correlation power obtained by the double oversampling, the calculation amount is significantly smaller than the correlation power obtained by averaging the correlation power with accuracy of four times oversample from the beginning. Further, since the timing of acquiring the synchronization can be made with high accuracy, the initial lead-in time of the synchronous tracking unit when moving to the synchronous tracking operation can be shortened and the synchronous tracking performance can also be improved. Particularly, in a multipath fading environment in which a received signal level is frequently changed, as signal searching means for RAKE reception, improvement in signal search performance and shortening of the pull-in time maintain synchronous retention (lower the probability of the synchronous shift) It is very effective at.

In the embodiment shown in Fig. 5, the two correlators of Fig. 21 have been described as two systems. Conversely, the same effect can be expected even when the correlator of Fig. 5 is compared with Fig. 21 as one system. In the case where the correlator is the first system, the timing assumed at the time of performing the acquisition acquisition check is changed to [1/2] Tc, but in FIG. 5, the same interval is changed, This is because it is possible to estimate the average correlation power of the central timing from the average correlation power according to the timing high-definition means.

(Example 5)

Fig. 6 shows an embodiment of a synchronous acquisition unit or a search base unit using the DMF according to the present invention, corresponding to Fig. 22, and corresponding parts are denoted by the same reference numerals. In FIG. 22, a DMF having correlation with two consecutive spreading codes of the same sign and outputting a correlation value with a 2-fold oversample is applied to a received signal inputted with a double oversample shown in FIG. 23, , And the acquisition of synchronization is detected as a result of addition of correlation electric powers that are effectively adjacent to each other. On the other hand, in the present invention, in order to estimate the correlation power directly obtained and the correlation power of the center point between adjacent samples using this correlation power, signals sampled with 2 times oversample are shifted in accordance with the serial parallel- A two-system DMF configuration that processes chip-shifted, chip-rate received samples.

6, the quasi-coincidence-detected in-phase-axis received signal and the orthogonal-axis received signal are input to the serial-to-parallel converters 230A and 230B at a 2-times oversampling rate and are shifted by [1/2] Tc Two minutes. The even-numbered samples are subjected to the correlation calculation at the chip rate in the correlators 231A and 231B, and output the correlated power for each chip through the squarers 50A and 50B and the adder 51. [ Likewise, odd-numbered samples output correlated power for each chip via correlators 231C and 231D. Each correlation power is subjected to averaging operation 52 by averaging by cyclic addition, and the average correlation power for each chip interval is stored in the frame memory 52B. The average correlation power is stored by the continuous high- The received signal is detected by the receiving path detecting unit 234 and the received signal is detected by the receiving unit 234 to be sent to the control unit CPU Results are reported. Further, in order to deal with the correlation power, the continuous high-definition unit 232 has the correction coefficient G _p .

Fig. 7 shows the detailed configuration of the continuous high-precision image-forming means 232 in Fig. The average correlation power is input from the averaging unit 52 for each chip interval. Accordingly, the output of the two averaging units 52 can be alternately input by alternately switching the switch 232A at a double chip rate, and as the switch output, the average correlation power is obtained with a timing accuracy of 2 times oversample . If this is the case, there is no substantial difference from the performance obtained in Fig. 22, but the average correlation power is continuously output with the accuracy of 4 times oversample according to the configuration after the delay circuit 232B.

That is, since the amplifier 232D and the adder 232C are connected through the delay circuits 232B and 232C as shown in Fig. 7, the amplifier 232D always amplifies the output (average correlation power) of the delay circuit 232C , And outputs the amplification result to the parallel-to-serial converter 232F. At the same time, the adder 232F always adds the output (average correlation power) of the delay circuit 232B and the output (average correlation power) of the delay circuit 232C and outputs the addition result to the serial-to-parallel converter 232F . The serial-to-parallel converter 232F alternately outputs the input amplification result and the addition result in a quadruple of chip clocks so that the amplified average correlation power and the average correlation power of the estimated center point in accordance with addition are continuously output The average correlation power is output with the timing accuracy of the 4-times oversampling.

Here, since the high-precision processing is performed on the average correlation power, the calculation amount is significantly smaller than the configuration in which the average correlation power is obtained at four times the precision from the beginning. In addition, the processing after the precision of 4 times is also good because the processing is performed once for the rate of output of the averaging section, that is, for the number of iteration, so that it becomes small along with the computation amount and the speed. Therefore, the increase in the throughput becomes smaller in the overall configuration of Fig.

As described above, according to the configuration of Fig. 6, the effect of being able to acquire the synchronization with the timing accuracy of 4 times oversampling is obtained, with the calculation amount and the hardware scale almost equal to the 2 times oversampling precision. In this case, similar to the embodiment of the synchronous acquisition unit by the sliding correlator of Fig. 5, the synchronous acquisition performance is improved by the improvement of the timing accuracy, and the synchronous misalignment due to the shortening of the pull- There is also an effect of reducing the probability.

(Example 6)

8 and 9 show an embodiment of a sync detector and a symbol demodulator using a sliding correlator according to the present invention. In both drawings, a description will be given of a case where symbol demodulation and synchronous tracking are performed on BPSK information symbols spread modulated according to BPSK. In the symbol demodulation section related to Fig. 2, two systems of a correlator that are originally one system are required in order to achieve high precision. However, it was explained that the unnecessary system without necessity can be shared with the synchronous log unit. 8 and 9, description will be made of a description that the synchronization trace section can be shared with each other, and synchronous trace characteristics having a 4-times oversampling accuracy can be realized from the correlation value of the 2-times oversampling precision even at the synchronization trace section.

8, the quasi-synchronized baseband received signal is waveform-shaped according to a waveform shaping filter (LPF) 235 and sampled in the sample 236 by a frequent clock at twice the chip clock fc. The sampled received signal is divided into four and input to the complex correlators 237A to 237D. The complex correlators 237A to 237D refer to a correlator that multiplies the same spreading codes for the in-phase and quadrature-axis received signals and integrates them over symbol intervals, in the case of Fig. The spreading codes generated by the spreading code generator 238 are also input to the complex correlators 237A to 237D simultaneously. However, each spread code is delayed in delay circuits 239A to 239C only for different delay times, and input in the order of complex correlators 237A to 237D in order of decreasing delay time. The delay time has a delay time of [1/2] Tc. The outputs of the four complex correlators 237A to 237D are multiplied by square summing means 240A to 240D, respectively, to be correlated powers, and are averaged by the averaging means 241A to 241D to reduce the influence of noise.

Since the integration timings of the complex correlators 237A to 237D depend on the input spreading codes, the delay circuits 242A to 242C for absorbing the time differences are used to average the four systems to the timing high- After the input timing of the correlation power is established, the timing high-precision means 243 outputs the correlation value corresponding to the time precision of the 4-times oversample from the time precision of the double oversample. The configuration of the timing high-definition unit 207A is the same as that of the timing high-precision unit 207 shown in FIG. 2, but the number of inputs and outputs is different. Here, in order to deal with the correlation power, the correction coefficient Gp corresponding to the power is used.

The output of the timing high-accuracy means 207A is input to the timing control means 243 to perform timing control. This timing control method performs initial setting such that the correlation value of timing 0, 1 / 2Tc, Tc, 3 / 2Tc of any one of the delay circuits 242A to 242C is maximized by the synchronization acquisition timing given by the control section, And thereafter, timing control is performed so that the maximum correlation value is included in any one of the delay circuits 242A to 242C. However, since the clock for driving the spreading code is twice the chip rate, only clock control is performed for every [1/2] Tc. The remaining finer control is coped with by switching between the amplifier outputs S1, S3, S5, and S7 or the addition outputs S2, S4, and S6 in the high-precision conversion unit 212A to give the maximum correlation value by symbol demodulation.

8 includes a delay circuit 244 for delaying the output of the complex correlator 232B and a high-precision means 212A for receiving the output of the complex correlators 237B and 237C. Although not shown in the figure, the symbol demodulation is also completed by performing phase compensation on the correlation symbol output from the high-definition unit 212A. The configuration of the high-definition unit 212A is the same as that of FIG. 2 except that the input / output is a complex signal (in-phase axis signal, orthogonal axis signal) and the same operation is performed separately for each signal. In this high-definition means 212A, a correlation symbol with high timing accuracy is selected and output in accordance with a selection signal given in accordance with the timing control means 243.

The maximum correlation value is S1, S2, ... ... , S6, and S7 will be described. First, when the maximum correlation value shifts from S3 to S4, the high-precision conversion means 212A also instructs the corresponding maximum correlation value to change from the output of the complex correlator 237B to the addition output of the complex correlators 237B and 237C. Next, when the maximum correlation value changes from S4 to S5, similarly, the high-definition unit 212A instructs to select the amplified output of the complex correlator 237C. When the maximum correlation value shifts from S5 to S6, the timing control means 243 instructs the pulse inserting / deleting circuit 245 to delete the pulse, and performs timing control so that the maximum value is S4. Then, the high-precision conversion means 212A also instructs the maximum correlation value to select the addition output of the complex correlators 237B and 237C.

With this control, demodulation characteristics and synchronous tracking characteristics with a 4-times oversampling precision can be obtained while using a circuit operating with a timing accuracy of 2 times oversample, and low power consumption can be realized. In FIG. 8, since the correlation values Sl and S7 are not used for control as actual problems, this portion may be omitted. In RAKE reception, when the demodulation timings of a plurality of symbol demodulation units are adjacent to each other, it can be used for monitoring to prevent a plurality of demodulation units from simultaneously receiving a reception signal of the same timing. In addition, although not particularly described in the conventional example, in many cases, the correlation characteristic is not symmetrical under the above circumstances. In this case, if the DLL configuration is employed, accurate reception timing may not be obtained. Therefore, The operation of the form has an effect of giving a stable demodulation characteristic.

Fig. 9 is similar to Fig. 8, and corresponding parts are denoted by the same reference numerals, except that the timing at which the maximum value is obtained is not directly tracked, but the synchronization trace configuration by the DLL is basically different. In the DLL, there is a problem as pointed out in Fig. 8, but since the problem can be expected to be prevented to a certain extent by using the signal search result of the search base, the configuration of Fig. 9 is simplified as compared with the configuration of Fig. .

In order to perform the DLL operation, an error signal is generated from the correlation calculation results of the timings (E, L) described with reference to Figs. 27A and 27B, and the symbol is demodulated from the correlation value at timing (O). Fig. 11 shows a control method therefor. Timing may be controlled so as to perform symbol demodulation and error signal generation in accordance with the timing and timing setting method of giving the maximum average correlation power shown in Fig. In the case of the DLL, the timing of giving the maximum average correlation power corresponds to the timing at which the error signal becomes minimum.

T1, T2, T3 and T4 in FIG. 11 are the correlation timings of Sl, S3, S5 and S7 in FIG. 8, and M1, M2 and M3 are the timings S2, S4 and S6 of the center points of the respective correlation timings. At this time, if the correlation power of the timing T2 is maximum, the control of the first column of the table is performed. That is, as the symbol timing (?), The correlation value obtained at the timing (T2) is output from the high-precision means and the timing (E, L) of the correlation power for generating the error signal is set as the timing (T1, .

In the obtained error signal, when it is necessary to change the timing of giving the maximum correlation power from T2 to M2, control is performed in the second column. That is, the symbol timing (O) is changed to M2, and the timings of E and L for generating the error signal are changed to Ml and M3, respectively, but the clock of the spread code generator 238 is not changed. When it is necessary to change the timing of giving the maximum correlation value from M2 to T3, the third column is controlled. That is, the symbol timing (O) is changed to T3 and the error signal timings (E, L) are changed to T2 and T4, respectively, but the clock of the spread code generator 238 is not changed.

When it is necessary to change the timing of giving the maximum correlation value from T3 to M3 in the obtained error signal, the fourth column is controlled. 8, the maximum correlation value can not be obtained at the timings of T2, M2, and T3. Therefore, the timing control means 243 controls the pulse inserting / deleting circuit 245 to give the maximum correlation value (In this case, a deletion signal) so that the timing becomes M2. As the pulse insertion / deletion circuit 245, pulse insertion and deletion are performed for twice the chip rate clock in accordance with the control signal, and the timing control is performed in [1/2] Tc units. This control is indicated by an arrow in the fourth column of the table. And the symbol timing (O) is changed from M3 to M2.

However, in the case of updating the control, for example, when the designation of the timing is changed, the timing designation after the change is maintained until the average correlation power for the new timing is obtained in the averaging means 241A to 241D.

8 and 9, it is possible to share a correlator between the symbol demodulator and the synchronizer, and the timing control of the spread code is at most two times the chip rate, but the timing accuracy of the synchronizer It is possible to demodulate and demodulate symbols, and low power consumption can be realized. Further, since the high-precision means in the synchronism tracking portion is also performed on the average correlation power value, the amount of computation is small compared with the method using high-precision samples from the beginning, and the time required for the average of the correlation power It is good to perform computation and control for high precision and it can be said that the increase in the amount of computation required for high precision is extremely small in view of the throughput of the entire hardware.

Fig. 8 and Fig. 9 are suitable for a RAKE receiver having a plurality of such configurations because the hardware scale can be reduced and the power consumption can be reduced. 8 and 9 illustrate a general symbol demodulating unit and a synchronous estimating unit. However, this method is applicable to the synchronous estimating unit and the symbol demodulating unit shown in FIG. 31 or FIG. 32 as they are. The application method thereof will be described below.

FIG. 10, in which the same reference numerals are given to the corresponding parts in FIG. 9, shows an embodiment of a symbol demodulating unit for performing synchronous detection using the pilot signal according to the present invention and a synchronous tracking unit, and corresponds to FIG. 31 and FIG. 32 shows one correlator for symbol demodulation and two correlators for error signal generation although they are not shown in detail in the drawing. In this embodiment, four correlator units are prepared and shared by the sync tracker and the symbol demodulator. The delay circuits 239A to 239C, 242A to 242C, 252A, 252B and 253 are for adjusting respective timing relationships. The multipliers 254A and 254B commonly acquire the Wa1sh function for the despread in-phase and quadrature axis receive signals in the QPSK despreaders 250B and 250C, respectively, in order to identify the orthogonally multiplexed information symbols . Since the handling of a highly accurate correlation power in FIG error signal generator 247, a pilot signal correction factor is G _P, high precision means (255A, 255B are values each symbol correlation, since the handle value pilot correlation correction factor G _A to be.

The operation of the high-precision error signal generating means 247 and the timing control means 243 is the same as that shown in Figs. 8 and 9. Fig. The highly accurate correlation calculation result of the information symbol is selected and output in the high-precision conversion means 255A according to the timing at which the maximum correlation value given from the timing control means 243 is obtained. Similarly, in the high-precision conversion means 255B, The result of the correlation calculation of the signal is selected and outputted. In the data scale phase rotation unit 112, phase compensation is performed based on the pilot signal, weighting is performed by the reception amplitude, and a demodulation symbol is output.

Although not shown in the figure, the output result is guided to the symbol synthesizing unit 107 of Fig. 31, but as disclosed in Japanese Patent Application Laid-Open No. 94-14008, timing adjustment by FIF The demodulation symbol is retained by the latch circuit until the demodulation symbol of the overturning god is determined and synthesized at the time when the overtone modulation symbol is determined by the symbol synthesizing unit 107. This reduces the FIFO size and lowers the power consumption An effect which can be further improved can be obtained.

According to the configuration shown in Fig. 10, the symbol demodulation characteristic and the synchronization trace characteristic with the 4-times oversampling precision can be realized with the timing accuracy of the 2-times oversample as in the case of Figs. 8 and 9, and the power consumption can be reduced. In addition, since the high-precision means in the synchronism tracking portion is performed with respect to the average correlation power, the increase in the amount of computation can not be seen from the overall configuration. Including the reduction of the FIFO also provides the effect of reducing the hardware scale and reducing the power consumption without deteriorating the timing accuracy.

(Example 7)

12 and 13 are embodiments in which the configurations of Figs. 8 and 9 are extended and applied to the inverse modulation type synchronous DLL of Fig. 26, respectively, and corresponding parts are denoted by the same reference numerals. 12 shows an embodiment in which the timing control is performed so that the maximum value of the seven correlated powers that have been highly precise by the timing precise means 207A is at the center of the three timings. Fig. 13 shows the high precision error signal generating means 262, The timing control is performed from an error signal obtained by high precision. The channel estimation unit 260, the temporary judgment unit 261 for the demodulation symbol, the inverse modulation unit 258A to 258D, and the DLL in the result of the inverse modulation are the same as those in FIG. 26, (237A to 237D), a correlation value at a timing accuracy of twice oversampling is obtained, and the timing accuracy of the oversampling is made to be high at the timing accuracy of 4 times oversample by the timing high-precision means 207A.

Precision measuring means 259A and 259B are provided before the channel estimating means 260 and the trellis measuring means 261 in order to use correlation values in which the channel estimation and the trellis correction timing are made highly accurate. As a result, since channel estimation and trellis adjustment are performed with high-precision timing, there is an effect that a high-precision symbol demodulation characteristic and synchronous tracking characteristic can be obtained regardless of using only the correlation value of the timing accuracy of double oversampling . That is, there is an advantage that the power consumption can be reduced as compared with the conventional configuration example for realizing the same precision.

8 to 13, the circuit configuration is also simple because the control unit is a control unit of timing control [1/2] Tc chip, and the RAKE receiver It is relatively easy to control because it is only necessary to identify the timing management for constituting, the amplification of the correlation value, and the correlation value of the center point. In FIGS. 12 and 13, all of the correction coefficients G _A are used because the high-precision means 259A and 259B and the timing high-accuracy means 207A and 262 are all performed on the correlation value.

(Example 8)

Fig. 14 corresponds to Fig. 33 as one embodiment of a RAKE receiver using a digital matched filter according to the present invention. As in the other embodiments, the correlation samples are subjected to correlation calculation with a two-times oversampling timing accuracy in parallel by a correlator operating on a chip basis, with reception samples shifted by Tc [1/2] of the timing, 232, and 266 to a 4-times oversampling precision.

FIG. 14 is a diagram showing a portion for detecting and averaging the correlated power of the multipath reception signals in the same manner as the embodiment shown in FIG. 6, and corresponding portions are denoted by the same reference numerals. 14, the parameters of the averaging unit 52 (the weight of the cyclic adder, the number of cyclic additions, and the like) are different from each other because the target is the synchronization acquisition or signal search in FIG. 6, whereas FIG. 14 is the determination of the signal strength for RAKE reception . In Fig. 14, the output of the continuous high-precision conversion unit 232 is stored in the shift register 267 until the next cyclic addition result is obtained, resulting in a weight coefficient for RAKE synthesis.

Regarding the symbol demodulation system, the digital matched filter output is phase-compensated according to the phase-compensating means 265A and 265B, and is synchronously detected to be a demodulated symbol. The phase compensation method is not shown in Fig. 14, but is implemented using, for example, the method described in Figs. 26 and 32, or a general digital Costas loop. Although not shown in the figure, the timing adjustment means are included in the phase compensation means 265A and 265B so as to coincide with the timing of the output of the continuous high-precision means with respect to the timing delay or the like caused by these phase compensation. Then, using the correction coefficient for the correlation value according to the continuous high-precision conversion means 266, it is made high-precision with a 4-times oversampling precision and is stored in the shift register 268 at each symbol interval, The shift register 267 is added to the adder 270, and RAKE synthesis is realized.

As described in the above embodiment, even when a digital matched filter is used, RAKE synthesis is realized with a 4-times oversampling precision using the result of correlation calculation with double-oversampling accuracy. Therefore, it is possible to achieve reduction in hardware scale and reduction in power consumption. 14 and FIG. 6 show a large portion that can be shared, and by combining them with each other efficiently, further downsizing and lower power consumption can be achieved.

It is also possible to limit the number of stages of the shift register units 267 and 268 in accordance with the delay profile characteristics, thereby reducing the hard scale. It is then necessary to control the input sample timing so that the received sample is clamped within the limited shift register. As this control method, for example, there is a method disclosed in Japanese Patent Laid-Open Publication No. 92-347944. This method is realized according to the result of the correlation calculation of the timing accuracy of the double oversampling. However, by using the correlation value obtained by making the accuracy high by four times according to the method given in the present embodiment, It is possible to perform the control in accordance with the control signal.

In the first to eighth embodiments, the configuration in which the sliding correlator is used and the configuration in which the digital matched filter is used are shown, respectively. For example, in a RAKE receiver, a configuration may be considered in which a searcher unit uses a digital matched filter, a symbol demodulator uses a sliding correlator, and a synchronization correlator uses a sliding correlator. Combinations can also be made using the method disclosed in this embodiment Do.

In the third and eighth embodiments, the matched filter is shown only for the digital matched filter. However, even in the case of using the analog matched filter, since the sample rate is limited when A / D conversion is performed after the A / D conversion, The method disclosed in the present invention becomes effective.

In the second, sixth, and seventh embodiments, the high-precision unit used in the symbol demodulation unit always outputs the amplified correlation calculation result when a value other than the estimated value of the central point is selected. This is also necessary in order to unify the reliability of the estimated correlation value and the amplified correlation value when the RAKE reception is weighted and also to unify the number of bits of the digital processing.

In the first to eighth embodiments, a case has been described centering on the case of estimating only the timing center point by using the addition result of the two as a method of estimating the timing point, in which the correlation value is not directly obtained. However, since there are many estimation methods, correlation values other than the center point can be easily estimated by applying them, and the same effect can be obtained even if symbol demodulation, synchronous estimation, and synchronous acquisition are performed using the estimation results . Estimation methods include, for example, Nyquist interpolation, Hermitian interpolation, and second interpolation. Nyquist interpolation is an interpolation based on Nykest's sampling theorem.

Claims (3)

A spread spectrum signal receiving method for performing a correlation operation with a spreading code with respect to a baseband component of a spread spectrum reception signal and demodulating the reception signal, A first correlation calculation step of performing a correlation calculation between a spreading code and a baseband component when a correlation operation between a spread spectrum signal baseband component and a spreading code is performed; A second correlation calculation step of performing a correlation calculation at a timing at which the timing relationship between the spreading code and the baseband component in the first step is 1/2 of the spreading code interval, And estimating a correlation calculation result at a timing point whose timing relationship is 1/2 or less using the results of the first and second steps. A spread spectrum signal receiving method for performing a correlation operation with a spreading code with respect to a baseband component of a spread spectrum reception signal and demodulating the reception signal, A first correlation operation step of performing a correlation operation between a spreading code and a baseband component; A second correlation operation step of performing a correlation operation between the spreading code and the baseband component by offsetting the spreading code by 1/2 of the code interval, An estimation step of estimating a correlation calculation result of two timing center points by adding the first correlation calculation result and the second correlation calculation result, A first weighting step of weighting the first correlation calculation result and a second weighting result of the second correlation calculation result, And an optimum timing selecting step of selecting a correlation calculation result or an estimation result of an optimal timing from the calculation step of the first and second weighting steps. A receiver of a spread spectrum signal for performing a correlation operation with a spreading code with respect to a baseband component of a spread spectrum reception signal and demodulating the reception signal, Spread code generating means for generating a spread signal, Delay means for delaying the spreading code generated by the spreading code generating means in a plurality of stages, A plurality of correlation calculating means for performing a correlation operation between the baseband component and the spreading code and a spreading code delayed in the plurality of steps, A plurality of squaring means for obtaining correlation powers from the calculation results of the correlation calculating means, A plurality of averaging means for performing averaging operation on the correlation power to obtain average correlation power, Timing adjusting means for adjusting timing at which said plurality of average powers are obtained; Timing correcting means for estimating an average correlation power of a timing center point at which a correlation power is obtained by using a plurality of average correlation power whose timings are adjusted; Timing control means for performing timing control from the highly accurate average correlation power, Clock control means for controlling a spread code clock in accordance with a control result of the timing control means, And a high precision means for selecting and outputting a maximum correlation calculation result among correlation calculation results of a plurality of correlation calculation results and a timing center point estimated from the calculation result in accordance with the control result of the timing control means Receiving device.