KR102551536B1 - Display device and driving method thereof - Google Patents

Abstract

The present invention relates to a display device and a method for driving the same. In a pixel array of the display device, a resolution of a first resolution region is fixed, and a resolution of a second resolution region is varied according to output signals of a data driver and a gate driver.

Description

Display device and its driving method {DISPLAY DEVICE AND DRIVING METHOD THEREOF}

The present invention relates to a display device having a partially different screen resolution and a method for driving the same.

Flat panel displays include liquid crystal displays (LCDs), electroluminescence displays (ELDs) such as organic light emitting diode displays (OLED displays), and field emission displays (Field Emission Displays). Display, FED), plasma display panel (PDP), electrophoresis display (EPD), and the like.

The screen of the display panel includes a pixel array in which pixels are arranged in a matrix form to display an input image. The pixel array of this display panel is generally manufactured with a single resolution. In the prior art, the resolution of the input image can be changed by converting the resolution of the input image data, but the physical resolution of the display panel cannot be changed.

In the method of changing only the data resolution of the input image without changing the physical resolution of the display panel, it is difficult to realize a desired level of image quality of the display image. Conventional display devices have limited utilization because the physical resolution of the screen is a single resolution.

Accordingly, an object of the present invention is to provide a display device capable of partially differentiating the physical resolution of a display panel and a driving method thereof.

The display device of the present invention includes a display panel including data lines, gate lines crossing the data lines, and a pixel array in which pixels are arranged in a matrix form and divided into a first resolution area and a second resolution area. do. The display device includes a data driver that converts data of an input image into data voltages and supplies them to the data lines, a gate driver that supplies gate pulses to the gate lines, and supplies the data of the input image to the data driver. and a timing controller controlling the data driver and the gate driver. A resolution of the first resolution region is fixed, and a resolution of the second resolution region is varied according to output signals of the data driver and the gate driver.

The method of driving the display device includes controlling a resolution of the second resolution area to be higher than that of the first resolution area when a virtual reality application is executed.

According to the present invention, the physical resolution of a pixel array on a screen of a display panel may be partially different, and the resolution of a part of the pixel array may be varied by controlling output signals of a gate driver and a data driver. Furthermore, the present invention can improve the user's sense of immersion by reducing the screen door effect by increasing the resolution of only a portion of the screen that the user sees in special applications such as virtual reality, and can reduce power consumption by lowering the resolution of the pixel array in a general use environment. can

1 is a schematic block diagram of a display device according to an exemplary embodiment of the present invention.
2 and 3 are diagrams showing pixel structures of first and second resolution regions according to an embodiment of the present invention.
4 is a waveform diagram showing gate pulses when the second resolution region is driven as a low resolution region and gate pulses when the second resolution region is driven as a high resolution region.
5 is a diagram showing an example in which the display device of the present invention is applied to a smart phone.
6 is a view showing a display device according to another exemplary embodiment of the present invention.
7 and 8 are diagrams showing examples of using the display device of the present invention for implementing virtual reality (VR) in a smartphone.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. Like reference numbers throughout the specification indicate substantially the same elements. In the following description, if it is determined that a detailed description of a known function or configuration related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description will be omitted. Component names used in the following description may be selected in consideration of the ease of writing specifications, and may be different from names of parts of actual products.

The display device of the present invention may be implemented with various flat panel display devices such as a liquid crystal display (LCD) and an organic light emitting diode display (OLED display).

The screen includes a pixel array on which an input image is displayed. The pixel array is divided into a first resolution area and a second resolution area, and each of the resolution areas includes a plurality of pixels arranged in a matrix form. The pixels may include red (R), green (G), and blue (B) sub-pixels for color implementation. Also, the pixels may further include white sub-pixels. The pixels may further include one or more of Cyan (C), Magenta (M), and Yellow (Y) sub-pixels.

The first and second resolution regions have the same pixel structure. While one physical resolution of the first and second resolution regions is fixed, the other physical resolution may be variable. Here, the physical resolution does not change only by converting image data, but refers to a resolution that varies according to a connection relationship between subpixels. Hereinafter, it is assumed that the physical resolution of the first resolution area is fixed, and the second resolution area is a variable physical resolution area.

Referring to FIG. 1 , the display device of the present invention includes a display panel 100 and a display panel driving unit that writes data of an input image to pixels of the display panel 100 .

The display panel 100 includes a pixel array divided into first and second resolution areas. The pixel array includes data lines DL to which data voltages are supplied, gate lines (or scan lines, GL) crossed with the data lines DL and to which gate pulses (or scan pulses) are supplied, and data lines. It includes pixels arranged in a matrix form defined by the intersections of DL and gate lines GL. Each of the pixels may include one or more thin film transistors (TFTs) and capacitors.

The display panel driver includes a data driver 101 , a gate driver (or scan driver) 102 , and a timing controller 103 . The data driver 101 converts the digital video data DATA of the input image input from the timing controller 103 into an analog gamma compensation voltage to generate a data voltage and supplies the data voltage to the data lines DL. . The gate driver 102 generates gate pulses synchronized with the data voltage, shifts the gate pulses, and sequentially supplies them to the gate lines GL.

The timing controller 103 receives data (DATA) of an input image from the host system 200 and also receives a timing signal synchronized with the data. Timing signals synchronized with the data DATA of the input image include vertical/horizontal synchronization signals Vsync and Hsync, a data enable signal DE, and a main clock CLK.

The timing controller 103 transmits data DATA of an input image to the data driver 101 . Also, the timing controller 103 provides timing control signals DDC and GDC for controlling the operation timing of the data driver 101 and the gate driver 102 using the timing signals Vsync, Hsync, DE, and CLK. generated and controls the drive units 101 and 102.

The host system 200 may be any one of a television system, a set-top box, a navigation system, a DVD player, a Blu-ray player, a personal computer (PC), a home theater system, and a phone system. The host system 200 transmits input image data and timing signals Vsync, Hsync, DE, and CLK to the timing controller 103, and generates power required to drive the display panel and its drivers.

The host system 200 may change the resolution of the input image by using a scaler and transmit it to the timing controller 103 . The host system 200 may vary the resolution of the input image data according to a user command through a user interface or an application program to be executed.

The physical resolution of the first resolution area of the display panel 100 is fixed. The second resolution area of the display panel 100 may display an image with a resolution higher than that of the first resolution area or a resolution lower than that of the first resolution area. According to the present invention, a part of the screen, that is, the second resolution area can be implemented as a high resolution area in a special use, and power consumption can be reduced by lowering the resolution of the second resolution area in a general use environment. The timing controller 103 may control outputs of the driving units 102 and 103 to drive only pixels in the second resolution area without driving pixels in the first resolution area in a special application. Of course, both pixels of the first and second resolution regions may be driven in a special application.

2 and 3 are diagrams showing pixel structures of first and second resolution regions according to an embodiment of the present invention. 2 and 3 show a portion of a pixel array. In Fig. 3, the TFT is omitted.

Referring to FIGS. 2 and 3 , the first resolution area RD1 is an area defined by first to fourth lines L1 to L4 and first to twelfth columns C1 to C12. . The second resolution area RD2 is defined by the first to fourth lines L1 to L4 and the thirteenth to eighteenth columns C13 to C18. 2 and 3, R is the first color (Red) and G is the second color (Green). B is the third color (Blue).

In each of the first resolution region RD1 and the second resolution region RD1, the subpixels R1 to G8 are fabricated to have the same size. The sub-pixels R1 to B4 included in the pixel PIX1 of the first resolution region RD1 are divided due to the connection structure of the gate lines Gn to Gn' and the data lines Dx to Dx+2. 2 It is more than the pixels of the resolution area RD2.

In the examples of FIGS. 2 and 3 , one pixel PIX1 in the first resolution region RD1 is divided into 12 sub-pixels R1 to B4. In the first pixel PIX1 , two gate lines are connected to each other and the same gate pulse is applied to the gate lines. Within the first pixel PIX1 , two data lines connected to each other connect sub-pixels of the same color to supply the same data voltage to the sub-pixels. For each color, two data lines connect sub-pixels of the same color.

Each of the pixels PIX2 to PIX5 in the second resolution region RD2 includes three sub-pixels. In the examples of FIGS. 2 and 3 , the physical resolution of the second resolution area RD2 is four times higher than that of the first resolution area RD1. For example, if the first resolution area RD1 is a full high definition (FHD) area, the second resolution area RD2 is an ultra high definition (UHD) area. The first and second resolution regions RD1 and RD2 are not limited to those of FIGS. 2 and 3 . For example, the resolutions of the first resolution regions RD1 and RD2 may be made lower than those of FIG. 2 by changing gate lines and data lines of the first resolution region RD1 as shown in FIG. 6 .

The first pixel PIX1 includes four first color subpixels R1 , R2 , R3 , and R4 , four second color subpixels G1 , G2 , G3 , and G4 , and four third color subpixels. It includes pixels B1, B2, B3, and B4. The first color subpixels R1 , R2 , R3 , and R4 are spaced apart from each other but are physically connected through gate lines 21 and 22 and data lines 31 and 32 . A second color subpixel G1 and a third color subpixel B1 may be disposed between the first color subpixels R1 and R2 disposed on the same line. Since the gate lines 21 and 22 short circuited to each other are connected to the subpixels R1 to B4 in the first pixel PIX1, the data voltage is simultaneously supplied to the subpixels R1 to B4. do. At this time, the first data voltage is supplied to the first color subpixels R1, R2, R3, and R4, and the second data voltage is supplied to the second color subpixels G1, G2, G3, and G4. . At the same time, the third data voltage is supplied to the third color sub-pixels B1, B2, B3, and B4.

Subpixels R1 to B4 of the first pixel PIX1 are separated by gate lines 21 and 22 and data lines 31 to 36 . The first gate line 21 is connected to the subpixels R1 to B2 arranged on the first line L1. The second gate line 22 is connected to the subpixels R3 to B4 arranged on the second line L2. The first and second gate lines 21 and 22 are connected to the first channel Gn of the gate driver 102 . The gate driver 102 simultaneously supplies a first gate pulse to the first and second gate lines 21 and 22 through the first channel Gn.

The first and second data lines 31 and 32 are connected to the first channel Dx of the data driver 101 . The data driver 101 supplies the same first data voltage to the first and second data lines 31 and 32 through the first channel Dx. Accordingly, the first data voltage is simultaneously supplied to the first color subpixels R1 , R2 , R3 , and R4 arranged on the first and second lines L1 and L2 .

The third and fourth data lines 33 and 34 are connected to the second channel Dx+1 of the data driver 101 . The data driver 101 supplies the same second data voltage to the third and fourth data lines 33 and 34 through the second channel Dx+1. Accordingly, the second data voltage is simultaneously supplied to the second color subpixels G1 , G2 , G3 , and G4 arranged on the first and second lines L1 and L2 .

The fifth and sixth data lines 35 and 36 are connected to the third channel Dx+2 of the data driver 101 . The data driver 101 supplies the same third data voltage to the fifth and sixth data lines 35 and 36 through the third channel Dx+2. Accordingly, the third data voltage is simultaneously supplied to the third color subpixels B1 , B2 , B3 , and B4 arranged on the first and second lines L1 and L2 .

In the second resolution region RD2, 12 sub-pixels R5 to B8 are disposed in four pixels PIX2 to PIX5. The gate lines 21 and 23 disposed in the second resolution region RD2 are connected to different channels in the gate driver 102 and driven independently. The gate driver 102 supplies a first gate pulse to the second and third pixels PIX2 and PIX3 through the first gate line 21 connected to the first channel Gn. The gate driver 102 provides second gates to the sub-pixels R7 to B8 of the fourth and fifth pixels PIX4 and PIX5 through the third gate line 23 connected to the second channel Gn'. supply pulses. The fourth to ninth channels (Dy to Dy+5) of the data driver 101 are connected to the sixth to twelfth data lines 37 to 42 in a 1:1 ratio. The data driver 101 supplies data voltages to each of the sixth to twelfth data lines D37 to 42 through the fourth to ninth channels Dy to Dy+5.

The first gate line 21 crosses the first and second resolution regions RD1 and RD2 and is connected to the subpixels R1 to B6 of the resolution regions RD1 and RD2. The second and third gate lines 22 and 23 are disposed along the same straight line between the second and third lines L2 and L3 and are electrically isolated from each other. The second gate line 22 is disposed only in the first resolution region RD1 and is connected to the subpixels R3 to B4 disposed on the second line L2. The third gate line 23 is disposed only in the second resolution region RD2 and is connected to the subpixels R7 to B8 disposed on the second line L2. The third gate line 23 is separated from the first and second gate lines 21 and 23 and driven independently from the gate lines 21 and 22 .

The gate driver 102 may be divided into a first GIP (Gate in panel) circuit GIP1 and a second GIP circuit GIP2 as shown in FIG. 3 . The first and second GIP circuits GIP1 and GIP2 may be disposed on the display panel 100 to be separated into both sides with the pixel array interposed therebetween. The first GIP circuit GIP1 may supply gate pulses to the gate lines 21 and 22 connected to the pixels of the first resolution region RD. The second GIP circuit GIP2 may supply gate pulses to gate lines 21 and 23 connected to pixels of the second resolution region RD. The first gate line 21 may be connected among the first and second GIP circuits GIP1 and GIP2. In this case, a gate pulse is applied through one end of the first gate line 21 . One end of the first gate line 21 may be connected to the channel of the first GIP circuit GIP1, and the other end of the first gate line 21 may be connected to the channel of the first GIP circuit GIP1. In this case, gate pulses are simultaneously applied to both sides of the first gate line 21 .

The second pixel PIX2 includes a first color sub-pixel R5 , a second color sub-pixel G5 , and a third color sub-pixel B5 disposed on the first line L1 . The third pixel PIX3 includes a first color sub-pixel R6 , a second color sub-pixel G6 , and a third color sub-pixel B6 disposed on the first line L1 . Since the first gate line 21 is connected to the subpixels R5 to B6 of the second and third pixels PIX2 and PIX3, data voltages are simultaneously supplied to the subpixels R5 to B6. Since the independent data lines 37 to 42 are connected to the subpixels R5 to B6, respectively, the subpixels R5 to B6 can be charged with data voltages supplied through different data lines.

The fourth pixel PIX4 includes a first color sub-pixel R7 , a second color sub-pixel G7 , and a third color sub-pixel B7 disposed on the second line L2 . The fifth pixel PIX5 includes a first color subpixel R8, a second color subpixel G8, and a third color subpixel B8 disposed on the second line L2. Since the third gate line 23 is connected to the subpixels R7 to B8 of the fourth and fifth pixels PIX4 and PIX5, data voltages are simultaneously supplied to the subpixels R7 to B8. The third gate line 23 applies the second gate pulse from the second channel Gn' of the gate driver 102 to the subpixels R7 to B8 of the fourth and fifth pixels PIX4 and PIX5. supply at the same time Since the independent data lines 37 to 42 are connected 1:1 to the subpixels R7 to B8, the subpixels R7 to B8 can charge data voltages supplied through different data lines. there is.

The timing controller 103 may change the resolution of the second resolution region RD2 by controlling the data driver 101 and the gate driver 102 .

As shown in FIG. 4(A), gate pulses are simultaneously applied to the first and second gate lines 21 and 23 through the first and second channels Gn and Gn' of the gate driver 102, and the same When the same data voltage is supplied to data lines connected to color subpixels, the second resolution area RD2 is driven as a low resolution area. When the second resolution region RD2 is driven at a low resolution, the data driver 101 supplies the same data voltage to channels Dy and Dy+3 and supplies the same data voltage to channels Dy+1 and Dy+4. do. Also, the data driver 101 supplies the same data voltage to channels Dy+2 and Dy+5. When the second resolution region RD2 is driven as a low resolution region, the resolution of the second resolution region RD2 may be the same as that of the first resolution region RD1.

As shown in FIG. 4 (B), gate pulses are sequentially applied to the first and second gate lines 21 and 23 through the first and second channels Gn and Gn' of the gate driver 102, When independent data voltages are supplied to the data lines 37 to 42, the second resolution area RD2 is driven as a high resolution area.

The display device of the present invention can be applied to various devices. 5 is a diagram showing an example in which the display device of the present invention is applied to a smart phone. In FIG. 5, “DIC” is a drive IC. A data driver 101, a timing controller 103, and the like are integrated in a drive IC (DIC).

6 is a view showing a display device according to another exemplary embodiment of the present invention. 6 is an example in which the resolution of the first resolution area is lowered. 6, Gn to Gn+1" are channels from which gate pulses are output from the gate driver 102. Dx to Dy+5 are channels to which data voltages are output from the data driver 101.

Referring to FIG. 6 , each of the pixels of the first resolution region RD1 includes 27 sub-pixels. Within the pixel of the first resolution region RD1, three gate lines are connected to each other and the same gate pulse is applied to the gate lines. Within a pixel of the first resolution region RD1, three data lines connected to each other connect sub-pixels of the same color to supply the same data voltage to the sub-pixels. For each color, two data lines connect sub-pixels of the same color. The second resolution area RD2 is substantially the same as the above-described embodiments of FIGS. 2 and 3 .

The first and second resolution regions RD1 and RD2 are not limited to those of FIGS. 2, 3, and 5 and may be variously modified in position, shape, etc. to suit the application. 7 and 8 are views showing the use of the display device of the present invention to implement virtual reality (VR) in a smartphone.

A user connects a smartphone to a Head Mounted Display (HMD) device and executes a virtual reality application to enjoy a three-dimensional view of a virtual reality image. In order to utilize a smartphone as a VR device, the user's sense of immersion can be enhanced by designing the high-resolution second resolution region RD2 as regions facing each of the user's left and right eyes. In the VR device, a fisheye lens (LENS) exists between the user's eyes and the display panel, and the distance between the user's eyes and the display panel 100 is very short, about several centimeters. When the user views the reproduced image on the display panel 100 through the fisheye lens LENS, the user sees an image 4 to 5 times larger than the actual image displayed on the screen of the display panels 100 . If the resolution of the pixel array viewed by the user is low in such an environment where close-up view and fisheye lens are applied, the pixels are enlarged and the screen door effect is strongly recognized, reducing the user's sense of immersion. As shown in FIGS. 7 and 8 , the first area facing the user's left eye and the second area facing the user's right eye on the screen of the display panel 100 coupled to the VR device are defined as a high-resolution second resolution area RD2. If designed as a screen door effect, it is possible to improve the user's immersion. When used for VR devices, the present invention may drive only the second resolution region RD2 without driving the first resolution region RD1 in order to reduce power consumption.

A pair of fisheye lenses LENS are disposed in front of the separated second resolution area RD2 of the display panel 100 when the display device of the present invention is used as a VR device. A pair of fisheye lenses LENS are implemented as ultra-wide-angle lenses for widening the angle of view of the user's left and right eyes.

According to the present invention, power consumption can be reduced by controlling the resolution of the second resolution area RD2 to the same low resolution as the first resolution area RD1 in a general use environment in which a VR application or a purpose other than a VR device is executed. . At this time, the first and second resolution regions RD1 and RD2 are driven together.

Through the above description, those skilled in the art will know that various changes and modifications are possible within the scope without departing from the technical spirit of the present invention. Therefore, the present invention should not be limited to the contents described in the detailed description, but should be defined by the claims.

100: display panel 101: data driving unit
102, GIP1, GIP2: gate driver 103: timing controller
200: host system

Claims (11)

a display panel including data lines, gate lines crossing the data lines, and a pixel array in which pixels are arranged in a matrix form and divided into a first resolution area and a second resolution area;
a data driver that converts data of an input image into data voltages and supplies them to the data lines;
a gate driver supplying gate pulses to the gate lines; and
a timing controller supplying data of the input image to the data driver and controlling the data driver and the gate driver;
The resolution of the first resolution region is fixed, and the resolution of the second resolution region is variable according to output signals of the data driver and the gate driver;
The gate lines are
a first gate line connected to subpixels disposed on a first line in the first and second resolution regions across the first and second resolution regions;
a second gate line connected to the first gate line and connected to subpixels disposed on a second line of the first resolution region; and
a third gate line separated from the first and second gate lines and connected to subpixels disposed on a second line of the second resolution region;
The display device of claim 1 , wherein gate lines disposed in the second resolution region are independently driven by being connected to different channels in the gate driver. According to claim 1,
Each of the pixels is divided into a plurality of sub-pixels having different colors;
The display device of claim 1 , wherein the number of subpixels constituting one pixel in the first resolution region is greater than the number of subpixels constituting one pixel in the second resolution region. delete According to claim 1,
The data lines are
a plurality of data lines arranged in the first resolution area;
A plurality of data lines arranged in the second resolution area;
For each color within the first resolution region, a plurality of data lines are connected to each other and connected to sub-pixels of the same color;
The display device of claim 1 , wherein data lines arranged in the second resolution area are separated from each other and driven independently. According to claim 1,
A resolution of the second resolution region is greater than or equal to the first resolution region. According to claim 1,
The second resolution area includes a first area facing the user's left eye and a second area facing the user's right eye. According to claim 6,
When a virtual reality application is executed, a resolution of the second resolution region is higher than that of the first resolution region, and only the second resolution region among the first and second resolution regions is driven. According to claim 7,
The display device of claim 1 , wherein a resolution of the second resolution region is the same as that of the first resolution region when a virtual reality application is not executed, and the first and second resolution regions are driven together. delete delete delete

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