KR101924621B1 - Image display device - Google Patents

Abstract

A display panel including a plurality of pixels for selectively displaying a 2D image and a 3D image; A pattern driver configured to split the light from the display panel into first and second polarized lights; And generates a first discharge control voltage at an off level and generates a second discharge control voltage at a slit-on level higher than the off level and lower than a full-on level, And a control voltage generator for selectively outputting the two discharge control voltages; A first pixel of the pixels includes a first upper main display having a first pixel electrode connected to a data line via a first switch; And a second pixel electrode connected to the data line through a second switch driven at the same timing as the first switch, and the second pixel electrode is connected to the common line A first upper auxiliary display portion having a first discharge control switch connected to the first auxiliary auxiliary display portion; And a third pixel electrode connected to the data line through a third switch.

Description

IMAGE DISPLAY DEVICE [0002]

The present invention relates to an image display apparatus capable of selectively implementing a two-dimensional plane image (hereinafter, referred to as a '2D image') and a three-dimensional stereoscopic image (hereinafter, referred to as a '3D image').

Due to the development of various contents and circuit technology, the recent image display device can selectively implement the 2D image and the 3D image. The image display device implements a 3D image using a binocular stereoscopic technique or an autostereoscopic technique.

The binocular parallax method uses parallax images of right and left eyes with large stereoscopic effect, and both glasses and non-glasses are used, and both methods are practically used. In the non-eyeglass system, an optical plate such as a parallax barrier for separating the optical axis of left and right parallax images is installed in front of or behind the display screen. In the spectacle method, left and right parallax images having different polarization directions are displayed on a display panel, and stereoscopic images are implemented using polarized glasses or liquid crystal shutter glasses.

In the liquid crystal shutter glasses system, a left-eye image and a right-eye image are alternately displayed on a display unit in frame units, and a left-eye and right-eye shutter of the liquid crystal shutter glasses is opened and closed in synchronization with the display timing. The liquid crystal shutter glasses open the left eye shutter only during the odd frame period in which the left eye image is displayed and only the right eye shutter is opened during the excellent frame period in which the right eye image is displayed to produce binocular parallax in a time division manner. In such a liquid crystal shutter glasses system, the data on time of the liquid crystal shutter glasses is short, and the brightness of the 3D image is low, and the 3D crosstalk is very likely to occur depending on the synchronization of the display element and the liquid crystal shutter glasses and on / off switching response characteristics.

The polarizing glasses system includes a patterned retarder attached on a display panel. The polarizing glasses system alternately displays a left-eye image and a right-eye image on a display panel alternately in a horizontal line unit, and switches the polarization characteristics of light incident on the polarizing glasses through the pattern-driven retarder. As a result, the polarizing glasses system can realize a 3D image by spatially dividing the left eye image and the right eye image.

In this polarizing glasses system, since the left eye image and the right eye image are displayed adjacent to each other in a line unit, the vertical viewing angle at which no crosstalk occurs is narrow. Crosstalk occurs when the left eye and right eye images are superimposed on the monocular (left eye or right eye) of polarized glasses. Japanese Laid-Open Patent Publication No. 2002-185983 proposes a method of forming a black stripe on a pattern reliader in order to widen a vertical angle of view in which crosstalk does not occur. However, the black stripe used for improving the viewing angle causes a side effect which greatly reduces the luminance of the 2D image.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a polarizing glasses type image display device capable of widening the upper and lower viewing angles of a 3D image without lowering the brightness of the 2D image.

According to an aspect of the present invention, there is provided an image display apparatus including a display panel including a plurality of pixels to selectively display a 2D image and a 3D image; A pattern driver configured to split the light from the display panel into first and second polarized lights; And generates a first discharge control voltage at an off level and generates a second discharge control voltage at a slit-on level higher than the off level and lower than a full-on level, And a control voltage generator for selectively outputting the two discharge control voltages; A first pixel of the pixels includes a first upper main display having a first pixel electrode connected to a data line via a first switch; And a second pixel electrode connected to the data line through a second switch driven at the same timing as the first switch, and the second pixel electrode is connected to the common line A first upper auxiliary display portion having a first discharge control switch connected to the first auxiliary auxiliary display portion; And a third pixel electrode connected to the data line through a third switch.

A second upper main display portion having a fourth pixel electrode connected to the data line through a fourth switch, the second pixel being disposed below the first pixel, the pixel vertically adjacent to the first pixel among the pixels; A fifth pixel electrode connected to the data line through a fifth switch driven at the same timing as the fourth switch, and a fifth pixel electrode connected to the common line in accordance with the second discharge control voltage, A second upper auxiliary display unit having a two-discharge control switch; And a sixth pixel electrode connected to the data line through a sixth switch.

Wherein the first switch and the second switch are connected to a first gate line and are simultaneously turned on and off by a first scan pulse applied to the first gate line; The third switch is connected to a second gate line disposed below the first gate line and is turned on and off by a second scan pulse applied to the second gate line; The fourth switch and the fifth switch are connected to a third gate line disposed under the second gate line and are simultaneously turned on and off by a third scan pulse applied to the third gate line; The sixth switch is connected to a fourth gate line disposed below the third gate line and is turned on and off by a fourth scan pulse applied to the fourth gate line.

Each frame is time-divided into a first sub-frame period and a second sub-frame period subsequent to the first sub-frame period; The first gate line and the third gate line are sequentially driven within the first sub frame period; The second gate line and the fourth gate line are sequentially driven within the second sub frame period.

In the 2D mode for realizing the 2D image, the levels of data voltages supplied to the data lines in synchronization with the first to fourth scan pulses are different from each other; Wherein the first upper main display unit and the first upper auxiliary display unit display a 2D image of a first level; Wherein the first lower display unit displays a 2D image of a second level; The second upper main display unit and the second upper auxiliary display unit display a 2D image of a third level; And the second lower display unit displays the 2D image of the fourth level.

In the 3D mode for realizing the 3D image, the first upper main display unit displays a first left eye image; Wherein the first lower display unit and the second upper main display unit display the same right eye image; The second lower display unit displays a second left eye image; The first upper auxiliary display unit and the second upper auxiliary display unit display black images.

Wherein the first and second discharge control switches are turned off by the first discharge control voltage in a 2D mode for realizing the 2D image and are turned off by the second discharge control voltage in a 3D mode for implementing the 3D image, - Turns on.

Wherein the display panel further comprises a discharge control line to which the first discharge control voltage and the second discharge control voltage are selectively applied; The first discharge control switch has a gate electrode connected to the discharge control line, a source electrode connected to the second pixel electrode, and a drain electrode connected to the common line; The second discharge control switch has a gate electrode connected to the discharge control line, a source electrode connected to the fifth pixel electrode, and a drain electrode connected to the common line.

Wherein the first discharge control switch interrupts the current path between the second pixel electrode and the common line in the 2D mode and permits the current path between the second pixel electrode and the common line in the 3D mode, Discharging a voltage charged in the pixel electrode to the common voltage level; The second discharge control switch disconnects the fifth pixel electrode and the common line current path in the 2D mode and permits the fifth pixel electrode and the common line current path in the 3D mode, And discharges the voltage charged in the pixel electrode to the common voltage level.

The patterned retarder including a first retarder for passing light from the display panel through the first polarized light and a second retarder for passing light from the display panel through the second polarized light; And a boundary portion between the first retarder and the second retarder is opposed to the first upper auxiliary display portion and the second upper auxiliary display portion, respectively.

The image display apparatus according to the present invention includes each of the pixels as an upper main display unit, an upper auxiliary display unit having a discharge control switch, and a lower display unit. The present invention is characterized in that in the 2D mode, the discharge control switch is turned off so that the upper auxiliary display unit functions as an image display unit displaying the same 2D image as the upper main display unit, the discharge control switch is turned on in the 3D mode, As a black stripe. Accordingly, the present invention can secure a wide viewing angle of the 3D image without lowering the luminance of the 2D image.

Furthermore, the image display apparatus according to the present invention has an advantage that the resolution of 2D and 3D images can be easily controlled by adjusting the data voltages applied to the upper main display, the upper auxiliary display, and the lower display.

Furthermore, the image display apparatus according to the present invention can appropriately select the brightness enhancement of the 3D image or the up and down viewing angle expansion by adjusting the aperture area of the upper auxiliary display unit.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 and FIG. 2 are views showing a polarizing glasses type image display apparatus according to an embodiment of the present invention. FIG.
Figure 3 shows two vertically neighboring pixels.
4 is a diagram showing an aligned state of a pixel array and a patterned retarder;
5 is a detailed circuit diagram of the control voltage generator shown in FIG. 2;
6 is a diagram showing voltage levels of first and second discharge control voltages;
7 is a view showing scan pulses supplied in an interlaced manner;
8 is a detailed view showing a connection configuration of the first and second pixels shown in FIG. 3;
9 is a waveform diagram for explaining charging and discharging operations of pixels in a 2D mode;
10 is a view showing a correlation between a potential difference between a pixel electrode and a common electrode and a transmittance.
11 is a view showing an image display state of pixels in 2D mode.
12 is a waveform diagram for explaining charging and discharging operations of pixels in a 3D mode;
13 is a view showing an image display state of pixels in 3D mode.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to FIGS. 1 to 13. FIG.

FIG. 1 and FIG. 2 show a polarizing glasses type image display apparatus according to an embodiment of the present invention.

Referring to FIGS. 1 and 2, the image display apparatus includes a display device 10, a pattern driver 20, a controller 30, a panel driver 40, and polarizing glasses 50.

The display device 10 includes a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), and an organic light emitting diode A flat panel display device such as an electroluminescence device (EL) including an organic light emitting diode (OLED), and an electrophoresis (EPD) device. Hereinafter, the display element 10 will be described mainly with reference to a liquid crystal display element.

The display element 10 includes a display panel 11, an upper polarizing film 11a, and a lower polarizing film 11b.

The display panel 11 includes two glass substrates and a liquid crystal layer formed therebetween. A plurality of data lines DL and a plurality of gate lines GL are disposed on the lower glass substrate of the display panel 11 so as to intersect with the data lines DL. The intersection structure of the signal lines DL and GL forms a pixel array including a plurality of unit pixels UNIT PIX in the display panel 11. [ The unit pixel UNIT PIX has three pixels PIX for red (R), green (G) and blue (B), respectively. As shown in FIG. 3, each vertically adjacent first pixel PIX1 and a second pixel PIX2 includes an upper display unit UDIS and a lower display unit LDIS. The upper display unit UDIS includes an upper main display unit UMP and an upper auxiliary display unit USP serving as an active black stripe. A common line to which the common voltage Vcom is supplied and a discharge control line to which the discharge control voltages LCV1 and LCV2 are supplied are further formed on the lower glass substrate of the display panel 11. [ On the upper glass substrate of the display panel 11, a black matrix and a color filter are formed.

The upper and lower polarizing films 11a and 11b are attached to the upper glass substrate and the lower glass substrate of the display panel 11 to form an alignment film for setting a pre-tilt angle of the liquid crystal. The common electrode to which the common voltage Vcom is supplied may be formed on the upper glass substrate in a vertical electric field driving method such as TN (Twisted Nematic) mode and VA (Vertical Alignment) mode. In the IPS (In Plane Switching) And may be formed on the lower glass substrate together with the pixel electrode in a horizontal electric field driving method such as a Fringe Field Switching mode. A column spacer for maintaining a cell gap of the liquid crystal cell may be formed between the glass substrates.

The display device 10 of the present invention can be implemented in any form such as a transmissive display device, a transflective display device, and a reflective display device. In the transmissive display element and the semi-transmissive display element, the backlight unit 12 is required. The backlight unit 12 may be implemented as a direct type backlight unit or an edge type backlight unit.

The patterned retarder 20 is attached on the upper polarizing film 11a of the display panel 11. [ A first retarder RT1 is formed on the odd number lines of the pattern reliader 20 and a second retarder RT2 is formed on the even lines of the pattern writer 20. [ The light absorption axes of the first retarder RT1 and the second retarder RT2 are different from each other. The first retarder RT1 delays the phase of the linearly polarized light incident through the upper polarizing film 11a by a quarter wavelength to pass the incident light through the first polarized light (e.g., the left circularly polarized light). The second retarder RT2 delays the phase of the linearly polarized light incident through the upper polarizing film 11a by 3/4 wavelength to pass the incident light through the second polarized light (e.g., right circularly polarized light).

The controller 30 controls the operation of the panel driver 40 in the 2D mode or the 3D mode according to the mode selection signal SEL. The controller 30 receives the mode selection signal SEL through a user interface such as a touch screen, an on-screen display (OSD), a keyboard, a mouse and a remote controller, And 3D mode operation can be switched. The control unit 30 receives a 2D / 3D identification code, for example, an EPG (Electronic Program Guide) of a digital broadcast standard or an ESG (Electronic Service Guide) To distinguish the 2D mode from the 3D mode.

The control unit 30 separates the RGB image data input from the video source in the 3D mode into the RGB data of the left eye image and the RGB data of the right eye image and outputs the RGB data of the left eye image and the RGB data of the right eye image to the panel driver 40 To the data driver 40A. The control unit 30 supplies the RGB data of the 2D image input from the video source under the 2D mode to the data driver 40A of the panel driving unit 40. [

The control unit 30 controls the operation timing of the panel driving unit 40 using the timing signals such as the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the data enable signal DE, and the dot clock DCLK, Lt; / RTI >

A data control signal for controlling the operation timing of the data driver 40A includes a source start pulse (SSP), a rising start signal A source sampling clock (SSC) for controlling the latch operation of the data on the basis of the falling edge of the data, a source output enable signal SOE for controlling the output of the data driver 40A, And a polarity control signal POL for controlling the polarity of the data voltage to be supplied to the liquid crystal cells of the liquid crystal cells 11,

The gate control signal for controlling the operation timing of the gate driver 40B includes a gate start pulse (GSP) indicating a start horizontal line from which a scan starts in one vertical period in which one screen is displayed, a gate driver 40B A gate shift clock signal GSC for sequentially shifting the gate start pulse GSP and a gate output enable signal Gate OUT for controlling the output of the gate driver 40B, Enable: GOE).

The control unit 30 can drive the display panel 11 in an interlace manner using the data control signal and the gate control signal as shown in FIG. The control unit 30 multiplies the timing signals (Vsync, Hsync, DE, DCLK) synchronized with the input frame frequency to generate a frame signal having a frame frequency of Nxf (where N is a positive integer of 2 or more and f is an input frame frequency) The operation of the driving unit 40 can be controlled. The input frame frequency is 60 Hz in the National Television Standards Committee (NTSC) system and 50 Hz in the PAL (Phase-Alternating Line) system.

The panel driver 40 includes a data driver 40A for driving the data lines DL of the display panel 11 and a gate driver 40B for driving the gate lines GL of the display panel 11, And a control voltage generator 40C for driving the discharge control lines of the display panel 11. [

Each of the source driver ICs of the data driver 40A includes a shift register, a latch, a digital-to-analog converter (DAC), an output buffer, and the like. The data driver 40A latches the RGB data of the 2D or 3D image according to the data control signals SSP, SSC and SOE. The data driver 40A converts the RGB data of the 2D or 3D image into the analog positive gamma compensation voltage and the negative gamma compensation voltage in response to the polarity control signal POL to reverse the polarity of the data voltage. The data driver 40A outputs the data voltage to the data lines DL so as to be synchronized with the scan pulse (or gate pulse) output from the gate driver 40B. The source drive ICs of the data driver 40A can be bonded to the lower glass substrate of the display panel 11 by a TAB (Tape Automated Bonding) process.

The gate driver 40B generates a scan pulse that swings between the gate high voltage and the gate low voltage in accordance with the gate control signals GSP, GSC, and GOE. In accordance with the gate control signals GSP, GSC and GOE, the scan pulses are supplied to the gate lines GL in an interlaced manner. The gate driver 40B includes a gate shift register array and the like. The gate shift register array of the gate driver 40B may be formed in a GIP (Gate In Panel) method in a non-display area outside the display area where the pixel array is formed in the display panel 11. [ With the GIP scheme, the gate shift registers can be formed with the pixel array in the TFT process of the pixel array.

The control voltage generating unit 40C generates the first discharge control voltage LCV1 and the second discharge control voltage LCV2 and outputs the first discharge control voltage LCV1 and the second discharge control voltage LCV2 in accordance with the mode selection signal SEL. And the voltage LCV2 is selectively supplied to the discharge control line. The first discharge control voltage LCV1 is generated at an off level (gate low voltage) and the second discharge control voltage LCV2 is higher than the off level and lower than the pull-on level (gate high voltage) And is generated higher than the common voltage Vcom. The first discharge control voltage LCV1 and the second discharge control voltage LCV2 are applied to the gate electrodes of the discharge control switches DST1 and DST2 shown in FIG. 8 to supply current to the discharge control switches DST1 and DST2 And switches the operation.

The polarizing glasses 50 include a left eye 50L having a left eye polarization filter and a right eye 50R having a right eye polarization filter. The left eye polarizing filter has the same optical absorption axis as the first retarder RT1 of the patterned retarder 20 and the right eye polarizing filter has the same optical absorption axis as the second retarder RT2 of the patterned retarder 20 I have. For example, the left eye polarizing filter of the polarizing glasses 50 may be selected as a left circular polarization filter, and the right eye polarizing filter of the polarizing glasses 50 may be selected as a right circular polarization filter. The user can view the 3D image data displayed on the display device 10 in a space division manner through the polarized glasses 50. [

FIG. 3 shows two vertically adjacent pixels PIX1 and PIX2 among the red, green and blue pixels PIX shown in FIG. 4 shows an alignment state of the pixel array and the pattern reliader 20. As shown in FIG.

Referring to FIG. 3, the first pixel PIX1 includes an upper display unit UDIS and a lower display unit LDIS, which are disposed at intersections of two gate lines GL1 and GL2 and one data line DL1 do. The opening area of the upper display portion UDIS may be designed to be substantially equal to the opening area of the lower display portion LDIS or may be designed to be smaller than the opening area of the lower display portion LDIS.

The upper display unit UDIS of the first pixel PIX1 includes an upper main display unit UMP and an upper auxiliary display unit USP disposed on both sides of the first gate line GL1 and the discharge control line CONL do. The upper main display UMP and the upper auxiliary display USP are electrically connected to the data line DL1 when a scan pulse of a gate high voltage is applied to the first gate line GL1. The upper auxiliary display portion USP is electrically connected to the common line charged with the common voltage Vcom when the second discharge control voltage LCV2 is applied to the discharge control line CONL.

The lower display portion LDIS of the first pixel PIX1 is disposed under the upper auxiliary display portion USP of the first pixel PIX1 with the second gate line GL2 therebetween. The lower display portion LDIS of the first pixel PIX1 is electrically connected to the data line DL1 when a scan pulse of a gate high voltage is applied to the second gate line GL2.

The second pixel PIX2 includes an upper display unit UDIS and a lower display unit LDIS which are disposed at intersections of two gate lines GL3 and GL4 and one data line DL1.

The upper display unit UDIS of the second pixel PIX2 includes an upper main display unit UMP and an upper auxiliary display unit USP disposed on both sides of the third gate line GL3 and the discharge control line CONL, do. The upper main display portion UMP and the upper auxiliary display portion USP are electrically connected to the data line DL1 when a scan pulse of a gate high voltage is applied to the third gate line GL3. The upper auxiliary display portion USP is electrically connected to the common line charged with the common voltage Vcom when the second discharge control voltage LCV2 is applied to the discharge control line CONL.

The lower display portion LDIS of the second pixel PIX2 is disposed under the upper auxiliary display portion USP of the second pixel PIX2 with the fourth gate line GL4 therebetween. The lower display portion LDIS of the second pixel PIX2 is electrically connected to the data line DL1 when a scan pulse of a gate high voltage is applied to the fourth gate line GL4.

In the 2D mode, the upper auxiliary display unit USP of the first pixel PIX1 displays the same 2D image as the upper main display unit UMP adjacent thereto. In the 3D mode, the upper auxiliary display unit USP of the first pixel PIX1 displays the black gradation image while the adjacent upper main display unit UMP displays the left eye or right eye image, so that the luminance of the 2D image is not reduced It serves to widen the upper and lower viewing angles of 3D images. Similarly, in the 2D mode, the upper auxiliary display unit USP of the second pixel PIX2 displays the same 2D image as the upper main display unit UMP adjacent thereto. In the 3D mode, the upper auxiliary display unit USP of the second pixel PIX2 displays black gradation images while the adjacent upper main display unit UMP displays the left eye or right eye image, so that the brightness of the 2D image is not lowered It serves to widen the upper and lower viewing angles of 3D images.

The upper display unit UDIS and the lower display unit LDIS of the first pixel PIX1 and the upper display unit UDIS and the lower display unit LDIS of the second pixel PIX2 can display different 2D images have. The lower display portion LDIS of the first pixel PIX1 and the upper main display portion UMP of the second pixel PIX2 disposed between the upper auxiliary display portions USP for displaying the black gradation image in the 3D mode have the same gradation Right eye (or left eye) image can be displayed. At this time, a left eye (or right eye) image may be displayed on the upper main display unit UMP of the first pixel PIX1 and a right eye (or left eye) image may be displayed on the lower display unit LDIS of the second pixel PIX2 have. In the 3D mode, the display image has a form in which the left eye image and the right eye image alternate with each other over the upper auxiliary display portion USP of each pixel that is in black gradation.

Assuming that an odd pixel line is formed by a plurality of first pixels PIX1 neighboring in the horizontal direction and an even pixel line is formed by a plurality of second pixels PIX2 neighboring in the horizontal direction, 4, the delitters 20 are arranged in such a manner that the boundary portion between the first retarder RT1 and the second retarder RT2 is arranged on the upper auxiliary display units USP And is aligned with the pixel array such that it is opposed to the upper auxiliary displays USP of the second pixels PIX2 disposed in the even pixel line.

FIG. 5 shows a detailed configuration of the control voltage generator 40C shown in FIG. 6 shows the voltage levels of the first and second discharge control voltages. 7 shows scan pulses supplied in an interlaced manner.

Referring to FIG. 5, the control voltage generator 40C includes a DC-DC generator 402 and a multiplexer 404.

The DC-DC generator 402 generates a first discharge control voltage LCV1 and a second discharge control voltage LCV2 using an input DC power source.

The first discharge control voltage LCV1 may be generated at the same off level OL as the gate low voltage VGL of the scan pulse SP capable of turning off the switch of the display panel as shown in Fig. When the gate-low voltage VGL of the scan pulse SP is selected to be -5V, the first discharge control voltage LCV1 may be generated at -5V.

The second discharge control voltage LCV2 is lower than the gate high voltage VGH of the scan pulse SP which is higher than the common voltage Vcom and allows the switch of the display panel to be full- It is caused by a slight on level (SOL). The second discharge control voltage LCV2 is set to a gate high level so that the ON state of the discharge control switches DST1 and DST2 shown in FIG. 8 can be maintained at a higher level than the off level and a lower level May be selected as an appropriate value between the voltage VGH and the common voltage Vcom. When the gate high voltage VGH of the scan pulse SP, which allows the common voltage Vcom to be selected to 7.5V and the switch to be fully on, is selected as 28V, the second discharge control voltage LCV2 is 8V-12V. ≪ / RTI >

The multiplexer 404 selectively outputs the first discharge control voltage LCV1 and the second discharge control voltage LCV2 to the discharge control line CONL in accordance with the mode selection signal SEL. The multiplexer 404 supplies the first discharge control voltage LCV1 to the discharge control line CONL in the 2D mode and the second discharge control voltage LCV2 to the discharge control line CONL in the 3D mode.

The discharge control switches DST1 and DST2 shown in FIG. 8 are turned off according to the first discharge control voltage LCV1 and are turned on according to the second discharge control voltage LCV2. The charging voltage of the upper auxiliary display units USP connected thereto by the slit-on of the discharge control switches DST1 and DST2 starts to be discharged to the common voltage level. It takes a certain time until the upper auxiliary display units USP are completely discharged to the common voltage level. There is no problem at the upper end of the display panel in which the charging and discharging sequence is relatively fast, but at the lower end of the display panel in which the charging and discharging sequence is relatively late, the time required for complete discharging in the frame may be insufficient.

In order to secure a sufficient discharge time of the upper auxiliary display units USP, the present invention is to time-divide one frame into a first sub-frame SF1 and a second sub-frame SF2 according to the interlace method shown in Fig. 7, Sequentially driving the odd gate lines connected to the upper display units UDIS in the sub-frame SF1, successively driving the outermost gate lines connected to the lower display units LDIS in the second sub-frame SF2 . SP2, SP4, ..., SPn "denote scan pulses sequentially supplied to the odd gate lines, and" As shown in FIG. By this interlace driving method, the discharge time of the upper auxiliary display units USP can be sufficiently secured for each frame by the second sub-frame SF2. As a result, the holding time of the black gradation level is increased, and as a result, the upper auxiliary display units USP function more as a black stripe.

FIG. 8 shows the connection configuration of the first and second pixels PIX1 and PIX2 shown in FIG. 3 in detail. 9 is a waveform diagram for explaining the charging and discharging operations of the pixels PIX1 and PIX2 in the 2D mode and Fig. 10 is a waveform chart showing the relationship between the pixel electrode- common electrode potential difference V and the transmittance T And FIG. 11 shows an image display state of the pixels PIX1 and PIX2 in the 2D mode. FIG. 12 is a waveform diagram for explaining charging and discharging operations of the pixels PIX1 and PIX2 in the 3D mode, and FIG. 13 shows the video display states of the pixels PIX1 and PIX2 in the 3D mode.

Referring to FIG. 8, the first pixel PIX1 includes an upper display unit UDIS and a lower display unit LDIS disposed at intersections of the first and second gate lines GL1 and GL2 and the data line DL1 do.

The upper display unit UDIS of the first pixel PIX1 is connected to the first gate line GL1 to which the first scan pulse SP1 is applied and the first gate line GL1 to which the first and second discharge control voltages LCV1 and LCV2 are selectively applied And an upper main display unit UMP and an upper auxiliary display unit USP disposed on both sides of the discharge control line CONL.

The upper main display unit UMP of the first pixel PIX1 includes a first pixel electrode Ep1 and a first common electrode Ec1 constituting a first liquid crystal capacitor Clc1 opposing the first pixel electrode Ep1, , And a first storage capacitor (Cst1). The first pixel electrode Ep1 is connected to the first gate line GL1 and the data line DL1 through the first switch ST1. The first switch ST1 is turned on in response to the first scan pulse SP1 to apply the data voltage Vdata on the data line DL1 to the first pixel electrode Ep1. The gate electrode of the first switch ST1 is connected to the first gate line GL1, the source electrode thereof is connected to the data line DL1, and the drain electrode thereof is connected to the first pixel electrode Ep1. The first common electrode Ec1 is connected to the common line CL charged with the common voltage Vcom. The first storage capacitor Cst1 is formed by overlapping the first pixel electrode Ep1 and the common line CL with an insulating layer interposed therebetween.

The upper auxiliary display unit USP of the first pixel PIX1 includes a second pixel electrode Ep2 and a second common electrode Ec2 constituting the second liquid crystal capacitor Clc2 opposite to the second pixel electrode Ep2, , And a second storage capacitor (Cst2). The second pixel electrode Ep2 is connected to the first gate line GL1 and the data line DL1 through the second switch ST2. The second switch ST2 is turned on in response to the first scan pulse SP1 to apply the data voltage Vdata on the data line DL1 to the second pixel electrode Ep2. The gate electrode of the second switch ST2 is connected to the first gate line GL1, the source electrode thereof is connected to the data line DL1, and the drain electrode thereof is connected to the second pixel electrode Ep2. And the second common electrode Ec2 is connected to the common line CL charged with the common voltage Vcom. The second storage capacitor Cst2 is formed by overlapping the second pixel electrode Ep2 and the common line CL with the insulating layer interposed therebetween.

The second pixel electrode Ep2 is connected to the common line CL through the first discharge control switch DST1. The first discharge control switch DST1 switches the current path between the second pixel electrode Ep2 and the common line CL in response to the first discharge control voltage LCV1 and the second discharge control voltage LCV2 selectively do. The gate electrode of the first discharge control switch DST1 is connected to the discharge control line CONL, the source electrode thereof is connected to the second pixel electrode Ep2, and the drain electrode thereof is connected to the common line CL. When the first discharge control voltage LCV1 is applied, the first discharge control switch DST1 completely closes the source-drain channel of the first discharge control switch DST1 and the current path between the second pixel electrode Ep2 and the common line CL . When the second discharge control voltage LCV2 is applied, the first discharge control switch DST1 partly opens its source-drain channel to pass a current path between the second pixel electrode Ep2 and the common line CL In part.

The lower display unit LDIS of the first pixel PIX1 includes a third pixel electrode Ep3, a third common electrode Ec3 constituting a third liquid crystal capacitor Clc3 opposite to the third pixel electrode Ep3, And a third storage capacitor Cst3. The third pixel electrode Ep3 is connected to the second gate line GL2 and the data line DL1 through the third switch ST3. The third switch ST3 is turned on in response to the second scan pulse SP2 to apply the data voltage Vdata on the data line DL1 to the third pixel electrode Ep3. The gate electrode of the third switch ST3 is connected to the second gate line GL2, the source electrode thereof is connected to the data line DL1, and the drain electrode thereof is connected to the third pixel electrode Ep3. And the third common electrode Ec3 is connected to the common line CL charged with the common voltage Vcom. The third storage capacitor Cst3 is formed by overlapping the third pixel electrode Ep3 and the common line CL with the insulating layer therebetween.

The second pixel PIX2 includes an upper display unit UDIS and a lower display unit LDIS which are disposed at intersections of the third and fourth gate lines GL3 and GL4 and the data line DL1.

The upper display unit UDIS of the second pixel PIX2 is connected to the third gate line GL3 to which the third scan pulse SP3 is applied and the third gate line GL2 to which the first and second discharge control voltages LCV1 and LCV2 are selectively applied And an upper main display unit UMP and an upper auxiliary display unit USP disposed on both sides of the discharge control line CONL.

The upper main display unit UMP of the second pixel PIX2 includes a fourth pixel electrode Ep4 and a fourth common electrode Ec4 constituting a fourth liquid crystal capacitor Clc4 opposite to the fourth pixel electrode Ep4, , And a fourth storage capacitor (Cst4). The fourth pixel electrode Ep4 is connected to the third gate line GL3 and the data line DL1 through the fourth switch ST4. The fourth switch ST4 is turned on in response to the third scan pulse SP3 to apply the data voltage Vdata on the data line DL1 to the fourth pixel electrode Ep4. The gate electrode of the fourth switch ST4 is connected to the third gate line GL3, the source electrode thereof is connected to the data line DL1, and the drain electrode thereof is connected to the fourth pixel electrode Ep4. And the fourth common electrode Ec4 is connected to the common line CL charged with the common voltage Vcom. The fourth storage capacitor Cst4 is formed by overlapping the fourth pixel electrode Ep4 and the common line CL with an insulating layer therebetween.

The upper auxiliary display unit USP of the second pixel PIX2 includes a fifth pixel electrode Ep5 and a fifth common electrode Ec5 constituting the fifth liquid crystal capacitor Clc5 opposite to the fifth pixel electrode Ep5, , And a fifth storage capacitor (Cst5). The fifth pixel electrode Ep5 is connected to the third gate line GL3 and the data line DL1 through the fifth switch ST5. The fifth switch ST5 is turned on in response to the third scan pulse SP3 to apply the data voltage Vdata on the data line DL1 to the fifth pixel electrode Ep5. The gate electrode of the fifth switch ST5 is connected to the third gate line GL3, the source electrode thereof is connected to the data line DL1, and the drain electrode thereof is connected to the fifth pixel electrode Ep5. The fifth common electrode Ec5 is connected to the common line CL charged with the common voltage Vcom. The second storage capacitor Cst2 is formed by overlapping the fifth pixel electrode Ep5 and the common line CL with the insulating layer therebetween.

The fifth pixel electrode Ep5 is connected to the common line CL through the second discharge control switch DST2. The second discharge control switch DST2 selectively switches the current path between the fifth pixel electrode Ep5 and the common line CL in response to the first discharge control voltage LCV1 and the second discharge control voltage LCV2, do. The gate electrode of the second discharge control switch DST2 is connected to the discharge control line CONL, the source electrode thereof is connected to the fifth pixel electrode Ep5, and the drain electrode thereof is connected to the common line CL. When the first discharge control voltage LCV1 is applied, the second discharge control switch DST2 completely closes the source-drain channel of the second discharge control switch DST2 so that the current path between the fifth pixel electrode Ep5 and the common line CL . When the second discharge control voltage LCV2 is applied, the second discharge control switch DST2 partly opens its source-drain channel to pass a current path between the fifth pixel electrode Ep5 and the common line CL In part.

The lower display unit LDIS of the second pixel PIX2 includes a sixth pixel electrode Ep6 and a sixth common electrode Ec6 constituting a sixth liquid crystal capacitor Clc6 opposite to the sixth pixel electrode Ep6, And a sixth storage capacitor Cst6. The sixth pixel electrode Ep6 is connected to the fourth gate line GL4 and the data line DL1 through the sixth switch ST6. The sixth switch ST6 is turned on in response to the fourth scan pulse SP4 to apply the data voltage Vdata on the data line DL1 to the sixth pixel electrode Ep6. The gate electrode of the sixth switch ST6 is connected to the fourth gate line GL4, the source electrode thereof is connected to the data line DL1, and the drain electrode thereof is connected to the sixth pixel electrode Ep6. The sixth common electrode Ec6 is connected to the common line CL charged with the common voltage Vcom. The sixth storage capacitor Cst6 is formed by overlapping the sixth pixel electrode Ep6 and the common line CL with the insulating layer interposed therebetween.

The discharge control switches DST1 and DST2 are designed to have the same channel capacity as the first to sixth switches ST1 to ST6. Therefore, the ON state of the discharge control switches DST1 and DST2 is lower than the full on level as the second discharge control voltage LCV2 is applied at a lower level than the gate high voltage VGH. A light-on level (SOL). Even if the second switch ST2 and the first discharge control switch DST1 are turned on at the same time, the amount of current discharged through the first discharge control switch DST1 is smaller than the amount of current charged through the second switch ST2. Even if the fifth switch ST5 and the second discharge control switch DST2 are turned on at the same time, the amount of current discharged through the second discharge control switch DST2 is smaller than the amount of current charged through the fifth switch ST5 little.

9 to 11, operations and effects of the pixels PIX1 and PIX2 having such a connection configuration in the 2D mode will be described.

Referring to FIG. 9, in the 2D mode, the discharge control switches DST1 and DST2 maintain the OFF state in response to the first discharge control voltage LCV1 of the off level (-5 V).

The first scan pulse SP1 and the third scan pulse SP3 are sequentially input to the gate high voltage VGH level in the first sub-frame SF1.

In response to the first scan pulse SP1, the first and second switches ST1 and ST2 are simultaneously turned on to the pull-on level. The data voltage D1 for implementing the 2D image is charged to the first pixel voltage Vp1 in the upper main display unit UMP of the first pixel PIX1 by turning on the first switch ST1, The data voltage D1 for realizing the 2D image is similarly charged to the second pixel voltage Vp2 in the upper auxiliary display unit USP of the first pixel PIX1 by turning on the switch ST2. Since the first and second switches ST1 and ST2 are designed in the same manner, the second pixel voltage Vp2 is substantially equal to the first pixel voltage Vp1.

In response to the third scan pulse SP3, the fourth and fifth switches ST4 and ST5 are simultaneously turned on at the pull-on level. The data voltage D3 for realizing the 2D image is charged to the fourth pixel voltage Vp4 in the upper main display unit UMP of the second pixel PIX2 by turning on the fourth switch ST4, The data voltage D3 for realizing the 2D image is similarly charged to the fifth pixel voltage Vp5 in the upper auxiliary display unit USP of the second pixel PIX2 by turning on the switch ST5. Since the fourth and fifth switches ST4 and ST5 are designed in the same manner, the fifth pixel voltage Vp5 is substantially equal to the fourth pixel voltage Vp4.

The second scan pulse SP2 and the fourth scan pulse SP4 are sequentially input to the gate high voltage VGH level in the second sub-frame SF2.

The third and sixth switches ST3 and ST6 are turned on at the pull-on level in response to the second and fourth scan pulses SP2 and SP4, respectively. The data voltage D2 for realizing the 2D image is charged to the third pixel voltage Vp3 in the lower display unit LDIS of the first pixel PIX1 by turning on the third switch ST3, The data voltage D4 for realizing the 2D image is charged to the sixth pixel voltage Vp6 in the lower display portion LDIS of the second pixel PIX2 by the turn-on of the sixth pixel voltage Vp6.

The voltage difference (V) between the pixel voltage and the common voltage and the transmittance (T) are proportional to each other as shown in Fig. The upper display unit UDIS of the first pixel PIX1, the lower display unit LDIS of the first pixel PIX1 when the data voltages D1, D2, D3 and D4 are inputted at different levels as shown in FIG. The upper display unit UDIS of the second pixel PIX2 and the lower display unit LDIS of the second pixel PIX2 can display 2D images of different gradations as shown in FIG. This has the effect of doubling the physical vertical resolution of the display panel in the 2D mode.

The upper auxiliary display unit USP of the first pixel PIX1 displays the same 2D image as that of the upper main display unit UMP of the first pixel PIX1 and is displayed on the upper display unit UDIS of the first pixel PIX1 The brightness of the 2D image is increased. The upper auxiliary display unit USP of the second pixel PIX2 displays the same 2D image as that of the upper main display unit UMP of the second pixel PIX2 so as to display the 2D image displayed on the upper display unit UDIS of the second pixel PIX2, Thereby enhancing the brightness of the image.

Fig. 10, Fig. 12 and Fig. 13 are combined to explain the operation effect of the pixels PIX1 and PIX2 having such a connection configuration in the 3D mode together with their operation effects.

In the 3D mode, the discharge control switches DST1 and DST2 continue to be in the SLIGHT ON state in response to the second discharge control voltage LCV2 of the SLLITE ON level (8-12V).

The first scan pulse SP1 and the third scan pulse SP3 are sequentially input to the gate high voltage VGH level in the first sub-frame SF1.

In response to the first scan pulse SP1 of the gate high voltage VGH, the first and second switches ST1 and ST2 are simultaneously turned on to the pull-on level. The data voltage L1 for realizing the 3D image is charged to the first pixel voltage Vp1 in the upper main display unit UMP of the first pixel PIX1 by turning on the first switch ST1, The data voltage L1 for realizing the 3D image is similarly charged to the second pixel voltage Vp2 in the upper auxiliary display unit USP of the first pixel PIX1 by turning on the switch ST2.

In the period in which the first scan pulse SP1 is input to the gate high voltage VGH, the pull-on state is compared with the channel resistance of the second switch ST2 by the first discharge control switch DST1 having the slit- The channel resistance is much larger. Therefore, in a period in which the first scan pulse SP1 is input to the gate high voltage VGH, the discharge current flowing out from the second pixel electrode Ep2 is much higher than the charge current flowing into the second pixel electrode Ep2 And as a result, the second pixel voltage Vp2 is charged to a level similar to the first pixel voltage Vp1.

When the first scan pulse SP1 is inverted to the gate low voltage VGL, the first and second switches ST1 and ST2 are simultaneously turned off. At this time, the channel resistance of the first discharge control switch DST1 having the slit-on state is much smaller than the channel resistance of the second switch ST2 having the off state. Accordingly, the second pixel voltage Vp2 charged in the upper auxiliary display unit USP of the first pixel PIX1 is supplied to the first pixel PIX1 for a predetermined period (for example, 20 horizontal periods 20H) via the first discharge control switch DST1, And is discharged to the common voltage Vcom level.

In response to the third scan pulse SP3 of the gate high voltage VGH, the fourth and fifth switches ST4 and ST5 are simultaneously turned on at the pull-on level. The data voltage R1 for implementing the 3D image is charged to the fourth pixel voltage Vp4 in the upper main display unit UMP of the second pixel PIX2 by turning on the fourth switch ST4, The data voltage R1 for realizing the 3D image is similarly charged to the fifth pixel voltage Vp5 in the upper auxiliary display unit USP of the second pixel PIX2 by turning on the switch ST5.

In the period in which the third scan pulse SP3 is input to the gate high voltage VGH, the pull-on state is compared with the channel resistance of the fifth switch ST5 by the second discharge control switch DST2 having the slit- The channel resistance is much larger. Therefore, in the period in which the third scan pulse SP3 is input to the gate high voltage VGH, the discharge current flowing out from the fifth pixel electrode Ep5 is much higher than the charge current flowing into the fifth pixel electrode Ep5 And as a result, the fifth pixel voltage Vp5 is charged to a level similar to the fourth pixel voltage Vp4.

When the third scan pulse SP3 is inverted to the gate-low voltage VGL, the fourth and fifth switches ST4 and ST5 are simultaneously turned off. At this time, the channel resistance of the second discharge control switch DST2 having the slit-on state is much smaller than the channel resistance of the fifth switch ST5 having the off state. Accordingly, the fifth pixel voltage Vp5 charged in the upper auxiliary display unit USP of the second pixel PIX2 is supplied to the second pixel PIX2 for a predetermined period (for example, 20 horizontal periods 20H) via the second discharge control switch DST2, And is discharged to the common voltage Vcom level.

The second scan pulse SP2 and the fourth scan pulse SP4 are sequentially input to the gate high voltage VGH level in the second sub-frame SF2.

The third and sixth switches ST3 and ST6 are turned on at the pull-on level in response to the second and fourth scan pulses SP2 and SP4, respectively. The data voltage R1 for realizing the 3D image is charged to the third pixel voltage Vp3 in the lower display unit LDIS of the first pixel PIX1 by turning on the third switch ST3, The data voltage L2 for realizing the 3D image is charged to the sixth pixel voltage Vp6 in the lower display portion LDIS of the second pixel PIX2 by the turn-on of the sixth pixel voltage Vp6.

The voltage difference (V) between the pixel voltage and the common voltage and the transmittance (T) are proportional to each other as shown in Fig. The voltage difference between the second pixel voltage Vp2 and the common voltage Vcom and the voltage difference between the fifth pixel voltage Vp5 and the common voltage Vcom become "0 ". As a result, the upper auxiliary display units USP of the first and second pixels PIX1 and PIX2 display black gradation images as shown in FIG. 13 according to the potential difference-transmittance characteristic. The upper main display units UMP and the lower display units UDIS of the first and second pixels PIX1 and PIX2 display a 3D image of a specific gray level as shown in FIG. In other words, when data voltages (L1, R1, R1, L2) are input at the same level as in FIG. 12, the upper main display unit UMP of the first pixel PIX1 outputs the left- The lower display portion LDIS of the pixel PIX1 and the upper main display portion UMP of the second pixel PIX2 display the right eye image of the second gradation and the lower display portion LDIS of the second pixel PIX2 displays the right- And the upper auxiliary display units USP of the first and second pixels PIX1 and PIX2 can display a black image.

The upper auxiliary display units USP of the first and second pixels PIX1 and PIX2 function as an active black stripe. The black image displayed on the upper auxiliary display units USP serves to widen the display interval between the vertically neighboring 3D images (i.e., the left eye image L and the right eye image R). The present invention can widely obtain a 3D vertical viewing angle in which no crosstalk occurs even without a separate black stripe pattern through the black image.

The luminance and the upper and lower viewing angles of the 3D image are in a trade-off relationship. As the opening area of the upper auxiliary display units USP is widened, the 3D up / down viewing angle becomes wider, but the luminance of the 3D image can be reduced. Accordingly, in the designing process, the size of the upper auxiliary display units USP can be appropriately selected in consideration of the luminance of the 3D image and the upper and lower viewing angles.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the present invention should not be limited to the details described in the detailed description, but should be defined by the claims.

10: display element 11: display panel
20: pattern-driven retarder 30: control unit
40: panel driver 40A: data driver
40B: gate driver 40C: control voltage generator
50: polarized glasses

Claims (12)

A display panel including a plurality of pixels to selectively display a 2D image and a 3D image; And
And a control voltage generator for selectively outputting a first discharge control voltage of the OFF level and a second discharge control voltage of the SLITE-ON level;
Wherein the first pixel of the pixels,
A first upper main display having a first pixel electrode connected to a data line through a first switch;
And a second pixel electrode connected to the data line through a second switch driven at the same timing as the first switch, and the second pixel electrode is connected to the common voltage A first upper auxiliary display unit having a first discharge control switch connected to a common line charged with the first discharge control switch; And
And a first lower display unit having a third pixel electrode connected to the data line through a third switch,
Wherein the common voltage is higher than the off level and the slitter-on level is higher than the common voltage and lower than the full-on level. The method according to claim 1,
A second pixel disposed adjacent to the first pixel and adjacent to the first pixel,
A second upper main display unit having a fourth pixel electrode connected to the data line through a fourth switch;
A fifth pixel electrode connected to the data line through a fifth switch driven at the same timing as the fourth switch, and the fifth pixel electrode is connected to the common electrode in accordance with the second discharge control voltage applied to the gate electrode. A second upper auxiliary display unit having a second discharge control switch connected to the line; And
And a second lower display unit having a sixth pixel electrode connected to the data line through a sixth switch. 3. The method of claim 2,
Wherein the first switch and the second switch are connected to a first gate line and are simultaneously turned on and off by a first scan pulse applied to the first gate line;
The third switch is connected to a second gate line disposed below the first gate line and is turned on and off by a second scan pulse applied to the second gate line;
The fourth switch and the fifth switch are connected to a third gate line disposed under the second gate line and are simultaneously turned on and off by a third scan pulse applied to the third gate line;
Wherein the sixth switch is connected to a fourth gate line disposed below the third gate line and is turned on and off by a fourth scan pulse applied to the fourth gate line. The method of claim 3,
Each frame is time-divided into a first sub-frame period and a second sub-frame period subsequent to the first sub-frame period;
The first gate line and the third gate line are sequentially driven within the first sub frame period;
And the second gate line and the fourth gate line are sequentially driven within the second sub frame period. The method of claim 3,
In implementing the 2D image, the levels of data voltages supplied to the data lines in synchronization with the first to fourth scan pulses are different from each other;
Wherein the first upper main display unit and the first upper auxiliary display unit display a 2D image of a first level;
Wherein the first lower display unit displays a 2D image of a second level;
The second upper main display unit and the second upper auxiliary display unit display a 2D image of a third level;
And the second lower display unit displays a 2D image of a fourth level. The method of claim 3,
In implementing the 3D image,
The first upper main display unit displays a first left eye image;
Wherein the first lower display unit and the second upper main display unit display the same right eye image;
The second lower display unit displays a second left eye image;
Wherein the first upper auxiliary display unit and the second upper auxiliary display unit display a black image. 3. The method of claim 2,
Wherein the first and second discharge control switches are turned off by the first discharge control voltage when the 2D image is implemented. 8. The method of claim 7,
Wherein the display panel further comprises a discharge control line to which the first discharge control voltage and the second discharge control voltage are selectively applied;
The first discharge control switch has a gate electrode connected to the discharge control line, a source electrode connected to the second pixel electrode, and a drain electrode connected to the common line;
Wherein the second discharge control switch has a gate electrode connected to the discharge control line, a source electrode connected to the fifth pixel electrode, and a drain electrode connected to the common line. 9. The method of claim 8,
Wherein the first discharge control switch comprises:
Wherein the second pixel electrode and the common line current path are disconnected in the 2D image implementation, and when the 3D image is implemented, a current path between the second pixel electrode and the common line is applied, To the common voltage;
Wherein the second discharge control switch comprises:
The second pixel electrode and the common line current path are disconnected in the 2D image implementation, and in the 3D image realization, the voltage between the fifth pixel electrode and the common line is supplied to the fifth pixel electrode, Is discharged to the common voltage. 3. The method of claim 2,
Further comprising a pattern reliader for dividing the light from the display panel into first and second polarized light beams,
The patterned retarder including a first retarder for passing light from the display panel through the first polarized light and a second retarder for passing light from the display panel through the second polarized light;
And a boundary portion between the first retarder and the second retarder is opposed to the first upper auxiliary display portion and the second upper auxiliary display portion, respectively. The method according to claim 1,
In the 3D image realization, the on-channel resistance of the first discharge control switch which is turned on by the second discharge control voltage is higher than the on-channel resistance of the second switch Channel resistance of the second switch which is greater than the on-channel resistance of the first switch and is off by the first scan pulse of the off-level. 3. The method of claim 2,
In the 3D image realization, the on-channel resistance of the second discharge control switch, which is turned on by the second discharge control voltage, is turned on by the third scan pulse of the pull- Channel resistance of the fifth switch turned off by the third scan pulse of the off level.

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