KR102277094B1 - Buffer cache management method and a computing device to which the buffer cache management method are applied - Google Patents

Abstract

Disclosed are a buffer cache management method and a computing device to which the buffer cache management method is applied. The buffer cache management method includes: identifying a reference pattern for an environment setting file block and a texture input file block required in an image generation process through rendering and a result file block generated as a result of the rendering; A buffer cache based on the identified reference pattern as having a texture area for storing a texture input file block identified as having a repeating reference pattern of a first period, and having a repeating reference pattern of a second period longer than the first period dividing the identified environment setting file block into environment setting areas for storing; storing a file block of the same type as that of the received file block among the texture area and the environment setting area when the file block to be stored in the buffer cache is received; and adjusting a cache size of the texture area or the environment setting area based on a cache hit ratio of the file blocks stored in the buffer cache.

Description

BUFFER CACHE MANAGEMENT METHOD AND A COMPUTING DEVICE TO WHICH THE BUFFER CACHE MANAGEMENT METHOD ARE APPLIED

The present invention relates to a buffer cache management method and a computing device to which the buffer cache management method is applied, and more particularly, to a method and apparatus for more effectively managing a buffer cache in a rendering system.

Rendering is the process of creating high-quality images of 24 frames per second or more through software work based on basic input file blocks such as shape, contrast, and texture, and is widely used in 3D animation and special effects. In rendering, it is common to use a dedicated cluster machine instead of a PC because it requires a large amount of computation that takes up to two days or more to generate one frame.

Although this rendering operation is computationally intensive, the time required for the rendering system can be shortened due to the recent maximization of parallel operations through many-core systems. However, there is a problem in that another bottleneck occurs due to storage access that is hundreds of thousands of times slower than the CPU or GPU during the rendering operation.

The present invention relates to a buffer cache management method for a rendering system, which can improve the performance of the buffer cache by dividing and managing the space of the buffer cache in consideration of the reference characteristics of file blocks required in an image generation process through rendering. Methods and apparatus are provided.

A buffer cache management method according to an embodiment of the present invention includes the steps of identifying a reference pattern for an environment setting file block and a texture input file block required in an image generation process through rendering and a result file block generated as a result of the rendering ; A buffer cache based on the identified reference pattern as having a texture area for storing a texture input file block identified as having a repeating reference pattern of a first period, and having a repeating reference pattern of a second period longer than the first period dividing the identified environment setting file block into environment setting areas for storing; storing a file block of the same type as that of the received file block among the texture area and the environment setting area when the file block to be stored in the buffer cache is received; and adjusting a cache size of the texture area or the environment setting area based on a cache hit ratio of the file blocks stored in the buffer cache.

In the identifying, the reference pattern may be identified using reference frequencies of the environment setting file block and the texture input file block referenced by the rendering software performing the rendering in the process of generating the image.

In the dividing, cache sizes of the divided texture area and the environment setting area may be determined based on the workload of each of the environment setting file block and the texture input file block.

In the storing step, when it is necessary to replace the file blocks stored in the texture area and the environment setting area, the most recently used (MRU) algorithm is used to release the most recently referenced file block, and to store the newly received file block. can

The buffer cache further includes an arbitrary reference area other than the texture area and the environment setting area, and the storing is performed in the arbitrary reference area when the file block emitted from the texture area and the environment setting area has an arbitrary reference pattern. can be saved

In the storing, when it is necessary to replace the file blocks stored in the random reference area, the least recently used (LRU) algorithm may be used to release the longest unreferenced file block and store the newly received file block.

The texture area includes a first real area in which the texture input file block is stored and a first virtual area for checking a performance contribution according to a cache hit ratio, and the environment setting area is a second area in which the environment setting file block is stored. A second virtual region may be included to check the performance contribution according to the real region and the cache hit ratio.

a sum of cache sizes for a first real region of the texture region and a second real region of the environment setting region is equal to a sum of cache sizes for a first real region and a first virtual region of the texture region; A buffer cache size rule equal to the sum of cache sizes for the second real area and the second virtual area of the setting area may be applied.

In the storing, when the file blocks stored in the first real area of the texture area and the second real area of the environment setting area need to be replaced, the metadata of the file block to be emitted is stored in the first virtual area and the second virtual area. can be stored in each.

The adjusting may include reducing the cache size of the first virtual region and reducing the cache size of the first real region when a texture input file block required in the image generation process through the rendering is found in the first virtual region of the texture region. Increase the cache size of , but decrease the cache size of the second real region to maintain the buffer cache size rule, and increase the cache size of the second virtual region.

A computing device to which the buffer cache management method according to an embodiment of the present invention is applied includes a processor, wherein the processor includes an environment setting file block and a texture input file block required in an image generation process through rendering, and a result of the rendering a texture area for identifying a reference pattern for the generated result file block, and storing a texture input file block identified as having a repeating reference pattern of a first period in a buffer cache based on the identified reference pattern; It is divided into an environment setting area for storing the environment setting file block identified as having a repeating reference pattern of a second period longer than the period, and when a file block to be stored in the buffer cache is received, the texture area and the environment setting A file block of the same type as the received file block may be stored in an area, and the cache size of the texture area or the environment setting area may be adjusted based on a cache hit ratio of the file blocks stored in the buffer cache.

The processor may identify the reference pattern by using the reference frequency of the environment setting file block and the texture input file block referenced by the rendering software performing the rendering in the process of generating the image.

The processor may determine cache sizes of the divided texture area and the environment setting area based on the workload of each of the environment setting file block and the texture input file block.

When it is necessary to replace the file blocks stored in the texture area and the environment setting area, the processor may use a Most Recently Used (MRU) algorithm to release the most recently referenced file block and store the newly received file block. .

The buffer cache may further include an arbitrary reference area other than the texture area and the environment setting area, and the processor may store the file block emitted from the texture area and the environment setting area in the arbitrary reference area when the file block has an arbitrary reference pattern. have.

When it is necessary to replace the file blocks stored in the random reference area, the processor may use a least recently used (LRU) algorithm to release a file block that has not been referenced for the longest time and store the newly received file block.

The texture area includes a first real area in which the texture input file block is stored and a first virtual area for checking a performance contribution according to a cache hit ratio, and the environment setting area is a second area in which the environment setting file block is stored. A second virtual region may be included to check the performance contribution according to the real region and the cache hit ratio.

a sum of cache sizes for a first real region of the texture region and a second real region of the environment setting region is equal to a sum of cache sizes for a first real region and a first virtual region of the texture region; A buffer cache size rule equal to the sum of cache sizes for the second real area and the second virtual area of the setting area may be applied.

When it is necessary to replace the file blocks stored in the first real area of the texture area and the second real area of the environment setting area, the processor writes metadata of the file blocks to be emitted to the first virtual area and the second virtual area, respectively. can be saved

The processor decreases the cache size of the first virtual region when a texture input file block required in the image generation process through the rendering is found in the first virtual region of the texture region, and the cache size of the first real region may be increased, but the cache size of the second real region may be decreased to maintain the buffer cache size rule, and the cache size of the second virtual region may be increased.

The present invention relates to a buffer cache management method for a rendering system, and the performance of the buffer cache can be improved by dividing and managing the space of the buffer cache in consideration of the reference characteristics of file blocks required in an image generation process through rendering. .

1 is a diagram illustrating a rendering system according to an embodiment of the present invention.
2A and 2B are diagrams illustrating buffer cache performance of a general-purpose system and a rendering system according to an embodiment of the present invention.
3 is a diagram illustrating a reference pattern of file blocks required for rendering according to an embodiment of the present invention.
4 is a diagram illustrating a spatial structure of a buffer cache according to an embodiment of the present invention.
5 is a diagram illustrating a file block replacement method of a buffer cache according to an embodiment of the present invention.
6 is a diagram illustrating a method for dynamically allocating a buffer cache according to an embodiment of the present invention.
7 is a flowchart illustrating a buffer cache management method according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a diagram illustrating a rendering system according to an embodiment of the present invention.

Referring to FIG. 1 , the processor 110 of the computing device 100 of the present invention may generate a high-quality image based on data such as shape, contrast, and texture through a software operation. In this case, data necessary to generate a high-definition image may be stored in the storage 120 in the computing device 100 , and the processor 110 accesses the data stored in the storage 120 during a rendering operation to access the high-quality image through software image can be created. For example, the storage 120 may be a non-volatile memory (NVRAM).

In this case, the processor 110 may generate a high-quality image through a software operation after reading data necessary for the rendering operation from the storage 120 . In the process of generating a high-quality image as described above, the processor 110 may repeatedly request the same data from the storage 120. The storage 120 has a long access time to the data, so the more data repeatedly requested, the longer the rendering time. can increase

The computing device 100 of the present invention reads data necessary for a rendering operation from the storage 120 in order to shorten the rendering time, and then forms a buffer cache 130 or a separate buffer cache ( 130), the rendering time can be shortened by enabling quick access when the same data is requested again.

Accordingly, the computing device 100 of the present invention proposes an efficient buffer cache 130 management method for improving the storage 120 performance of the rendering system.

2A and 2B are diagrams illustrating buffer cache performance of a general-purpose system and a rendering system according to an embodiment of the present invention.

2A and 2B show performance according to cache size when general-purpose workloads and rendering workloads are executed in a general buffer cache system using the least recently used (LRU) algorithm, respectively. Referring to FIG. 2A , the performance of the buffer cache in a general computing system is gradually improved as the cache size increases in the case of general-purpose workloads. However, in the case of the rendering workload as shown in FIG. 2B , even if the cache size is increased, the performance is hardly improved, but it shows that the performance improvement appears only after the cache size is increased enough to contain all the data. This indicates that it is not appropriate to use the general-purpose computer method when managing the buffer cache of the rendering system.

Accordingly, the present invention can provide a buffer cache management method suitable for a rendering workload so that performance improvement in proportion to the increase in the cache size can be obtained.

3 is a diagram illustrating a reference pattern of file blocks required for rendering according to an embodiment of the present invention.

In order to design a buffer cache for a rendering system, the computing device 100 of the present invention may first extract and analyze reference traces of file blocks required in an image generation process through rendering. In this case, the file block may mean a set of various data required in an image generation process through rendering. 3 shows file blocks referenced over time in the extracted reference trace for each file block type.

The x-axis of FIG. 3 is a logical time that increases by 1 whenever a file block is referenced, and the y-axis may indicate a block number. At this time, if the referenced file block is analyzed by file block type, the configuration file block read 310 may appear when the program is executed. After that, the texture input file block read 320 may appear every frame, and a result file block generated as a result of rendering using the texture input file block may be generated. The last generated result file block write 320 may occur whenever rendering of every frame is finished. These read and write characteristics for each file block type can appear in common no matter what rendering operation is executed.

In more detail, the configuration file block read 310 may have the form of a repeating reference pattern with a long cycle since it appears once for every program execution. In addition, the texture input file block read 320 occupies most of the repeating reference pattern having a short period, and may have a form in which some arbitrary reference patterns are mixed. Finally, the result file block write 330 may take the form of a one-time sequential reference.

Since the reference pattern for each file block type can be identified through the file block format, the computing device 100 of the present invention can provide a buffer cache management method specialized for rendering based on the reference pattern for each file block type.

On the other hand, when various reference patterns are mixed, it is effective to divide the space of the buffer cache 130 and operate a management technique suitable therefor. Accordingly, the computing device 100 of the present invention improves the performance of the buffer cache 130 by allocating the space of the buffer cache 130 based on the performance improvement effect for each reference pattern that appears during rendering, and applying an appropriate management technique. can provide a way to do it.

First, the computing device 100 does not cache a file block referenced once because there is no performance improvement effect, and caches a file block having a repeating reference pattern with a long period and a file block having a repeating reference pattern with a short period. Space allocation may be performed based on the gain through When the reference pattern of the file block is detected in real time, since the overhead is large, the computing device 100 of the present invention allocates space in the buffer cache 130 and management can be performed.

4 is a diagram illustrating a spatial structure of a buffer cache according to an embodiment of the present invention.

4 shows the spatial structure of the buffer cache 130 proposed by the present invention. The buffer cache 130 includes a configuration area (area C) in which a configuration file block having a repeating reference pattern with a long period is stored and a texture area (area C) in which a texture file block having a shape of a repeating reference pattern having a short period is stored. T region), and a separate arbitrary reference region (O region). The computing device 100 does not allocate space because the result file block generated as a result of rendering is not reused, and may adjust the cache size for the allocated area according to the performance contribution.

The computing device 100 may set virtual regions G1 and G2 in each region in order to determine the performance contribution to the environment setting region (region C) and the texture region (region T). In this case, the virtual regions G1 and G2 may refer to regions in which information indicating that the file blocks have been recently released can be maintained for a certain period of time with respect to the file blocks released from the real regions T1 and C1 in which the actual file blocks are stored due to space constraints. , space overhead can be very small because only meta information of the emitted file block is maintained.

The computing device 100 may determine how much performance improvement can be expected when the cache sizes of the real regions T1 and C1 are adjusted using the virtual regions G1 and G2. For example, when frequent references occur in the virtual region G2 of the environment setting region (region C), the computing device 100 increases the cache size for the real region C1 of the environment setting region (region C) to increase the cache hit ratio By improving , the performance of the buffer cache 130 may be improved.

In the present invention, a buffer cache size rule for space allocation of the buffer cache 130 may be applied to optimize the performance of the buffer cache 130 . Specifically, in the buffer cache size rule, the sum of the cache sizes for the actual area (T1) of the texture area (T area) and the actual area (C1) of the environment setting area (C area) is the actual area (T1) of the texture area (T area). T1) and the sum of the cache sizes for the virtual region G1, and may be the same as the sum of the cache sizes for the real region C1 and the virtual region G2 of the environment setting region (C). It may be the same as Equation 1 to Equation 3 below, which is expressed by the formula

<Equation 1>

Cache size of T1 + Cache size of C1 = S

<Equation 2>

Cache size of T1 + Cache size of G1 = S

<Equation 3>

Cache size in C1 + Cache size in G2 = S

When new file blocks enter each area of the buffer cache 130 , the computing device 100 checks the file block format of the corresponding file block, and places the new file block in a certain area based on the checked file block format. You can decide to save. If the new file block is the result file block, the computing device 100 does not store it in the buffer cache 130 , and when the new file block is a texture input file block or a configuration file block, the file block extension Based on it, it can be stored in the texture area (T area) or the environment setting area (C area).

5 is a diagram illustrating a file block replacement method of a buffer cache according to an embodiment of the present invention.

Since the buffer cache 130 has a limited capacity, appropriate file block replacement is required for a high cache hit ratio. Since the file block reference in the texture area (region T) or the environment setting area (region C) is in the form of a repeating reference pattern, when it is necessary to replace the file block in the corresponding areas, the computing device 100 performs the most recently used (MRU) An algorithm can be used to release the most recently referenced block of files.

At this time, if the released file block is a file block having a form of an arbitrary reference pattern rather than a form of a repeating reference pattern, since such early release may cause performance degradation, the computing device 100 processes the released file block Instead of directly deleting from the real area (T1) of the texture area (area T) or the actual area (C1) of the environment setting area (area C), the emitted file block is entered into an arbitrary reference area (area O), and each iteration The meta information can be recorded in the virtual regions G1 and G2 of the reference region.

Contrary to this, when replacement of a file block is required in an arbitrary reference area (area O), the computing device 100 may determine a file block from which to emit a file block that has not been referenced for the longest time by using a least recently used (LRU) algorithm. . This is because the most common algorithm that shows good performance in non-regular reference patterns is LRU.

In addition, since the virtual regions G1 and G2 also have a limit on the cache size, when a space shortage occurs when new meta information is stored in the virtual regions G1 and G2, the computing device 100 is the oldest in the virtual regions G1 and G2. Meta information of the file block entered in G2) can be deleted.

6 is a diagram illustrating a method for dynamically allocating a buffer cache according to an embodiment of the present invention.

A case in which a file block required in an image generation process through rendering already exists in the buffer cache 130 can be roughly classified into three types. The first case is a case in which a required file block exists in the actual area T1 of the texture area (T area) or the actual area C1 of the environment setting area (C area). In this case, as a case in which a cache hit occurs because a loop of repeated reference is stored in the buffer cache 130 , modification of meta information for management of the buffer cache 130 may not be necessary.

The second case is a case in which a requested file block exists in an arbitrary reference area (area O). In this case, the computing device 100 may move the corresponding file block to a point having the highest priority on the LRU list.

Finally, the third case is a case in which a required file block exists in the virtual regions G1 and G2. For reference, this may overlap with the second case. In this case, the computing device 100 may improve performance by dynamically adjusting the cache size for each region of the buffer cache 130 . Specifically, when a required file block exists in the virtual regions G1 and G2, the computing device decreases the size of the corresponding virtual region by 1 and increases the size of the corresponding real region by 1 in order to improve the performance of the buffer cache 130 . can do it In this case, the computing device 100 may adjust the size of the region having another repeating reference pattern by one in order to maintain the cache size S according to the buffer cache size rule.

For example, when a required file block is found in the virtual region G1 (or G2), the computing device 100 increases the size of the real region T1 (or C1) by 1, instead of increasing the size of the real region C1 (or C1) having a different repeating reference pattern. Alternatively, the size of T1) may be reduced by 1. Accordingly, the size of the virtual region G2 (or G1) may also be increased by one.

7 is a flowchart illustrating a buffer cache management method according to an embodiment of the present invention.

In operation 710 , the computing device 100 may identify a reference pattern for an environment setting file block and a texture input file block required in an image generation process through rendering, and a result file block generated as a result of rendering. In this case, the computing device 100 may identify the reference pattern by using the reference frequency of the environment setting file block and the texture input file block referenced by the rendering software performing the rendering in the process of generating the image.

In step 720 , the computing device 100 uses the buffer cache 130 based on the identified reference pattern as a texture area for storing the texture input file block identified as having the repeating reference pattern of the first period, the first It can be divided into an environment setting area for storing the environment setting file block identified as having a repeating reference pattern of a second period longer than the period, and an arbitrary reference area.

In this case, the computing device 100 may determine the cache size of the divided texture area and the environment setting area based on the workload of each of the environment setting file block and the texture input file block.

In step 730 , when a file block to be stored in the buffer cache 130 is received, the computing device 100 stores a file block of the same type as that of the received file block among the texture area and the environment setting area. can be stored in At this time, when it is necessary to replace the file blocks stored in the texture area and the environment setting area, the computing device 100 emits the most recently referenced file block using the MRU (Most Recently Used) algorithm, and the newly received file block can be saved.

And, when the file block emitted from the texture area and the environment setting area has an arbitrary reference pattern, the computing device 100 may store it in the arbitrary reference area. At this time, when it is necessary to replace the file blocks stored in the random reference area, the computing device 100 uses the LRU (Least Recently Used) algorithm to emit the longest unreferenced file block and store the newly received file block. have.

Meanwhile, the texture area includes a first real area in which the texture input file block is stored and a first virtual area for checking the performance contribution according to the cache hit ratio, and the environment setting area is a second real area in which the environment setting file block is stored. and a second virtual region for checking performance contribution according to the cache hit ratio.

In this case, when the file blocks stored in the first real area of the texture area and the second real area of the environment setting area need to be replaced, the computing device 100 converts the metadata of the file block to be emitted into the first virtual area and the second virtual area. Each area can be saved.

In operation 740 , the computing device 100 may adjust the cache size of the texture area or the environment setting area based on the cache hit ratio of the file blocks stored in the buffer cache 130 . Specifically, the computing device 100 decreases the cache size of the first virtual region and reduces the cache size of the first real region when a texture input file block required in the image creation process through rendering is found in the first virtual region of the texture region. The cache size may be increased, but the cache size of the second real region may be decreased to maintain the buffer cache size rule, and the cache size of the second virtual region may be increased.

Meanwhile, the method according to the present invention is written as a program that can be executed on a computer and can be implemented in various recording media such as magnetic storage media, optical reading media, and digital storage media.

Implementations of the various techniques described herein may be implemented in digital electronic circuitry, or in computer hardware, firmware, software, or combinations thereof. Implementations may be implemented for processing by, or for controlling the operation of, a data processing device, eg, a programmable processor, computer, or number of computers, a computer program product, ie an information carrier, eg, a machine readable storage It may be embodied as a computer program tangibly embodied in an apparatus (computer readable medium) or a radio signal. A computer program, such as the computer program(s) described above, may be written in any form of programming language, including compiled-blocked or interpreted languages, as a stand-alone program or as a module, component, subroutine, or computing environment. It can be deployed in any form including as other units suitable for use in A computer program may be deployed to be processed on one computer or multiple computers at one site or to be distributed across multiple sites and interconnected by a communications network.

Processors suitable for processing a computer program include, by way of example, both general and special purpose microprocessors, and any one or more processors of any kind of digital computer. Generally, a processor will receive instructions and data from either read-only memory or random access memory or both. Elements of a computer may include at least one processor that executes instructions and one or more memory devices that store instructions and data. In general, a computer may include one or more mass storage devices for storing data, for example magnetic, magneto-optical disks, or optical disks, receiving data from, sending data to, or both. may be combined to become Information carriers suitable for embodying computer program instructions and data are, for example, semiconductor memory devices, for example, magnetic media such as hard disks, floppy disks and magnetic tapes, Compact Disk Read Only Memory (CD-ROM). ), an optical recording medium such as a DVD (Digital Video Disk), a magneto-optical medium such as a floppy disk, a ROM (Read Only Memory), and a RAM (RAM). , Random Access Memory), flash memory, EPROM (Erasable Programmable ROM), EEPROM (Electrically Erasable Programmable ROM), and the like. Processors and memories may be supplemented by, or included in, special purpose logic circuitry.

In addition, the computer-readable medium may be any available medium that can be accessed by a computer, and may include both computer storage media and transmission media.

While this specification contains numerous specific implementation details, they should not be construed as limitations on the scope of any invention or claim, but rather as descriptions of features that may be specific to particular embodiments of particular inventions. should be understood Certain features that are described herein in the context of separate embodiments may be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment may also be implemented in multiple embodiments, either individually or in any suitable subcombination. Furthermore, although features operate in a particular combination and may be initially depicted as claimed as such, one or more features from a claimed combination may in some cases be excluded from the combination, the claimed combination being a sub-combination. or a variant of a sub-combination.

Likewise, although acts are depicted in the drawings in a particular order, it should not be construed that all acts shown must be performed or that such acts must be performed in the specific order or sequential order shown to achieve desirable results. In certain cases, multitasking and parallel processing may be advantageous. Further, the separation of the various device components of the above-described embodiments should not be construed as requiring such separation in all embodiments, and the program components and devices described may generally be integrated together into a single software product or packaged into multiple software products. You have to understand that you can.

On the other hand, the embodiments of the present invention disclosed in the present specification and drawings are merely presented as specific examples to aid understanding, and are not intended to limit the scope of the present invention. It is apparent to those of ordinary skill in the art to which the present invention pertains that other modifications based on the technical spirit of the present invention can be implemented in addition to the embodiments disclosed herein.

100: computing device
110: processor
120 : storage
130: buffer cache

Claims (20)

A buffer cache management method comprising:
identifying a reference pattern for an environment setting file block and a texture input file block required in an image generation process through rendering;
the texture input file block and environment to store a texture input file block identified as having a repeating reference pattern of a first period and a configuration file block identified as having a repeating reference pattern of a second period longer than the first period dividing the buffer cache into a texture area and an environment setting area based on the workload of each setting file block;
storing a file block of the same type as that of the received file block among the texture area and the environment setting area when the file block to be stored in the buffer cache is received; and
adjusting the cache size of the texture area or the environment setting area based on a cache hit ratio of the file blocks stored in the buffer cache;
A buffer cache management method, including According to claim 1,
The identifying step is
A buffer cache management method for identifying the reference pattern by using the reference frequency of the environment setting file block and the texture input file block referenced in the process of generating an image by the rendering software performing the rendering. delete According to claim 1,
The saving step is
When it is necessary to replace the file blocks stored in the texture area and the environment setting area, the most recently used (MRU) algorithm is used to release the most recently referenced file block and to store the newly received file block. . According to claim 1,
The buffer cache is
Further comprising an arbitrary reference area other than the texture area and the environment setting area,
The saving step is
When the file block emitted from the texture area and the environment setting area has an arbitrary reference pattern, the buffer cache management method stores the file block in the arbitrary reference area. 6. The method of claim 5,
The saving step is
When it is necessary to replace the file blocks stored in the random reference area, the LRU (Least Recently Used) algorithm is used to release the longest unreferenced file block and to store the newly received file block. According to claim 1,
The texture area is
a first real area in which the texture input file block is stored and a first virtual area for checking performance contribution according to a cache hit ratio;
The environment setting area is
and a second real area in which the environment setting file block is stored and a second virtual area for checking a performance contribution according to a cache hit ratio. 8. The method of claim 7,
The sum of the cache sizes for the first real region of the texture region and the second real region of the environment setting region is,
A buffer cache size rule equal to the sum of the cache sizes for the first real region and the first virtual region of the texture region and equal to the sum of the cache sizes for the second real region and the second virtual region of the configuration region applies How to manage the buffer cache. 8. The method of claim 7,
The saving step is
A buffer for storing metadata of the file blocks to be emitted in the first virtual area and the second virtual area, respectively, when it is necessary to replace the file blocks stored in the first real area of the texture area and the second real area of the environment setting area How to manage your cache. 9. The method of claim 8,
The adjusting step is
When the texture input file block required in the image creation process through the rendering is found in the first virtual region of the texture region,
Decrease the cache size of the first virtual region, increase the cache size of the first real region, and decrease the cache size of the second real region to maintain the buffer cache size rule; A buffer cache management method that increases the cache size. In the computing device to which the buffer cache management method is applied,
including a processor;
The processor is
Identifies reference patterns for configuration file blocks and texture input file blocks required in the image creation process through rendering,
the texture input file block and environment to store a texture input file block identified as having a repeating reference pattern of a first period and a configuration file block identified as having a repeating reference pattern of a second period longer than the first period Splits the buffer cache into a texture area and a preference area based on the workload of each configuration file block;
When a file block to be stored in the buffer cache is received, it is stored in an area in which a file block of the same type as the received file block is stored among the texture area and the environment setting area;
A computing device for adjusting a cache size of the texture area or the environment setting area based on a cache hit ratio of the file blocks stored in the buffer cache. 12. The method of claim 11,
The processor is
A computing device for identifying the reference pattern by using the reference frequency of the environment setting file block and the texture input file block referenced in the process of generating an image by the rendering software performing the rendering. delete 12. The method of claim 11,
The processor is
When it is necessary to replace the file blocks stored in the texture area and the environment setting area, the most recently used (MRU) algorithm is used to emit the most recently referenced file block and to store the newly received file block. 12. The method of claim 11,
The buffer cache is
Further comprising an arbitrary reference area other than the texture area and the environment setting area,
The processor is
If the file block emitted from the texture area and the environment setting area has an arbitrary reference pattern, the computing device stores the file block in the arbitrary reference area. 16. The method of claim 15,
The processor is
When it is necessary to replace the file blocks stored in the random reference area, a computing device that uses a least recently used (LRU) algorithm to release a file block that has not been referenced for a long time and stores the newly received file block. 12. The method of claim 11,
The texture area is
a first real area in which the texture input file block is stored and a first virtual area for checking performance contribution according to a cache hit ratio;
The environment setting area is
A computing device comprising: a second real area in which the configuration file block is stored; and a second virtual area for checking a performance contribution according to a cache hit ratio. 18. The method of claim 17,
The sum of the cache sizes for the first real region of the texture region and the second real region of the environment setting region is,
A buffer cache size rule equal to the sum of the cache sizes for the first real region and the first virtual region of the texture region and equal to the sum of the cache sizes for the second real region and the second virtual region of the configuration region applies becoming a computing device. 18. The method of claim 17,
The processor is
Computing for storing the metadata of the file blocks to be emitted in the first virtual area and the second virtual area when it is necessary to replace the file blocks stored in the first real area of the texture area and the second real area of the environment setting area Device. 19. The method of claim 18,
The processor is
When the texture input file block required in the image creation process through the rendering is found in the first virtual region of the texture region,
Decrease the cache size of the first virtual region, increase the cache size of the first real region, and decrease the cache size of the second real region to maintain the buffer cache size rule; A computing device that increases the cache size.

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