JP6243884B2 - Information processing apparatus, processor, and information processing method - Google Patents

Description

  The present invention relates to an information processing apparatus and information processing method using a flash memory as a secondary storage device.

  With the expansion of the capacity of NAND flash memories, SSDs (Solid State Drives) have come to be used as storage devices that replace conventional HDDs (Hard Disk Drives) (see, for example, Patent Document 1). In general, an SSD includes a storage device in which a plurality of NAND flash memory devices are arranged in parallel, and can achieve data access much faster than an HDD by paralleling individual device performance and parallelism.

WO 2014/132346 A1

  Various procedures are required from when an application makes an access request to a file stored in the SSD to when processing using the data of the file is actually started. Typically, the logical address is obtained by referring to the metadata based on the requested file name, the logical address is converted into a physical address representing the area where the data is actually stored, or the read data is It is necessary to perform tampering checks and decryption processing. These processes tend to become more complex as the capacity of the flash memory increases, and there is a problem that an increase in processing load leads to latency and the high transmission rate of the SSD cannot be utilized.

  The present invention has been made in view of these problems, and an object of the present invention is to provide a technique capable of improving the efficiency of data access in an information processing apparatus using an SSD.

  One embodiment of the present invention relates to an information processing apparatus. This information processing device has a main processor that issues an access request for a file stored in a secondary storage device, receives the access request, issues the access request for each of a plurality of data blocks constituting the file, The sub-processor that notifies the main processor when all the data blocks that make up the memory are read and accessible, and the access request from the sub-processor is accepted, and the sub-block is read each time the requested data block is read from the secondary storage device. And a controller for notifying the processor.

  Another aspect of the invention relates to a processor. The processor receives an access request for a file stored in the secondary storage device in the information processing apparatus from another processor, and divides the access request into access requests for each of a plurality of data blocks constituting the file, An access request issuing unit that issues the access request issued to the controller that controls access to the secondary storage device, and when all the data blocks constituting the file are read and accessible by the controller, the other And a notification unit for notifying the processor.

  Yet another embodiment of the present invention relates to an information processing method. The information processing method includes a step in which a main processor issues an access request to a file stored in a secondary storage device, and an access request for each of a plurality of data blocks constituting a file, in which a sub processor accepts the access request. A step in which the controller accepts an access request from the sub processor and notifies the sub processor each time the requested data block is read from the secondary storage device, and the sub processor configures the file And a step of notifying the main processor when all the data blocks to be read are read and accessible.

  Note that any combination of the above-described components, and the expression of the present invention converted between a method, an apparatus, a system, a computer program, a recording medium on which the computer program is recorded, and the like are also effective as an aspect of the present invention. .

  According to the present invention, an information processing apparatus using SSD can be made efficient in both resources and processing time.

It is a figure which shows the internal structure of the information processing apparatus in this Embodiment. It is a figure which shows typically the relationship between the data stored in the flash memory in this Embodiment, and the structure of an address conversion table. It is a figure for demonstrating the method of acquiring the storage area of the data of 2nd address space in this Embodiment. It is a figure which shows the internal structure of the information processing apparatus in this Embodiment. It is a figure which shows the structure of the software stack in this Embodiment. It is a figure which shows typically the procedure in which the file archive and flash controller in this Embodiment store the file data to be processed in the flash memory. It is a figure which shows typically the process sequence until it accesses the file requested | required using the file archive in this Embodiment. It is a figure which shows typically the process sequence until the reading of the file requested | required using the file archive in this Embodiment is completed.

  FIG. 1 shows an internal configuration of the information processing apparatus according to the present embodiment. The information processing apparatus exemplified here may be any of general information equipment such as a portable game machine, a personal computer, a mobile phone, a tablet terminal, and a PDA. The information processing apparatus 10 includes a host unit 12 including a CPU, a system memory 14, a NAND flash memory 20 (hereinafter simply referred to as a flash memory 20), and a flash controller 18.

  The host unit 12 loads programs and data stored in the flash memory 20 into the system memory 14 and performs information processing using the programs and data. The application program and data are read from a recording medium driven by a recording medium driving unit (not shown) or downloaded from a server connected to the network by a communication unit and stored in the flash memory 20. At this time, the host unit 12 issues an access request to the flash memory 20 to the flash controller 18, and the flash controller 18 performs read / write processing on the flash memory 20 accordingly.

  A plurality of NAND flash memories are connected to the flash memory 20, and data is distributed and stored in a plurality of channels (four channels "ch0" to "ch3" in the figure) as shown. The flash controller 18 includes a host controller 22 having an interface function with the host unit 12, a memory controller 28 having an interface function with the flash memory 20, and an SRAM (Static Random Access Memory) 24. The operations of the host controller 22 and the memory controller 28 can be realized by various circuits and devices in terms of hardware, and can be realized by programs stored therein in terms of software. Therefore, it is understood by those skilled in the art that the present invention can be realized in various forms by hardware only, software only, or a combination thereof, and is not limited to any one.

  The host unit 12 generates an access request for the flash memory 20 according to the progress of information processing, and stores it in the system memory 14. The access request includes an access destination logical address (LBA: Logical Block Address). The host controller 22 of the flash controller 18 reads the access request stored in the system memory 14 and converts the LBA into a physical address of the flash memory 20. At this time, at least a part of the necessary address conversion table originally stored in the flash memory 20 is expanded in the SRAM 24.

  The host controller 22 supplies the memory controller 28 with the physical address acquired based on the LBA with reference to the address conversion table. The memory controller 28 reads and writes data by accessing the corresponding area of the flash memory 20 based on the physical address. Generally, data reading / writing with respect to the flash memory 20 is performed in an access unit such as 4096 bytes.

When data is rewritten, data in the target area of the flash memory 20 is erased. In this case, the data is written in units of several MiB (1 MiB = 10 ²⁰ bytes). Since the flash memory 20 is worn as data erasure is repeated, it is necessary to devise a technique for suppressing the number of erasures. Specifically, when data rewriting occurs, the data before rewriting is not erased as much as possible, the data after rewriting is stored in another area, and the address conversion table is updated to point to the area. On the other hand, even if rewriting occurs frequently, the used area is periodically deleted so that the newly allocated area is not exhausted.

  As described above, when data is read / written in an access unit of 4096 bytes, if the data size of each entry in the address conversion table is 4 bytes, the entire address conversion table has a capacity of 0. It will have a data size of 1%. For example, if the total capacity of the flash memory 20 is 1 terabyte, the address conversion table is 1 gigabyte. Whenever the host unit 12 requests data access, the flash controller 18 needs to refer to the address conversion table in order to convert the designated LBA into a physical address.

  When the address conversion table to be referenced is stored in the flash memory 20, the frequency of accessing the flash memory 20 for address conversion increases, leading to a decrease in processing throughput and an increase in latency. Efficiency can be improved by caching a large part of the address conversion table in an external DRAM or the like, but a larger capacity DRAM is required as the capacity of the flash memory 20 increases. Further, the data transmission rate of the DRAM becomes dominant, and the throughput may not be expected to sufficiently improve the latency.

Therefore, in the present embodiment, the size of the address conversion table is suppressed by increasing the data processing unit for the write request, that is, the granularity, for at least a part of the data. For example, the particle size of the write and 128MiB, similarly above the data size of each entry of the address conversion table, when a 4-byte, the data size of the entire address translation table is a 1/2 ²⁵ times the capacity of the flash memory 20. For example it is possible to represent the area of 1TiB ^{(2 40} bytes) by the address translation table 32KiB (32 × ^{2 10} bytes).

  By storing an address conversion table having a sufficiently small size in the SRAM 24 in the flash controller 18 as described above, address conversion can be performed without any external DRAM. A mode in which the granularity of writing is coarse is particularly effective in a game program or the like that is loaded from an optical disk or a network, stored in the flash memory 20, and only repeatedly referenced. This is because, as a result of rewriting of stored data not occurring, it is not necessary to secure a new area in units for storing the rewritten data.

  Even if writing is performed with such a coarse granularity, data continuity is maintained within the writing unit, so that data at the time of reading can be randomly specified in smaller units. On the other hand, for data that needs to be rewritten, such as saved data, it is desirable that writing can be performed with fine granularity. Therefore, a plurality of conversion tables having different write granularities are defined according to the data characteristics. Since the address conversion table with fine granularity has a large data size as described above, a part of the address conversion table is cached in the SRAM 24.

  FIG. 2 schematically shows the relationship between the data stored in the flash memory 20 and the configuration of the address conversion table. A plurality of address spaces with different granularities are defined in the address conversion table. In the example shown in the figure, the address conversion table is composed of a first address space with a fine granularity and a second address space with a coarse granularity. However, the particle size may be three or more. In the figure, the LBA designated by the host unit 12 is represented in a format of “(address space number) − (address in space)”. For example, “1-1” represents an address “1” in the first address space, and “2-2” represents an address “2” in the second address space. However, other information may be included in the data such as 4 bytes describing the LBA.

  The physical address acquired by the address conversion is basically expressed in a format of “(channel number) − (address)” or “address”. On the other hand, in the flash memory 20, the storage area is represented by a vertically long rectangle for each channel. Of the rectangles formed by dividing the rectangle, a rectangle with “T” is an area in which an address conversion table is stored, and a rectangle with an LBA such as “1-1” is data corresponding thereto. Indicates the area where is stored. The granularity at the time of writing data defined in the first address space is typically equal to the granularity at the time of reading, for example, 4 KiB, and one LBA is defined for an area of the size.

  On the other hand, in the second address space, an area larger than the area defined in the first address space can be collectively defined by one LBA. In the example shown in the figure, it is a continuous region extending over four channels ch0 to ch3. The granularity at the time of writing data targeted by this address space is, for example, 128 MiB, but may be determined as appropriate according to the upper limit of the size of the address conversion table based on the capacity of the flash memory 20 and the SRAM 24. Since this data is not rewritten by information processing, its storage area and data structure are basically maintained.

  However, when a bit error is detected due to aging degradation of the flash memory 20 and data is moved, a continuous area of the size is newly allocated. In addition, when a block in the flash memory 20 becomes defective as the number of erasures increases, the peripheral blocks included in the write unit cannot be assigned to the data in the second address space. On the other hand, when the data defined in the first address space is rewritten or moved, a new area can be allocated with a fine granularity such as 4 KiB. Also, the finer the granularity, the fewer blocks that cannot be assigned due to nearby defects.

  Therefore, as described above, the size of the address translation table can be reduced and the efficiency of the data storage area in the flash memory 20 can be achieved by varying the granularity at the time of writing depending on the data characteristics. The address conversion table stored in the “T” area of the flash memory 20 is read out to the SRAM 24 separately in the first address space and the second address space. Since the address conversion table in the second address space has a small data size as described above, a cache hit can always be made by preloading all of the addresses at the time of activation.

  A part of the address conversion table in the first address space is cached according to the capacity of the SRAM 24. Conventional techniques can be applied to the cache operation procedure. When the address conversion table stored in the SRAM 24 is updated by moving or rewriting data, it is written back to the original table stored in the flash memory 20 at an appropriate timing.

  Here, it is assumed that the host unit 12 requests reading or writing by designating LBA = “1-1” as the first address space. At this time, the flash controller 18 refers to the address conversion table and acquires the physical address “ch0-C” of the flash memory 20 associated therewith. As described above, in the first address space, an LBA is set for each unit of writing and thus for each unit of reading. Therefore, data of one unit having the physical address “ch0-C” shown in the address conversion table, that is, the address C of the channel number ch0 as the head address is read.

  In the case of a write request, the read data is updated as appropriate, written to another area of the flash memory 20, and the physical address in the address conversion table is updated to indicate the area. On the other hand, when the host unit 12 designates LBA = “2-1” as the second address space and requests reading, the flash controller 18 reads the read unit based on the physical address “A” described in the address conversion table. The data storage area is calculated.

FIG. 3 is a diagram for explaining a method of acquiring a data storage area in the second address space. As described above, the upper bits of the LBA in the second address space represent a logical address uniquely given to each area of the write unit. This address corresponds to “2-1” in FIG. For example write access granularity of the second address space 128MiB ^{(2 27} bytes), the size of the address conversion table 512B ^{(2 9} bytes), if the address space is to 1TiB ^{(10 40} bytes), LBA32 of the bits Bit 31: 19 is the upper bit.

  The flash controller 18 refers to the address conversion table 100 using the upper bits as an index, and obtains a physical address (PA) associated therewith. This address corresponds to “A” or the like in FIG. 2 and represents the head physical address in the area of the write unit. FIG. 3 shows that the upper bit “index” of the LBA matches “index3” of the address conversion table 100 and the corresponding physical address “PA3” is acquired.

  In the case of the first address space, as described above, data may be read from the read unit area having “PA3” as the head address. On the other hand, in the case of the second address space, the flash controller 18 adds the lower bit of the LBA indicated as “offset” in the drawing and the acquired physical address “PA3” to obtain the final physical address 102. Get as. Then, the data is read from the read unit area having the physical address 102 as the head address. The host unit 12 can read an arbitrary part of the coarse granularity write unit by changing the lower bits of the LBA.

  For the data stored in the area defined in the second address space, although the head address changes infrequently due to movement, etc., the data structure inside the write unit does not change, so the host unit 12 includes the lower bits. If the same LBA is shown, the same data can always be read out. Assuming that the number of channels = 4, the number of chip selects = 1, the block size = 4 MiB, the page size = 16 KiB, the LUN (Logical Unit Number) = 1, and the number of planes = 2 as the configuration of the flash memory 20, the physical address PA [31 : 0] are assigned as follows.

Offset [13: 0] = {PA [4: 0], 9′b0}
Channel [1: 0] = PA [6: 5]
Plane = PA [7]
Block = PA [31: 8] / (4 * 1024/16)
Page = PA [31: 8]% (4 * 1024/16)

  Next, the host unit 12 in this embodiment will be described. The flash memory 20 has a read transmission rate higher than that of one HDD, which can be realized by each of the NAND devices constituting the flash memory 20, and has a latency of 1/10 or less of that of the HDD. Since a large-capacity SSD is equipped with a large number of NAND devices, it can realize a significantly higher transmission rate than an HDD. However, in most SSDs, the host interface in the flash controller becomes a bottleneck, and the high transmission rate of the device itself cannot be fully utilized.

  In general, data stored in an HDD is divided into 512-byte or 4096-byte blocks, and is recorded in a distributed manner. The file system has metadata for making distributed data appear as one continuous data, and converts an access command for a continuous area of a file into an access command for a plurality of distributed blocks. Since the metadata for converting the file name to be accessed into the LBA corresponding to each block of the HDD is also recorded in the HDD, the metadata must first be read in order to read the file.

  Since the metadata itself may also be distributed over multiple areas in the HDD, small data access to the HDD by layering metadata, such as reading higher-level metadata to read the metadata, etc. May occur frequently. Meanwhile, since the logical block address of the area where the access destination data is stored cannot be acquired, the CPU cannot issue the next read request. When such a data access procedure is directly applied to the SSD, a high transmission rate by parallel access to a plurality of NAND devices cannot be realized.

  Further, since a general HDD does not have an encryption or tampering prevention function, the host CPU needs to perform encryption or tampering check. Encryption and tampering checks may be done at the BIOS level or at the file system level, but in either case, the CPU processes them, and this process becomes a bottleneck for high SSD transmission rates. obtain. It is conceivable to distribute the load of these processes using an accelerator, but for that purpose, it is necessary to divide the read file into processing units and issue a number of processing requests according to the processing units. It is difficult to reduce the load.

  Furthermore, the processing of the CPU may be delayed due to the occurrence of a large number of interrupts notifying completion of such a large number of processing requests. Some file systems support data compression. In this case, the file system performs data compression when writing the file and performs data expansion when reading the file. At this time, if the interface speed of the data storage destination is slow, the effective transmission rate may be improved by reducing the amount of data, but the data compression / decompression process may become a bottleneck for a high transmission rate of SSD. .

  In this way, the transmission rate that is dramatically improved when the NAND flash device alone is viewed cannot often be utilized due to various bottlenecks caused by being incorporated in a system designed for the HDD. In order to alleviate these various bottlenecks, in this embodiment, a software stack for high-speed access is provided in addition to the conventional file system. A conventional file system is accessed through a virtual file system to support various storage devices and network file systems. Therefore, as described above, the metadata is configured across a plurality of hierarchies, and the metadata may be read many times before the target file is read.

  In the present embodiment, metadata is simplified by providing a software stack for high-speed access specialized for flash memory. Furthermore, in this embodiment, in addition to the conventional CPU, an auxiliary processor that mainly executes and controls the software stack is provided, and the hardware accelerator for encryption / decryption, tampering check, and data decompression is also controlled. The processing is distributed by the processor. Further, an efficient read process is realized by expanding and unifying the unit of data read in the flash memory.

  FIG. 4 shows the internal configuration of the information processing apparatus of this embodiment. This figure shows in detail the configuration of the host unit 12 in the internal configuration of the information processing apparatus 10 shown in FIG. Accordingly, the flash memory 20, the flash controller 18, and the system memory 14 may be the same as those shown in FIG. However, the address conversion table for the flash controller 18 to convert the LBA into a physical address may be composed of a plurality of address spaces having different granularities as described above, or may have a unified granularity.

  The host unit 12 has a configuration in which a main CPU 30, a sub CPU 32, and a memory controller 34 are connected to each other via a coherent bus 36. The coherent bus 36 is further connected to an IO bus 38 to which an IO controller 40 and an accelerator 42 are connected. The main CPU 30 loads programs and data stored in the flash memory 20 into the system memory 14 and performs information processing using the programs and data.

  As described above, the sub CPU 32 is an auxiliary processor mainly responsible for processing for data access to the flash memory 20. The sub CPU 32 may be a processor core that is inferior to the main CPU 30 but has a small chip area as used in a so-called embedded processor. The instruction set architecture and operating system of the main CPU 30 and the sub CPU 32 do not need to be the same, but are connected by a coherent bus 36 so that the main CPU 30 and the sub CPU 32 can share data stored in the system memory 14. The page size is also common.

  The sub CPU 32 divides the file read request issued from the main CPU 30 into read requests for data of a predetermined size and stores them in the system memory 14. As described above, in the present embodiment, hardware other than the main CPU 30 performs the main part of data access to the flash memory 20, and the read unit is made fine immediately after issuing the access request to the file. This enables parallel access to a plurality of NAND devices and realizes a high transmission rate. In addition, the buffer that stores the read data in the built-in SRAM, the processing performed by the accelerator, such as encryption and falsification check, and the data size are made highly compatible so that the processing is not delayed.

  The IO bus 38 includes an accelerator 42 that performs cryptographic processing, data falsification check, and data expansion. They read the data stored in the system memory 14 by a DMAC (not shown), perform decoding, tampering check, and data expansion, and store them again in the system memory 14 by the DMAC. The flash controller 18 reads a command related to data access issued by the host unit 12 from the system memory 14 and performs read / write processing on the flash memory 20.

  The flash controller 18 temporarily stores the data read from the flash memory 20 in the built-in SRAM 24, performs an ECC check, and transfers the data to the system memory 14. The memory controller 34 and the IO controller 40 of the host unit 12 have general interface functions for the system memory 14 and the flash controller 18, respectively.

  FIG. 5 shows the configuration of the software stack in the present embodiment. In a general technique, when a command is issued from the uppermost application 50, the virtual file system 48 is processed by a system call. As a result, a local file system 46 such as a network file system or a disk file system is called, and access to the corresponding device driver 44 is realized. In other words, the virtual file system 48 is an abstraction layer that provides a function for enabling the application 50 to handle the local file system 46 corresponding to various devices in a common method.

  The virtual file system 48 manages directory entry information constituting the metadata, interprets the file name and path, and calculates where the data is in each device. At this time, since complicated processing such as directory tree search, exclusive control, and cache management is involved, for example, when a large number of small files are opened, the processing is particularly likely to be delayed. Therefore, in this embodiment, a layer called a file archive 52 is defined separately from the virtual file system 48. The application 50 accesses the file via an API (Application Programming Interface) specific to the file archive.

  The file archive 52 is an interface between the NAND flash driver that operates the flash memory 20 and the accelerator driver that operates the accelerator 42 and the application 50, and directly notifies the driver of access requests from the application. This simplifies the process of acquiring the data storage area corresponding to the file. The target data is stored in the flash memory 20 in a specific format so that the access requests divided into fine units can be processed in parallel smoothly.

  Specifically, a file accessed via the file archive 52 is divided into fixed-length blocks such as 64 KiB, compressed, and stored. Also, by making these files read-only, consistency is maintained even if a plurality of processes of the application 50 perform file access simultaneously. As a result, a plurality of file accesses can be processed in parallel without performing synchronization processing, and a higher transmission rate can be realized by a synergistic effect with data size reduction by compression.

  For example, a file that is repeatedly referred to as in the above-described game program is suitable for processing by a file archive. As described above, whether or not to be processed by the file archive 52 is appropriately determined according to the data characteristics. FIG. 6 schematically shows a procedure in which the file archive 52 and the flash controller 18 store the file data to be processed in the flash memory 20. The execution subject of the file archive at this stage is the main CPU 30 or the sub CPU 32. First, the file archive 52 writes the file 112 to be processed into a continuous area of the flash memory 20.

  In the figure, only one file 112 is shown, but actually, a plurality of files are collectively stored in a continuous area. For example, a write request is issued so that a plurality of program files read from an optical disc or the like are written in a continuous area with a coarse granularity such as 128 MiB. The actual writing process is performed by the flash controller 18. Here, the file archive 52 generates a hash list so that the logical address of the storage destination area can be directly subtracted from the file name. That is, a fixed-length hash value is generated from a file name using a predetermined hash function, and an entry indicating the logical address of the file is sorted by the hash value to generate a hash list. However, the address search mechanism is not limited to this.

  Next, the file archive 52 divides the target file 112 thus stored in the continuous area of the flash memory 20 into blocks of a predetermined size (S10). For example, a block group 114 of 256 blocks is formed by dividing a file 112 having a size of 16 MiB in units of 64 KiB. Further, the file archive 52 performs compression processing for each block, and requests the flash controller 18 to store the data 116 including the compressed block group in another area of the flash memory 20 (S12). In this case as well, data is written in a continuous area with a coarse granularity such as 128 MiB.

  The flash controller 18 generates an address conversion table that associates the logical address of the compressed data with the physical address of the area where the actual data is stored, along with the execution of the storage process. By associating the compressed data with logical addresses with a coarse granularity, the second address space shown in FIG. 2 is defined, and the data size of the address conversion table 64 can be reduced. On the other hand, the file archive 52 generates a compression table that associates logical addresses before and after compression of blocks.

  FIG. 7 schematically shows a processing procedure until the requested file is accessed using the file archive. First, when it becomes necessary to read a file during the process, the main CPU 30 that processes the application calls the file archive API by designating the file name. In the figure, the path and file name “/map/001/dat01.bin” are specified. With the API, the main CPU 30 acquires a logical address corresponding to the designated file using the hash list 60 described above. The hash list 60 is loaded from the flash memory 20 into the system memory 14 in advance.

  Based on the file name specified in the application, a hash value is derived using the same hash function as when the hash list was created (S20), and the corresponding logical address is obtained by searching the hash list 60 in a binary manner. (S22). When the sub CPU 32 is notified of the acquired logical address, the main CPU 30 is temporarily released from the processing of the file archive 52 by the sub CPU 32 taking over the processing. The sub CPU 32 refers to the compression table 62 loaded in the system memory 14 and obtains the compressed logical addresses of a plurality of blocks obtained by dividing the file from the notified logical addresses of the file ( S24, S26).

  Then, the sub CPU 32 generates a read request specifying the acquired logical address as the above-mentioned LBA format for each block after compression, and issues it to the flash controller 18 (S28). That is, the sub CPU 32 converts a read request issued by the main CPU 30 for one file into a plurality of read requests in units of blocks. In the case of the 16 MiB file described above, 256 read requests in 64 KiB units are issued. Note that the sub CPU 32 reserves a storage area for the read data in the kernel area of the system memory 14 at the time of the read request.

  In response to this, the flash controller 18 converts the LBA into a physical address using the address conversion table 64 and acquires the data of the corresponding address from the flash memory 20 (S30). In the address conversion, the flash controller 18 refers to the address conversion table 64 using the LBA upper bits as an index for a read request with a file archive as a request source, and assigns the LBA lower bits to the physical address associated therewith. Is added to obtain the physical address for each requested block.

  FIG. 8 schematically shows a processing procedure until reading of the requested file using the file archive is completed. First, the flash controller 18 reads the requested data from the flash memory 20 as described with reference to FIG. 7, and develops it in the built-in SRAM 24 (S40). This data is a unit obtained by dividing the original file into blocks and compressed, and has a size that can be sufficiently stored in the SRAM 24. Then, the flash controller 18 performs an ECC check on the unit data (S42).

  When the ECC check is passed, the data is stored in the kernel area 70 in the system memory 14 reserved in advance by the sub CPU 32 by DMAC (not shown) and the sub CPU 32 is notified of this (S44). If an error is detected by the ECC check, data is read again by generating a retransmission request in the flash controller 18. The flash controller 18 repeats the processing until all the processing for the fine unit read request issued from the sub CPU 32 is completed.

  In response to the notification from the flash controller 18, the sub CPU 32 issues an alteration check, decryption, and decompression processing request to the accelerator 42 for the data read to the kernel area 70 (S46). The accelerator 42 executes the processing for each stored data, stores the processed data, that is, the data of the blocks constituting the file in the user buffer 72 of the system memory 14 and notifies the sub CPU 32 (S48). .

  The sub CPU 32 notifies the main CPU 30 of the completion of reading by using interrupt or inter-process communication when all the data of the blocks constituting the requested file are prepared. In response to this, the main CPU 30 appropriately performs post processing accompanying the API processing of the file archive, and returns the processing to the application. In this embodiment, as shown in FIG. 5, a file stack in which the file archive 52 and the virtual file system 48 coexist is formed. As described above, in response to a request from the file archive 52, the flash controller 18 performs address conversion using the second address space in which writing is performed with coarse granularity.

  On the other hand, for the request from the virtual file system 48, the address conversion may be performed in the first address space in which writing is performed with a finer granularity. In this case, as shown in FIG. 2, two address conversion tables corresponding to each address space are individually stored in the SRAM 24, and the reference destination is switched depending on whether the request source is the file archive 52 or the virtual file system 48. The request source can be specified by the upper bits of the LBA included in the access request.

  In order to guarantee a high transmission rate for the read request by the file archive 52, the processing for the request is given higher priority than the read / write request by the virtual file system 48 and the processing for the compressed data write request by the file archive 52. You may go on. Priority control and transmission rate management are performed by the sub CPU 32 that issues a request to the flash controller 18 or the flash controller 18 that has received the request. During the period when data is being read by the request from the file archive 52, the data to be read is not erased by prohibiting another read request, and data is erased by garbage collection unless an error occurs. Can also be prohibited.

  Next, the performance of the information processing apparatus 10 having the above configuration will be examined. The processing time allowed to achieve the desired transmission rate is as shown in the following table. For example, in order to realize a transmission rate of 1 GB / second with a data granularity (processing unit) of 4 KiB per request, it is necessary to complete the processing in 4.1 μsec per request. If the time until the completion of processing is further increased, the transmission rate naturally decreases.

As described above, in the present embodiment, the main CPU 30 performs the following processing.
1. 1. Hash value calculation from file name 2. Search hash list Issuing a request to the sub CPU 32

  When the file size is as small as about 4 KiB, in order to realize a transmission rate of 10 GB / sec, it is necessary to complete the processing within 0.4 μsec per file. When read requests are frequently made in such a fine unit, the effect of parallelization is small, and it becomes easy to be affected by the transmission rate in the sub CPU 32, the flash controller 18, and the flash memory 20. It is conceivable that the transmission rate at the CPU 30 decreases. Therefore, if the data access request with such a small size is about once per 1 ms, a plurality of files are combined into one, and by requesting data access of about 10 MiB at a time, high robustness is achieved. A transmission rate of 10 GB / second can be realized.

In the present embodiment, the sub CPU 32 performs the following processing.
1. 1. A request issued by the main CPU 30 is divided into fixed-length data blocks. 2. Refer to the compression table to obtain the logical address where the compressed data is stored. 3. Issue a read request to the flash controller 18. 4. Request processing such as tampering check for the read data from the accelerator. Notify the main CPU 30 when the blocks making up the original file are ready

  The sub CPU 32 always uses fixed length data as a processing unit. For example, if the processing unit is 64 KiB, in order to realize a transmission rate of 10 GB / second, it is necessary to complete the processing at 6.6 μsec per request. For example, when a read request for a file of 16 MiB is issued from the main CPU 30, the sub CPU 32 divides it into 64 KiB and issues 256 read requests as described above. At this time, instead of processing requests one by one in 6.6 μs, a plurality of requests are processed together.

  In the present embodiment, only simplified processes such as issuing commands to the flash controller 18 and various accelerators and receiving completion notifications can be performed in parallel at high frequency. Therefore, for example, about 32 requests can be processed together and completed within 211 μsec, and as a result, a transmission rate of 10 GB / sec can be realized. Depending on the transmission rate that must be realized, for example, processing such as issuing a request to the flash controller 18 and receiving a completion notification may be distributed to a plurality of CPU cores.

In the present embodiment, the flash controller 18 performs the following processing.
1. 1. Read the request issued by the sub CPU 32 2. Refer to the address conversion table to convert LBA to physical address. 3. Read data from the corresponding area of the flash memory 20 Data is stored in the system memory 14 and a notification to that effect is sent to the sub CPU 32.

  In address conversion that requires high-speed processing, an address conversion table to be referred to is stored in the built-in SRAM 24. If the request from the sub CPU 32 is a unit of 64 KiB, it is necessary to complete the processing at 6.6 μsec per request in order to realize a transmission rate of 10 GB / sec. Since IOPS (Input Output Per Second) conversion is 151,515 IOPS, it is desirable to distribute the processing to a plurality of processor cores as in the case of the sub CPU 32. As described above, the flash controller 18 has a plurality of interface channels with respect to the flash memory 20, and the read request is further divided for each channel. For example, if a 64 KiB data read request is divided into 16 KiB processing units, four times as much IOPS is required, but these are processed in parallel by a plurality of channels, so the influence on the transmission rate is not great.

In the present embodiment, the accelerator 42 performs the following processing.
1. 1. Processing request from sub CPU 32 2. Read data from system memory 14 Tamper check, decryption, and decompression processing4. Storage of processed data in the system memory 14 and notification to the sub CPU 32

  When operating at an average throughput of 10 GB / second or more, considering the overhead between various processes, the accelerator needs a peak throughput higher than that. If the circuit operates at 128 bits / cycle and 1 GHz, the peak throughput is a sufficient value of 16 GB / second. On the other hand, if the circuit requires 16 cycles for 128-bit processing, measures such as 16 parallel accelerators may be taken.

  According to the present embodiment described above, the granularity of write access to the flash memory is made larger than the write granularity in the prior art such as a page unit. As a result, the entire address conversion table can be sized to be stored in the built-in SRAM, and there is no need to repeat access to the flash memory for address conversion. Even if the capacity of the flash memory is increased, it is not necessary to provide a large capacity external DRAM for caching the address conversion table. As a result, an increase in latency and a decrease in throughput due to access to the flash memory and the external DRAM can be prevented, and a manufacturing cost and a chip area can be reduced.

  Further, the address conversion table is divided into a plurality of address spaces, and the address conversion table suitable for the characteristics of the data can be selected by changing the granularity of the write access for each. A part of the address conversion table that defines an address space with a fine granularity is cached in the SRAM. For example, a game program or the like whose data is not updated is increased in granularity, and user data and the like that are frequently updated is decreased in granularity. As a result, it is possible to allocate a wasteful area in consideration of the characteristics of the flash memory, which is required to newly secure another area when updating data, and this can be compatible with the effect of increasing the granularity described above.

  In addition, a processor for requesting access to the flash memory is provided separately from the main processor. This processor divides the access request for each file into fine units, and the subsequent processing is performed in parallel in that unit as much as possible. To cope with this, the compressed data is stored in the flash memory for each block obtained by dividing the file. These configurations substantially increase the processing speed for one access request. Since the data to be read is also reduced in size, it is possible to buffer the SRAM in the flash controller, eliminating the need for an external DRAM.

  Further, in the software stack, in addition to the conventional file system, an interface layer that directly connects the application and the SSD is provided, thereby simplifying the processing from the file name to the address acquisition. In addition, depending on whether the requester of the read access is the interface layer or the conventional file system, priority is given to the process, the former is given higher priority, and the read unit is made larger than before, thereby improving the efficiency of the read process. This makes it possible to differentiate data read processing that requires quick reading, such as a program file, from general file read processing such as user data.

  By simplifying the metadata required from the file name to address acquisition, it is not necessary to follow the hierarchical metadata sequentially, and the data size of the metadata itself can be reduced, so the entire system memory is stored It is also possible to do. As a result, the load of memory access processing for address acquisition is greatly reduced. With the above configuration, it is possible to perform high-speed data access that makes full use of the high transmission rate of the flash memory while coexisting with conventional data access procedures for various storages.

  The present invention has been described based on the embodiments. Those skilled in the art will understand that the above-described embodiment is an exemplification, and that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are also within the scope of the present invention. is there.

  DESCRIPTION OF SYMBOLS 10 Information processing apparatus, 12 Host unit, 14 System memory, 16 External DRAM, 18 Flash controller, 20 Flash memory, 22 Host controller, 24 SRAM, 26 DRAM controller, 28 Memory controller, 30 Main CPU, 32 Sub CPU, 34 Memory controller, 36 coherent bus, 40 IO controller, 42 accelerator.

Claims (8)

A main processor that issues an access request for a file stored in the secondary storage device;
Wherein receiving the access request, the access request, issued by being divided into a plurality of access requests for each data block formed by dividing the file, the main when the data block is enabled all read access A sub-processor to notify the processor;
A controller for receiving an access request from the sub-processor and processing the data blocks individually by processing in parallel using a plurality of channels included in the secondary storage device, and notifying the sub-processor each time ; ,
An information processing apparatus comprising: The main processor uses an API (Application Programming Interface) for deriving the logical address of the storage location of the file in the secondary storage device from the attribute of the target file when the file needs to be accessed in the processing of the application program. invoke, notify the derived logical address to said sub processor,
The information processing apparatus according to claim 1, wherein the sub-processor generates the plurality of access requests by acquiring a logical address of the data block unit based on the logical address .   The file to be accessed by the main processor is compressed in units of the data block of a predetermined size, and the compressed data blocks of a plurality of files have a size larger than the read unit in the secondary storage device. The information processing apparatus according to claim 1, wherein the information processing apparatus is stored in a continuous area. The controller refers to an address conversion table for converting a logical address for each data block included in an access request from the sub-processor into a physical address in the secondary storage device;
The address conversion table defines a coarse-grained address space in which physical addresses of the large unit continuous area are collectively associated with logical addresses, and the entirety is stored in a memory built in the controller. The information processing apparatus according to claim 3.   The controller further accepts a file access request from the main processor via a file system unique to the controller, determines a path of the access request based on a logical address of an access destination included therein, and according to the result 5. The information processing apparatus according to claim 3, wherein the size of the writing unit is switched. For each data block read by the controller, further includes an accelerator for performing tampering check, decoding, and decompression processing,
The sub-processor issues a processing request to the accelerator and receives a processing completion notification from the accelerator every time the sub-processor is notified that a data block has been read from the controller. 6. The information processing apparatus according to any one of 5 above. An access request dividing unit that receives an access request to a file stored in the secondary storage device in the information processing apparatus from another processor, and divides the file into a plurality of access requests for each data block obtained by dividing the file;
The divided access requests, the access request issuing unit for issuing to the controller to be processed in parallel using a plurality of channels provided in the secondary storage device,
Each time the data block is read, a notification is acquired from the controller, and when all the data blocks are read and accessible, a notification unit that notifies the other processor;
A processor comprising: The main processor issuing a request to access a file stored in the secondary storage device;
A sub-processor that accepts the access request and issues the access request by dividing it into a plurality of access requests for each data block obtained by dividing the file;
The controller receives an access request from the sub processor and processes the data block individually by processing in parallel using a plurality of channels provided in the secondary storage device, and notifies the sub processor each time. And steps to
A step of said sub-processor, notifies the main processor when the data block is enabled all read access,
An information processing method comprising:

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