KR102058499B1 - Semiconductor memory system including reed-solomon low density parity check decoder and read method thereof - Google Patents

Abstract

The present invention provides a semiconductor memory system including an RS-LDPC decoder with reduced computation and hardware complexity, and a read method thereof. The semiconductor memory system according to the present invention includes a read data management unit for storing data read from a memory device, a likelihood value mapping unit for mapping the likelihood ratio values to data output from the read data management unit, and outputting mapping data. And a decoding unit for performing a low density parity check decoding using a parity check matrix, wherein the parity check matrix comprises k * N × containing k N × M submatrices. Where k, N, and M are two or more integers, the k N × M submatrices have a first submatrix having an N × M size and an N × M size and are adjacent to the first submatrix. And a second sub-matrix having the same element array as the matrix in which the first sub-matrix is cyclically shifted by N in the row direction according to the cyclic period M, and the first sub-matrix is a reed-sol The first row, which is a binary permutation of converting a code word generated according to a Reed-Solomon code into a symbol position vector, is located adjacent to the first row, and the first row is placed in the cycle N. According to the second and second rows having the same element array as the row cyclically shifted by 1, and having the same element array as the row in which the second row is cyclically shifted by 1 according to the cyclic period N, but having the same And a third row different from.

Description

Semiconductor memory system including Reed-Solomon low density parity check decoder and method of reading the same {SEMICONDUCTOR MEMORY SYSTEM INCLUDING REED-SOLOMON LOW DENSITY PARITY CHECK DECODER AND READ METHOD THEREOF}

The present invention relates to a semiconductor memory system, and more particularly, to a semiconductor memory system including a Reed-Solomon low density parity check decoder for correcting an error of read data when reading stored data. .

A semiconductor memory device is a memory device implemented using a semiconductor such as silicon (Si), germanium (Ge, Germanium), gallium arsenide (GaAs), or indium phospide (InP). to be. Semiconductor memory devices are largely classified into volatile memory devices and nonvolatile memory devices.

When reading data programmed into the semiconductor memory device, the read data may include an error for various reasons. In order to correct errors in the read data, error correction codes such as BCH (Bose-Chaudhuri-Hocquenghem) codes, Low Density Parity Check (LDPC) codes, Turbo codes, and the like have been studied.

In particular, the RS-LDPC code in which the Reed-Solomon (RS) code is extended to the LDPC code among the LDPC codes has a relatively excellent error correction capability since the minimum distance and the length of the girth are long. However, the RS-LDPC code has a very random structure of the parity check matrix despite the excellent error correction performance. The parity check matrix of the random structure has the disadvantage of increasing the computational throughput and hardware complexity of the RS-LDPC decoder.

An object of the present invention is to propose a simple structure parity check matrix for an RS-LDPC decoder, and a semiconductor memory system including an RS-LDPC decoder which efficiently decodes data using the proposed parity check matrix, and a read method thereof. To provide.

Another object of the present invention is to provide a semiconductor memory system including an RS-LDPC decoder having reduced computational throughput and hardware complexity, and a method of reading the same.

According to another aspect of the present invention, there is provided a semiconductor memory system including a read data manager configured to store data read from a memory device; A likelihood value mapping unit for outputting mapping data by mapping likelihood ratio values to the data output from the read data management unit; And a decoding unit configured to perform a low density parity check decoding on the mapping data using a parity check matrix, wherein the parity check matrix includes k N × M submatrices. A k * N × M matrix (where k, N, and M are integers of 2 or more), and the k N × M sub-matrixes comprise a first sub-matrix having an N × M size; And a second sub-matrix having an N × M size and positioned adjacent to the first sub-matrix, the second sub-matrix having the same element array as the matrix in which the first sub-matrix is cyclically shifted by N in the row direction according to a cyclic period M. The first sub-matrix includes: a first row which is a binary permutation of converting a code word generated according to a Reed-Solomon code into a symbol position vector; A second row adjacent to the first row and having the same elemental arrangement as the row in which the first row is cyclically shifted by one in accordance with a cyclic period N; And a third row positioned adjacent to the second row and having the same element array as the row in which the second row is cyclically shifted by one in accordance with a cyclic period N, but different from the first row.

In an embodiment, the decoding unit updates the values of the variable nodes and the check nodes with reference to the likelihood value or the check node message, and performs a decoding of the data according to the values of the updated variable nodes and check nodes. A calculator; A check node calculator which receives the updated values of the variable nodes as a variable node message and provides the check node message with reference to the received variable node message; A first network unit for relaying a variable node message transmission from the variable node block to the check node block; And a second network unit for relaying check node message transmission from the check node block to the variable node block.

The first network unit or the second network unit may include: a switch controller configured to allocate at least a portion of a variable node message input from the variable node block to any one of a plurality of channels; And a connection part including a fixed wiring block configured to wire the plurality of input terminals connected to any one channel to the plurality of output terminals.

In an embodiment, the switch controller allocates another portion of the variable node message to any one channel in place of at least a portion of the variable node message according to a clock signal.

The first network unit or the second network unit may include: a parallel shifter for dividing and assigning the variable node message to the check nodes according to the parity check matrix; And a shifter controller for controlling the operation of the parallel shifter.

In an embodiment, N is the number of elements of a Galois field used to generate the code word according to a Reed-Solomon code.

The apparatus may further include a syndrome checker configured to determine an error correction state by the low density parity check decoding.

In example embodiments, the decoding unit outputs a fail message according to the determination result of the error correction state, the read data management unit stores additional data read from the memory device in response to the fail message, and the likelihood value mapping unit The likelihood values are mapped to the additional data to output additional mapping data, and the decoding unit performs a low density parity check on the additional mapping data using the parity check matrix.

In an embodiment, the read voltage for reading the data and the read voltage for reading the additional data have different voltage levels.

In example embodiments, the apparatus may further include a storage configured to store the parity check matrix.

In example embodiments, the memory device may include a NAND flash memory.

A data reading method of a semiconductor memory system according to the present invention includes reading data stored in the semiconductor memory system using first read voltages; Performing a low density parity check decoding on the read data using a parity check matrix; And outputting a result of correcting an error of the read data according to the decoding result, wherein the parity check matrix is a k * N × M matrix including k N × M sub-matrices (where k Is an integer of 2 or more), wherein the k N × M sub-matrixes have a first sub-matrix having an N × M size; And a second sub-matrix having an N × M size and positioned adjacent to the first sub-matrix, the second sub-matrix having the same element array as the matrix in which the first sub-matrix is cyclically shifted by N in the row direction according to a cyclic period M. Wherein the first sub-matrix comprises: a first row which is a binary permutation of converting a code word generated according to a Reed-Solomon code into a symbol position vector; A second row located adjacent to the first row and having the same elemental arrangement as the row in which the first row is cyclically shifted by one in accordance with a cyclic period N; And a third row positioned adjacent to the second row and having the same element array as the row in which the second row is cyclically shifted by one in accordance with a cyclic period N, but different from the first row.

The method may further include reading back the stored data using a second read voltage different from the first read voltage according to the decoding result. Performing low density parity check decoding on the read data again using the parity check matrix.

According to another embodiment of the present invention, a data reading method of a semiconductor memory system may include reading data stored in the semiconductor memory system using normal read voltages; Restoring a parity check matrix for error correction of the read data; Performing Low Density Parity Check decoding on the read data using the reconstructed Parity Check Matrix; And outputting a result of correcting an error of the read data according to the decoding result, wherein reconstructing the low density parity check matrix comprises: reading at least one stored row of the low density parity check matrix; And restoring the low density parity check matrix such that the remaining rows of the low density parity check matrix each have an element array in the form of a cyclic shift of the read at least one row in the row direction by at least one size. One row is a binary permutation of code words generated according to Reed-Solomon codes converted to symbol position vectors.

In an embodiment, the reconstructed parity check matrix includes first and second sub-matrices having an N × M size and arranged in parallel (where N and M are integers of 2 or more), and the first sub-matrix is At least one row; A first shift row positioned adjacent to the at least one row and having the same elemental arrangement as the row in which the at least one row is cyclically shifted by one in accordance with a cyclic period N; And a second shift row positioned adjacent to the first shift row and having the same element array as the row in which the first shift row is cyclically shifted by one in accordance with a cyclic period N, wherein the second shift row is different from the at least one row. The second sub-matrix is positioned adjacent to the first sub-matrix and has the same element array as the matrix in which the first sub-matrix is cyclically shifted by N in the row direction according to the cyclic period M.

According to the present invention, a simple structure parity check matrix for an RS-LDPC decoder is proposed, and the semiconductor memory system can efficiently perform RS-LDPC decoding using the proposed parity check matrix.

In addition, the RS-LDPC decoder of the semiconductor memory system can be implemented with low hardware complexity.

In addition, the computational throughput required for the RS-LDPC decoder of the semiconductor memory system in data decoding can be reduced.

1 is a block diagram illustrating a semiconductor memory system 1000 according to an exemplary embodiment of the inventive concept.
2 is a block diagram illustrating a method of decoding data by a semiconductor memory system according to the present invention.
3 is a block diagram illustrating an ECC decoder 300 illustrated in FIG. 1.
4 is a flowchart illustrating a reading method of the semiconductor memory device shown in FIG. 1.
5 is a diagram for illustrating a parity check matrix structure of an LDPC code.
FIG. 6 is a Tanner graph illustrating a connection relationship between variable nodes and check nodes according to the parity check matrix illustrated in FIG. 5.
7 is a diagram illustrating a general parity check matrix according to an RS-LDPC code.
FIG. 8 is a diagram specifically illustrating a first sub-matrix 410 of a plurality of sub-matrix of the parity check matrix illustrated in FIG. 7.
9 to 11 illustrate a parity check matrix proposed according to the present invention.
12 is a flowchart illustrating a method of generating the parity check matrix 500 proposed by the present invention.
13 is a diagram exemplarily illustrating a parity check matrix according to the present invention.
14 is a block diagram illustrating the decoder of FIG. 3 according to an embodiment of the present invention.
FIG. 15 is a block diagram illustrating an exemplary switch network shown in FIG. 14.
16 and 17 exemplarily illustrate fixed wiring blocks of a switch network according to the present invention.
18 is a block diagram illustrating an application example of the semiconductor memory system 1000 shown in FIG. 1.
19 illustrates a memory card 3000 according to an embodiment of the present invention.
20 is a block diagram illustrating a solid state drive according to an exemplary embodiment of the present invention.
21 is a diagram illustrating a schematic configuration of a semiconductor memory system and a computing system including the same according to an embodiment of the present disclosure.

Both the foregoing general description and the following detailed description are exemplary in order to provide further explanation of the claimed invention. Therefore, the present invention is not limited to the embodiments described herein and may be embodied in other forms. The embodiments introduced herein are provided to ensure that the disclosed contents are thorough and complete, and that the spirit of the present invention can be sufficiently delivered to those skilled in the art.

In the present specification, when a part is mentioned to include a certain component, it means that it may further include other components. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram illustrating a semiconductor memory system 1000 according to an exemplary embodiment of the inventive concept. Referring to FIG. 1, the semiconductor memory system 1000 includes a storage device 100 and a controller 200. In an embodiment, the storage device 100 may include a nonvolatile memory device (eg, a flash memory device). In this case, the storage device 100 stores data by adjusting the threshold voltages of the memory cells.

The controller 200 is connected to the host and the storage device 100. In response to a request from a host, the controller 200 is configured to access the storage device 100. For example, the controller 200 is configured to control read, write, erase, and background operations of the storage device 100. The controller 200 is configured to provide an interface between the storage device 100 and a host. The controller 200 is configured to drive firmware for controlling the storage device 100.

In exemplary embodiments, the controller 200 is configured to provide a control signal and an address to the storage device 100. The controller 200 is configured to exchange data with the storage device 100.

The controller 200 includes an error correction code decoder 300. The ECC decoder 300 performs decoding using an error correction code (ECC) on the data read from the storage device 100. The ECC decoder 300 performs decoding to correct an error of the read data. The ECC decoder 300 performs decoding by using a Reed Solomon-Low Density Parity Check (RS-LDPC) code.

The controller 200 communicates with a host according to a specific communication standard. For example, the controller 200 may include a universal serial bus (USB), a multimedia card (MMC), a peripheral component interconnection (PCI), a PCI-express (PCI-express), an advanced technology attachment (ATA), a serial-ATA, parallel Communicate with the host through at least one of various communication standards such as ATA, small computer small interface (SCSI), enhanced small disk interface (ESDI), integrated drive electronics (IDE), and Firewire. .

In the present invention, a parity check matrix having a structure much simpler than a general parity check matrix is proposed. Since the parity check matrix proposed in the present invention is generated according to the RS-LDPC code, the feature of the RS-LDPC code with excellent error correction capability is maintained as it is. In addition, the present invention improves the random parity check matrix structure, which is a feature of the RS-LDPC code, so that the proposed parity check matrix has a regular and simple structure.

The proposed parity check matrix is applied to the ECC decoder 300 and used to perform LDPC decoding. At this time, the ECC decoder 300 can minimize the amount of computation required during decoding due to the simplified structure of the parity check matrix while maintaining excellent error correction performance of the RS-LDPC code. Therefore, the decoding efficiency of the memory semiconductor system 1000 may be improved.

In addition, the ECC decoder 300 may implement a switch network connecting the variable node and the check node with low hardware complexity due to the simplified structure of the parity check matrix. Accordingly, the overall hardware complexity of the memory semiconductor system 1000 may be reduced, and the chip area required for implementing the ECC decoder 300 may be reduced.

2 is a block diagram illustrating a method of decoding data by a semiconductor memory system according to the present invention. Referring to FIG. 2, the memory semiconductor system may further include an encoder 400 in addition to the storage device 100 and the ECC decoder 300 illustrated in FIG. 1. In an embodiment, the encoder 400 may be included in the controller 200 (see FIG. 1).

First, when data is input from a host (see FIG. 1), the input data is encoded by the encoder 400. At this time, the encoder 400 performs LDPC encoding on the input data using the parity check matrix. The encoded data is programmed into the storage device 100 as write data WD. In this case, the parity bits for decoding may be included in the write data.

When the read command is received, the semiconductor memory system 1000 reads data stored in the storage device 100 as read data RD. In this case, the read data RD may include an error E generated for various reasons. For example, an error E may occur due to a malfunction when the write data WD is programmed or data loss while the write data WD is being stored in the storage device 100. Alternatively, an error E may occur due to a malfunction in the read operation for reading the read data RD.

The decoder 300 performs LDPC decoding on the read data RD by using a parity check matrix to eliminate this error E. FIG. In this case, the parity check matrix used is the same as that used in encoding. The decoded result is output as decoded data Data '.

At this time, the decoding performance of the decoder 300 is greatly affected by the structure of the parity check matrix. As described above, the parity check matrix generated using the RS-LDPC code has better error correction capability than the parity check matrix based on the normal LDPC code, but has a disadvantage in that the matrix structure is complicated. If the structure of the parity check matrix is complicated, the decoder 300 needs more operations for decoding the read data RD. In addition, in LDPC decoding, the structure of the complex parity check matrix increases the hardware complexity in the network connection between the variable node and the check node.

The present invention proposes a parity check matrix having a block circulation structure in sub-matrix units and each sub-matrix having a quasi-cyclic structure while maintaining the characteristics of the RS-LDPC code. This parity check matrix has a very simple matrix structure. Therefore, the decoder 300 of the present invention can greatly reduce the amount of computation and hardware complexity required by performing RS-LDPC decoding using the proposed parity check matrix. It will be described later in detail in FIG.

3 is a block diagram illustrating an ECC decoder 300 illustrated in FIG. 1. Referring to FIG. 3, the ECC decoder 300 includes a read data manager 310, a log likelihood value mapper 320, and a decoder 330.

The read data manager 310 receives and stores read data RD (see FIG. 1) read from the storage device 100. The read data RD may include first read data RD1 and second read data RD2.

When the hard decision is performed, the read data manager 310 receives the data RD1 read using the normal read voltage from the storage device 100 and stores the data RD1 as the first read data RD1. The stored first read data RD1 may be provided to the likelihood value mapper 320 at the time of hard decision or soft decision.

In addition, when the soft decision is performed, the read data manager 310 receives the data read through the partial read voltage from the storage device 100 and stores the data read as the second read data RD2. Here, the partial read voltage means a voltage adjacent to the normal read voltage but having a different voltage level from the normal read voltage. When the soft decision is performed, the read data manager 310 provides the second read data RD2 to the likelihood value mapper 320.

The likelihood value mapper 320 is configured to map the likelihood values to the read data RD1 and RD2 provided. In an embodiment, the likelihood value mapper 320 may include a hard decision likelihood value register (not shown) for storing likelihood values to be mapped at the hard decision and a soft decision likelihood value register (s) for storing likelihood values to be mapped at the soft decision ( Not shown).

In an exemplary embodiment, when the hard decision is made, the likelihood value mapper 320 receives the first read data RD1 from the read data manager 310. The likelihood value mapper 320 maps the first read data RD1 to corresponding likelihood values according to the value of each bit of the first read data RD1.

At the soft decision, the likelihood value mapper 320 receives the second read data RD2 from the read data manager 310. The likelihood value mapper 320 maps the second read data RD2 to corresponding likelihood values according to the value of each bit of the second read data RD2.

In hard decision or soft decision, the result mapped by the likelihood value mapper 320 is output to the decoder 330 as likelihood value data LLR.

The decoder 330 receives the likelihood value data LLR from the likelihood value mapper 320 when the hard decision or the soft decision is made. The determination unit 330 LDPC decodes the received likelihood value data LLR. In the hard decision and the soft decision, each likelihood value data LLR is LDPC decoded using the same method and apparatus.

The determiner 330 updates the check nodes and variable nodes according to the parity check matrix at the time of LDPC decoding. The determination unit 330 performs a provisional decoding according to the update result (for example, posterior probability), calculates the decoded data and the parity check matrix, and determines whether the decoding is correctly performed according to the operation result. do.

In an embodiment, if the result of the calculation with the parity check matrix is zero, it is determined that decoding is performed correctly. Otherwise, it is determined that decoding has not been performed correctly.

If the decoding is correctly performed, the decoder 330 outputs the decoded data as the decoded data CD. If the correct decoding was not performed (ie, the error of the read data RD was not all corrected), the decoder 330 again updates the check nodes and the variable nodes.

Update and tentative decoding of the check nodes and variable nodes as described above are performed iteratively. Update and provisional decoding of check nodes and variable nodes may constitute one decoding loop.

When the hard decision is performed in the decoder 330 and the parity check according to the hard decision fails, the decoder 330 transmits a fail message to the read data manager 310. The read data manager 310 transmits a read request for soft decision to the controller 200 (see FIG. 1) in response to a fail message. Alternatively, when the hard decision is performed in the decoder 330 and the parity check according to the hard decision fails, the decoder 330 directly transmits a fail message to the controller 200. The controller 200 may prepare a read operation for soft decision in response to a fail message or a read request.

When the soft decision is performed, the second read data RD2 is stored in the read data manager 310. The stored second read data RD2 is provided to the likelihood value mapper 320 and used to map corresponding likelihood values. In an embodiment, when the soft decision is performed, the first read data RD1 may be provided together with the second read data RD2.

The second read data RD2 is data read using the partial read voltage to additionally obtain information about threshold voltages of the memory cells. In the soft decision, various likelihood values are mapped based on the additional information according to the second read data RD2. For example, if a memory cell is read as '1' by the normal read voltage but read as '1' with a threshold voltage close to '0' by the partial read voltage, then this memory cell is relatively low. It is mapped to have a likelihood value. On the other hand, if one memory cell is read as '1' by the normal read voltage and has a threshold voltage that is significantly different from '0' by the partial read voltage, such a memory cell has a relatively high likelihood value. Is thought to have. By using additional information on the threshold voltages of the memory cells, the decoding accuracy of the soft decision is higher than the decoding accuracy of the hard decision.

In the present invention, the decoder 330 uses a parity check matrix having a simple matrix structure according to the RS-LDPC code. Thus, the decoder 330 can reduce the amount of computation required while maintaining high error correction capability. As will be described later, in particular, since the switching network between the variable nodes and the check nodes can be implemented with a very simple structure, the hardware configuration for implementing the decoder 330 can be simplified, and the required hardware area can be reduced.

Since the general configuration of the decoder 330 and the general method of RS-LDPC decoding, which are not described herein, are well known in the art, a description thereof will be omitted.

4 is a flowchart illustrating a reading method of the semiconductor memory device shown in FIG. 1. Referring to FIG. 4, the read method of the semiconductor memory device 1000 includes steps S110 to S180.

In operation S110, the semiconductor memory device 1000 reads data stored in the storage device 100 (see FIG. 1) as first read data using the first read voltage. The first read voltage may be the normal read voltage described above.

In operation S120, the semiconductor memory device 1000 performs hard decision using the proposed parity check matrix for the first read data. At this time, since the proposed parity check matrix has a simple matrix structure, the amount of computation required for hard decision is reduced and the hardware complexity of the decoder 330 (see FIG. 3) is reduced. A detailed description of the proposed parity check matrix will be described later.

In operation S130, the semiconductor memory device 1000 determines whether decoding of the first read data is performed without error as a result of the hard decision. If there is no error in the decoded data, the read method proceeds to step S180. If there is an error in the decoded data, the read method proceeds to step S140.

In operation S140, the semiconductor memory device 1000 reads data stored in the storage device 100 as second read data using the second read voltage. Here, the second read voltage may be the partial read voltage described above.

In operation S150, the semiconductor memory device 1000 performs soft decision using the proposed parity check matrix for the second read data.

In operation S160, the semiconductor memory device 1000 determines whether decoding of the first and second read data is performed without error as a result of the soft decision. If there is no error in the decoded data, the read method proceeds to step S180. If there is an error in the decoded data, the read method proceeds to step S170.

In operation S170, the semiconductor memory device 1000 determines that data reading has failed, and outputs a read error message. When the step S170 ends, the read method ends.

Returning to step S140 or step S160, when the reading method proceeds to step S180, the semiconductor memory device 1000 outputs the decoded data, and the reading method ends.

According to the above configuration, a read method of the semiconductor memory device 1000 according to an exemplary embodiment of the inventive concept is provided. At this time, the read method performs RS-LDPC decoding using the proposed parity check matrix. In addition, since the proposed parity check matrix has a simplified matrix structure, the read method according to the present invention can reduce the amount of computation required for RS-LDPC and greatly reduce the hardware complexity of the decoder 330.

5 is a diagram for illustrating a parity check matrix structure of an LDPC code. Referring to FIG. 5, a parity check matrix H, check nodes C1, C2, and C3 and variable nodes V1, V2, V3, V4, and V5 are shown.

The elements of the first row, the elements of the second row, and the elements of the third row of the elements of the parity check matrix H form the first to third check nodes C1, C2, and C3, respectively. . The elements of the first to fifth columns of the elements of the parity check matrix H form the first to fifth variable nodes V1, V2, V3, V4, and V5, respectively.

As shown in Fig. 5, each element of the parity check matrix H belongs to a check node and a variable node at the same time. In this case, when any element of the parity check matrix H is '1', it means that the check node to which the element belongs and the variable node are connected to each other. For example, when the element H ₁₁ of the first row and the first column of the parity check matrix H is '1', the first check node C1 and the first variable node V1 to which the element H ₁₁ belongs. ) Are connected to each other.

Meanwhile, the parity check matrix H used in the ECC decoder 300 is not limited to the matrix shown in FIG. 5. For example, a parity check matrix having a lower density "1" than the parity check matrix H of FIG. 5 may be used in the ECC decoder 300. The size of the parity check matrix used in the ECC decoder 300 is also not limited to being 3 × 5 as shown in FIG. 5.

FIG. 6 is a Tanner graph illustrating a connection relationship between variable nodes and check nodes according to the parity check matrix illustrated in FIG. 5. Referring to FIGS. 5 and 6, the Tanner graph shown is provided between the first to third test nodes C1, C2, and C3 and the first to fifth variable nodes V1, V2, V3, V4, and V5. Represents a connection relationship.

When an element H _ij of the parity check matrix H is '1', the check node C _i to which the element H _ij belongs in the tanner graph is connected to the variable node V _j by a line. In LDPC decoding (including RS-LDPC decoding), variable nodes process the data and send the processed data to connected check nodes. Likewise, in LDPC decoding (including RS-LDPC decoding), check nodes transmit the data processed at the check node to the connected variable nodes. As such, in the LDPC decoding process, check nodes and variable nodes repeatedly exchange data according to a connection relationship.

Referring again to FIGS. 4 and 5, elements '1' of the first column, the third column, and the fifth column of the elements of the first test node C1. Accordingly, the first test node C1 is connected to the first variable node V1, the third variable node V3, and the fifth variable node V5, respectively. Similarly, since the elements of the third and fourth columns of the second check node C2 are '1', the second check node C2 is connected to the third variable node V3 and the fourth variable node V4, respectively. do. In addition, since the elements of the first, third and fourth columns of the third test node C3 are '1', the third test node C3 is the first variable node V1 and the third variable node V3. ) And the fourth variable node V4.

In an embodiment, the connection between the check nodes C1, C2, and C3 and the variable nodes V1, V2, V3, V4, and V5 may be implemented through a separate switch network. In this case, as described above, the connection relationship between nodes depends on the values of the elements of the parity check matrix H and the matrix structure. Therefore, the more irregular and complex the structure of the parity check matrix H becomes, the more complicated the hardware configuration of the switch network is.

7 is a diagram illustrating a general parity check matrix according to an RS-LDPC code. Referring to FIG. 7, the parity check matrix 400 may include a plurality of sub matrices 410, 420, and 430.

Each row of the plurality of sub-matrices 410, 420, and 430 has a binary permutation that converts a code word generated according to a Reed-Solomon code into a symbol position vector as an element. .

In addition, each of the plurality of sub-matrices 410, 420, and 430 includes a plurality of N × N square matrices. Here, N denotes the number of elements of the Galois-field used to generate codewords according to Reed-Solomon (RS) codes.

Referring again to FIG. 7, a matrix 411 incorporating an A matrix among a plurality of N × N square matrices is shown. In this example, it is assumed that N = 8. In FIG. 7, the matrix A 411 is represented by a plurality of quadrangles constituting a grid having eight rows and eight columns. In this case, the black square (a) means that the corresponding element is '1'. In contrast, the white square b means that the corresponding element is '0'.

For example, if the black square a is located in the fourth row and eighth column of the A matrix 411, the element of the fourth row and eighth column of the A matrix A is '1'. Conversely, if the white square b is located in the fifth row and the eighth column of the A matrix 411, the element of the fifth row and eighth column of the A matrix A is '0'.

As shown in the A matrix 411 of FIG. 7, the general parity check matrix 400 according to the RS-LDPC code has a random matrix structure. That is, parity check matrix 400 does not have a particular regularity in the arrangement of elements (whether each of the elements is '0' or '1'). Since all N × N square matrices of parity check matrix 400 have the same random matrix structure as A matrix 411, the decoder using parity check matrix 400 has a very complex hardware configuration and thus The amount of computation required also increases.

FIG. 8 is a diagram specifically illustrating a first sub-matrix 410 of a plurality of sub-matrix of the parity check matrix illustrated in FIG. 7. Referring to FIG. 7, the first sub-matrix 410 illustratively includes six N × N square matrices arranged in series.

According to FIG. 8, the first row 411 of the first sub-matrix 410 has the same matrix structure (or elemental array) as the first row of six N × N square matrices in series. Similarly, the second row 412 of the first sub-matrix 410 has the same matrix structure (or elemental array) as the second row of six N × N square matrices in series. That is, the p-th row of the first sub-matrix 410 has the same matrix structure (or elemental array) as the p-th row of six N × N square matrices in series.

As described with reference to FIG. 7, each row of the first sub-matrix 410 is a binary obtained by converting a code word generated according to a Reed-Solomon (RS) code into a symbol position vector. It has permutation as an element.

Since a method of generating a codeword according to an RS code and converting the generated codeword into a symbol position vector is well known in the art, such a process will be briefly described.

First, a generation polynomial of the RS code is generated using a Galois field. The Galois field is a field with a finite number of elements for which arithmetic operations are defined. The generation polynomial of the Reed-Solomon code may be represented by Equation 1 below.

Here, the coefficient gi of each term of the generated polynomial g (X) is an element in the Galois field. Since the generated polynomial g (X) is the minimum weight sign polynomial, each coefficient gi is not zero.

A codeword set is generated from the generated polynomial g (X). To do this, we first create a generation matrix Gb from the coefficients of the generation polynomial g (X). Since a specific method for generating the generation matrix Gb is well known in the art, a description thereof will be omitted.

If the first row of the generation matrix is r 1 and the second row is r 2, the linear combination of two rows r 1 and r 2 may form a set of codewords. Here, the codeword set generated by the linear combination of two rows r 1 and r 2 may be defined as in Equation 2.

Here, GF (P ^s ) is a Galois field having P ^s elements, P is a prime number, and s is a positive integer. And α and β are primitive elements of the Galois field, respectively.

The codeword set C _b ⁽ⁱ⁾ shown in Equation 2 is called a coset, and all code words constituting one corset have an independent relationship.

The codewords of the codeword set are converted into symbol position vectors to generate binary permutations. Each of the generated binary permutations constitutes each row of the parity check matrix according to the RS-LDPC code. Since a method of generating each row of the parity check matrix according to the RS-LDPC code is well known in the art, a detailed description thereof will be omitted.

The two rows of the parity check matrix H generated as described above become 1 at the same time only at one position, and thus do not have a cycle of length 4, and the size of the girth is at least 6 or more. Therefore, the RS-LDPC code has better error correction performance than the general LDPC code. On the other hand, since each row of the parity check matrix H generated according to the RS code has independent and arbitrary element structures, the matrix structure of the parity check matrix H becomes very complicated.

Referring to FIG. 8, a matrix structure of the first sub matrix 410 is shown. Each row of the first sub-matrix 410 has an element structure independent of each other (for example, the arrangement order of elements '0' and '1' of each row), so that the entirety of the first sub-matrix 410 Matrix structures are also complex and arbitrary.

9 to 11 illustrate a parity check matrix proposed according to the present invention. 9 shows a method of generating the first sub-matrix 510 of the proposed parity check matrix 500. 10 illustrates a matrix structure of the first sub-matrix 510 of the proposed parity check matrix 500. 11 illustrates a method of generating the remaining sub-matrix of the parity check matrix 500 using the first sub-matrix 510.

Referring to FIG. 9, first, a first row 511 of the first sub-matrix 510 is generated according to an RS code. That is, a binary permutation obtained by converting one of code words generated according to an RS code into a symbol position vector is determined as the first row 511 of the first sub-matrix 510. The specific method of generating the first row 511 according to the RS code is the same as described above.

When the first row 511 is generated, the first row 511 is sequentially cyclically shifted to generate the parity check matrix proposed in the present invention, and the remaining rows of the first sub-matrix 510 are generated. Create them. At this time, the first row 511 is cyclically shifted by a period of N sequentially by 1 to form the second row 512 to the Nth row 514. In this case, N is the number of elements of the Galois field used to generate the codeword according to the RS code.

Specifically, the second row 512 is generated by cyclically shifting the first row 511 by one in the row direction. Then, the second row 512 is cyclically shifted by one in the row direction to generate the third row 513.

In this manner, a k + 1th row is generated by cyclically shifting the kth row by 1 in the row direction (where k is an integer of 1 or more and N-1 or less). At this time, since each row is cyclically shifted with N as a period, the Nth column, the 2Nth column,... , the elements of the p · Nth column are each the first column of the k + 1th row, the N + 1th column,. , (p-1) -N + 1th column.

Meanwhile, as shown in FIG. 9, it is assumed that the first sub-matrix 510 includes six N × N square matrices arranged in series, and the first sub-matrix 510 has 6 · N columns. However, since the first sub-matrix 510 is a matrix generated by converting codewords according to RS codes, each N × N square matrix of the first sub-matrix 510 has only one element in one row. It has a value of '1'.

In this case, since each row of the first sub-matrix 510 is cyclically shifted from each other in a cyclic period, each of the N × N square matrices constitutes one circular node. Thus, the last element (or Nth element) of the kth row of the N × N square matrix becomes the first element of the k + 1st row of the N × N square matrix.

That is, for each N × N square matrices, the first through N−1th elements of the kth row are shifted to the second through Nth elements of the k + 1st row, respectively, and the kth row, which is the end of the loop node. The Nth element of is cyclically shifted to become the first element of the next row (ie, the k + 1th row).

For example, the first row of the third N × N square matrix 510a of the first sub-matrix 510 has an N−1 th element of '1'. Since the second row is a cyclic shift of the first row, the N-1th element of the first row becomes the Nth element of the second row. Thus, the second row has the Nth element of '1'. Since the third row is a cyclic shift of the second row and the cyclic period is N, the Nth element of the second row becomes the first element of the third row. Thus, the third row has the first element '1'.

Similarly, the first row of the sixth N × N square matrix 510b of the first submatrix 510 has an Nth element of '1'. Since the second row is a cyclic shift of the first row, the Nth element of the first row becomes the first element of the second row. Thus, the second row has the first element '1'.

In the same manner as above, each row of the first sub-matrix 510 is sequentially cyclically shifted by 1 (the cycle period is N) to generate the second to Nth rows of the first sub-matrix 510. When the generated N rows are arranged in parallel, the first sub-matrix 510 is completed. In this case, the N × N square matrices of the completed first sub-matrix 510 each have a circular structure that circulates row by row, and the first sub-matrix 510 has a quasi-cyclic cycle that includes a plurality of circulating N × N square matrices. It has a (Quasi-Cyclic) matrix structure.

FIG. 10 is a diagram illustrating a first sub-matrix generated according to the method described with reference to FIG. 9. Referring to FIG. 10, each row of the first sub-matrix 510 is generated by cyclically shifting adjacent rows by one (circulation period N). That is, the second row 512 of the first sub-matrix 510 is the result of the cyclic shift of the first row 512, and the third row 513 is the result of the cyclic shift of the second row 512. In this manner, the first sub-matrix 510 is completed by cyclically shifting each row to the eighth row 514.

Referring to FIG. 10, the first sub-matrix 510 generated as described above has a quasi-cyclic matrix structure. Thus, when compared with the structure of the first sub-matrix 410 of FIG. 8, the first sub-matrix 510 according to the present invention has a considerably simplified and aligned matrix structure.

Meanwhile, although an example in which adjacent rows are generated by cyclically shifting each row by one to generate the first sub-matrix 510 has been described, the present invention is not limited thereto. For example, adjacent rows may be generated by cyclically shifting each row of the first sub-matrix 510 by a predetermined size greater than one. In this case, the matrix structure of the first sub-matrix 510 may be different from the above-described embodiment, but the position change of '1' between adjacent rows of the first sub-matrix 510 still has a regularity. Therefore, since the parity check matrix has a simplified structure, the hardware complexity and the amount of computation of the ECC decoder 300 (see FIG. 1) can be reduced.

11 illustrates a method of completing the parity check matrix 500 using the first sub-matrix 510. Referring to FIG. 11, the parity check matrix 500 includes a plurality of sub matrices including first to third sub matrices 510, 520, and 530.

In FIG. 11, the first sub-matrix 510 is generated by the method described with reference to FIGS. 9 to 10. That is, the first sub-matrix 510 may be generated by sequentially performing a method of cyclically shifting one row of the first sub-matrix 510 to generate the next row.

In this embodiment, as shown in FIG. 11, the second sub-matrix 520 adjacent to the first sub-matrix 510 is generated by cyclically shifting the first sub-matrix 510 in block units. The second sub-matrix 520 is cyclically shifted in block units to generate a third sub-matrix 530 adjacent to the second sub-matrix 520. Similarly, the k-th sub-matrix is cyclically shifted block by block to generate a k + 1-th sub-matrix (where k is an integer of 1 or more). As such, when all sub-matrixes of the parity check matrix 500 are generated through a cyclic shift in blocks, the parity check matrix 500 is completed by combining the generated sub-matrixes in parallel. In this case, the block as the cyclic shift unit may be an N × N square matrix described with reference to FIGS. 9 to 10.

For example, it is assumed that the first sub-matrix 510 of the parity check matrix 500 is an N × M matrix including six blocks (or N × N square matrices) as shown in FIG. 11. In this case, the six blocks A, B, C, D, E, and F are sequentially arranged in series to form the first sub matrix 510. A detailed method of generating the first sub matrix 510 is the same as described with reference to FIGS. 9 to 10. The second sub-matrix 520 is generated by cyclically shifting the first sub-matrix 510 in block units. In this case, the cycle period of the first sub-matrix 510 is 6 blocks (or M columns).

Specifically, the first block A of the first sub-matrix 510 is shifted to become the second block A of the second sub-matrix 520 by the cyclic shift in block units. The second block B of the first sub-matrix 510 is shifted to become the third block B of the second sub-matrix 520. Similarly, the n-th block of the first sub-matrix 510 is shifted to become the n + 1-th block of the second sub-matrix 520 (where n is an integer of 1 or more and 5 or less). The last block F of the first sub-matrix 510 is shifted to become the first block F of the second sub-matrix 520. That is, the block F located at the end of the cyclic period is shifted to the beginning of the cyclic period by a cyclic shift in blocks. As described above, the second sub-matrix 520 generated by the cyclic shift of the first sub-matrix 510 in block units may include a matrix in which the first sub-matrix 510 is cyclically shifted by N in the row direction according to the cyclic period M; You will have the same array of elements. That is, when the first sub-matrix 510 is an N × M matrix, one block shift is substantially equal to N column shifts.

Likewise, the third sub-matrix 530 is generated by cyclically shifting the second sub-matrix 520 in units of blocks. In this way, the k-th sub-matrix is cyclically shifted in block units to generate a k + 1-th sub-matrix, and the parity check matrix 500 is completed by arranging the generated sub-matrices in parallel. In an embodiment, the parity check matrix 500 may be stored in the storage device 100 (see FIG. 1) of the semiconductor memory system 1000 (see FIG. 1). Alternatively, the parity check matrix 500 may be stored in a separate storage unit (not shown) included in the controller 200 (see FIG. 1). The stored parity check matrix 500 may be called and used for decoding the read data RD (see FIG. 1).

According to the above configuration, the parity check matrix 500 has a block circulation in sub-matrix units, and each block has a quasi-cyclic matrix structure. Therefore, the parity check matrix 500 proposed in the present invention has a very simplified matrix structure, compared to the conventional random and complicated parity check matrix. Therefore, the amount of computation required for RS-LDPC decoding is reduced, and the overall hardware complexity, including the network configuration connecting the check node and the variable node, can be greatly reduced.

12 is a flowchart illustrating a method of generating the parity check matrix 500 proposed by the present invention. Referring to FIG. 12, the method of generating the parity check matrix 500 includes steps S210 to S250.

In operation S210, the codeword of the RS code is converted into a symbol position vector to generate a first row 511 (see FIG. 9) of the first sub-matrix 510 (see FIG. 9). The specific method of generating the first row 511 from the codeword of the RS code is as described above.

In step S220, the first row 511 is cyclically shifted by one to generate a second row 512. Then, the second row 512 is cyclically shifted by one to generate a third row 513. In the same way, until the N rows are generated, the generated rows are cyclically shifted by one to produce the next row. Specific methods for cyclically shifting each row are the same as described with reference to FIGS. 9 to 10.

In operation S230, the generated rows are arranged in parallel to generate a first sub-matrix 510.

In operation S240, the first sub-matrix 510 is cyclically shifted by one block in block units to generate the second sub-matrix 520. The second sub-matrix 520 is cyclically shifted by one block in block units to generate the third sub-matrix 530. In the same manner, the next sub-matrix is generated by cyclically shifting the generated sub-matrix by one block until all the sub-matrixes necessary to complete the parity check matrix 500 are generated.

In operation S250, the generated sub-matrices are arranged in parallel to complete the parity check matrix 500.

On the other hand, although generating the first row 511 from the codeword of the RS code is illustrated here, the present invention is not limited thereto. For example, a third row 513 may be generated from a codeword of an RS code, and the remaining rows of the first sub-matrix 511 may be generated by sequentially cyclically shifting the third row 513. Even in such a case, the first sub-matrix 511 has a quasi-cyclic matrix structure does not change.

In addition, although each row of the first sub-matrix 511 is illustrated as being generated by cyclically shifting adjacent rows by one, each row of the first sub-matrix 511 according to the present invention is a predetermined value of two or more adjacent rows. Can be generated by cyclic shift by magnitude. For example, the p-th row is cyclically shifted by 2 to generate a p + 1 th row (where p is an integer of 1 or more and N-1 or less), and the generated rows are arranged in parallel to form a first sub-matrix (511). ) Can be created.

In this example, the sub-matrix is cyclically shifted by one block to generate an adjacent sub-matrix. However, each sub-matrix of the parity check matrix 500 according to the present invention blocks the adjacent sub-matrix by two or more blocks. Can be generated. For example, the q-th sub-matrix is circulated by 2 blocks to generate a q + 1-th row (where q is an integer of 1 or more), and the parity check matrix 500 is generated by arranging the generated sub-matrices in parallel. can do.

According to the above configuration, the parity check matrix 500 described with reference to FIGS. 9 to 11 may be generated.

13 is a diagram exemplarily illustrating a parity check matrix according to the present invention. Referring to FIG. 13, a matrix structure of a parity check matrix 600 and a block 610 including a plurality of sub-matrices composed of a plurality of blocks is exemplarily illustrated.

Referring to FIG. 13, the parity check matrix 600 includes six sub matrices arranged in parallel along the column direction. Each sub-matrix includes 28 blocks arranged in series along the row direction. The sub matrices of the parity check matrix 600 are sequentially block-blocked with each other. For example, the kth block of the pth submatrix of the parity check matrix 600 is the same as the k + 1th block of the p + 1th submatrix, where p is an integer of 1 or more and 6 or less, and k is 1 An integer greater than or equal to 27). However, since the sub-matrices of the parity check matrix 600 block circulate with each other using the number of blocks included in one sub-matrix as a cyclic period, the 28th block of the p-th submatrix is the first matrix of the p + 1th sub-matrix. same. As such, the parity check matrix 600 has a simple matrix structure in which the same blocks are arranged with constant regularity. Therefore, the parity check matrix 600 can be easily derived from the matrix structure of one sub-matrix.

Referring again to FIG. 13, a matrix structure of blocks included in the parity check matrix 600 is illustrated by way of example. Since each row of the parity check matrix 600 is generated based on a codeword of an RS code, each block of the parity check matrix 600 has one '1' as one element in one row. That is, if the element of the fifth column of a row of a block is '1', all elements except the element of the fifth column of the row are '0'. 9 to 10, each block of the parity check matrix 600 has a matrix structure that circulates row by row. On the other hand, the number written in each block of the parity check matrix 600 indicates the number of elements of the first row of each block is '1'. For example, if the number written in the block is 40, the first row of the block means that the 40th element is '1' and the remaining elements are '0'.

Specifically, the ninth block 610 of the first sub-matrix of the parity check matrix 600 will be described as an example. At the bottom of FIG. 13, the matrix structure of block 610 is specifically illustrated. In block 610, the number 11 is written. Thus, the first row of block 610 has an eleventh element '1' and the remaining elements are '0'. In addition, the block 610 has a structure of circulating one by one in units of rows. That is, the j th element of the i th row of the block 610 and the j + 1 th element of the i + 1 th row are the same. However, as described above, the last element of the i th row of the block 610 becomes identical to the first element of the i + 1 th row.

A detailed matrix structure of such a block 610 is shown in FIG. Referring to FIG. 13, the eleventh element of the first row of the block 610 is '1' and the remaining elements of the first row are '0'. In the second row of block 610, the first row is cyclically shifted in the row direction by one. Thus, the 12th element of the second row is '1' and the remaining elements of the second row are '0'. In this same manner, all rows of block 610 are organized.

14 is a block diagram illustrating the decoder of FIG. 3 according to an embodiment of the present invention. Referring to FIG. 14, the decoder 330 includes a variable node block 331, a check node block 333, a correction data manager 335, a syndrome checker 336, and switch networks 332 and 334. In the present embodiment, the decoder 330 performs RS-LDPC decoding using the parity check matrix 500 (see FIG. 11) proposed in FIGS. 9 to 13.

In the RS-LDPC decoding, a nonzero element of the parity check matrix 500 means that a corresponding variable node and a check node are connected to each other. Then, decoding is performed through data transmitted according to the connection of the variable node and the check node.

First, when the read data RD received by the read data manager 310 is transmitted to the likelihood value mapper 320, the likelihood value mapper 320 decodes a likelihood value corresponding to the transmitted read data RD. Provided at 330.

The variable node block 331 stores the provided likelihood value and provides the stored likelihood value to the test node block 333 through the first switch network 332 as a variable node message.

The check node block 331 compares the values of the variable nodes for each check node with reference to the provided variable node message, and provides the first and second minimum values as check node messages CHK. Here, the first minimum value means the smallest value among the compared variable node values, and the second minimum value means the second smallest value among the compared variable node values. The check node message CHK is provided to the variable node block 331 via the second switch network 334.

The variable node block 331 updates the variable node and check node values with reference to the received check node message CHK. Then, decoding is performed according to the updated variable node and check node values. The decoded result is provided to the correction data manager 335 as decoded data.

The correction data manager 335 stores the decoding result performed in the variable node block 331, and outputs the decoded data (CD) or the read error message (Err) to the outside according to the determination of whether the syndrome checker 336 succeeds in decoding. do.

The syndrome checker 336 determines whether the decoding is successful according to the decoded data stored in the correction data manager 335. For example, the syndrome checker 336 multiplies the decoded data by the transpose matrix of the parity check matrix 500, and determines whether the decoding is successful (or whether all errors are corrected) according to whether the multiplication result is zero or not. . The determination result of whether the decoding succeeded or not is provided to the correction data management 335.

In an embodiment, if the decoding fails, the syndrome checker 336 may provide a control message for the execution of the new decoding loop to the variable node block 331 or the first switch network 332. At this time, in the new decoding loop, the variable node block 331 provides updated variable node values to the check node block 331 as variable node messages in response to the control message. The check node block 331 then provides the new check node message to the variable node block 331 with reference to the provided variable node message. Then, the variable node block 331 updates the variable node and check node values with reference to the new check node message, and performs decoding according to the updated variable node and check node values. Then, the syndrome checker 336 determines whether the decoding is successful according to the decoding result, and decoding is terminated or a new decoding loop is repeatedly executed according to the determination result of the syndrome checker 336.

The first and second switch networks 332, 334 relay the data exchange between the variable node block 331 and the check node block 333. Specifically, the first switch network 332 transfers the variable node message provided from the variable node block 331 to the check node block 333. The second switch network 334 forwards the check node message provided from the check node block 333 to the variable node block 331.

In the decoder 330 according to the present invention, the parity check matrix 500 has a very regular and simple structure. Therefore, the connection between variable nodes and check nodes is also very simple and regular. Accordingly, the first and second switch networks 332 and 334 can be easily implemented through a plurality of hard-wired switches or parallel shifters. Details of the first and second switch networks 332 and 334 will be described later in conjunction with FIGS. 15 and 16.

According to the above configuration, the connection relationship between the variable nodes and the check nodes is simplified by using the parity check matrix 500 having a simple structure. Thus, the amount of computation and the memory required for the data exchange between the variable nodes and the check nodes are reduced. In addition, since the switch networks 332 and 334 relaying the variable node block 331 and the check node block 333 can be implemented with a simple hardware structure, the hardware complexity and hardware area of the decoder 330 can be reduced. .

Meanwhile, since the general contents of the decoder 330 and RS-LDPC decoding, which are not described herein, are well known in the art, a description thereof will be omitted.

FIG. 15 is a block diagram illustrating an exemplary switch network shown in FIG. 14. In FIG. 15, a detailed block diagram of the first switch network 332 (see FIG. 14) is shown. Meanwhile, since the second switch network 334 (see FIG. 14) has substantially the same configuration as the first switch network 332, the description of the second switch network 334 is omitted in this embodiment.

Referring to FIG. 15, the first switch network 332 includes a switch controller 332a and a connection unit 332b.

The switch controller 332a receives the variable node message from the variable node block 331 and allocates the variable node message to the corresponding channel among the plurality of channels in response to the clock signal. The channel to which the variable node message is allocated may vary depending on the clock signal. In an embodiment, the switch controller 310 may include a clock counter 332c for generating a clock signal.

The connection part 332b includes a plurality of fixed wiring blocks 10, 20, 30, 40, and 50. Each of the fixed wiring blocks 10, 20, 30, 40, and 50 receives a variable node message through a channel connected to the switch controller 332a. The fixed wiring blocks 10, 20, 30, 40, and 50 output the received variable node message to a predetermined output path through the fixed wiring.

In this case, each of the fixed wiring blocks 10, 20, 30, 40, and 50 may correspond to any one of the N × N square matrices included in the first sub-matrix 510 (see FIG. 10). The terminals are connected. For example, in the first fixed wiring block 10, input terminals and output terminals may be connected to correspond to an N × N square matrix A (see FIG. 10). Alternatively, input terminals and output terminals may be connected to the second fixed wiring block 30 so as to correspond to an N × N square matrix C (see FIG. 10). The specific configuration of the fixed wiring blocks 10 and 30 and the corresponding relationship with the N × N square matrices A and C will be described later with reference to FIGS. 16 and 17.

Meanwhile, the first switch network 332 may include only the fixed wiring blocks corresponding to the first sub-matrix 510 at the connection unit 332b and may relay data transmission corresponding to the entire parity check matrix 500. .

For example, when the clock signal represents the first sub-matrix 510, the switch controller 332b outputs the variable node message corresponding to the first sub-matrix 510 to the fixed wiring blocks 10, 20, 30, and 40. , Then 50). When the clock signal represents the second sub-matrix 520 (see FIG. 10), the switch control unit 332b shifts the channel to which the variable node message is allocated by one block, starting from the second fixed wiring block 20 in order. Allocate a variable node message. The first fixed wiring block 10 is assigned the last portion of the variable node message. Each sub-matrix of the parity check matrix 500 has a matrix structure that is block-circulated with each other. Thus, through this very simple operation of simply shifting the channel that allocates the variable node message in accordance with the clock signal, the entire variable nodes can be connected to the check nodes. Thus, the amount of computation and the memory required to connect the variable nodes and the check nodes are reduced. In addition, since the switch network is implemented using the minimum fixed wiring blocks, the hardware complexity and hardware area of the decoder 330 (see FIG. 14) may be minimized.

16 and 17 exemplarily illustrate fixed wiring blocks of a switch network according to the present invention.

FIG. 16 shows the input-output connection relationship of the first fixed wiring block 10 (see FIG. 15). FIG. 17 shows the input-output connection relationship of the third fixed wiring block 30 (see FIG. 15). It is assumed that the first and third fixed wiring blocks 10 and 30 each have an input-output connection relationship corresponding to an N × N square matrix (A, C, see FIG. 10).

Referring to FIG. 16, the connection relationship between the N × N square matrix A and the first fixed wiring block 10 is shown. In the N × N square matrix A, the elements of the first row and the first column are '1' and the remaining elements of the first row are '0'. In the parity check matrix 500 (see FIG. 10) according to the present invention, the N × N square matrix A has a matrix structure circulating in units of rows. Therefore, in the N × N square matrix A, the element of the i th row i column is '1' (where i is an integer less than or equal to N), and the remaining elements are '0'.

The element '1' in the parity check matrix 500 means that the corresponding variable node and the check node are connected to each other. On the other hand, the element '0' in the parity check matrix 500 means that the corresponding variable node and the check node are not connected to each other. Accordingly, according to the N × N square matrix A, the variable node terminals A1, A2, A3, A4, A5, A6, A7, and A8 of the first fixed wiring block 10 are connected to the test node terminals B1. , B2, B3, B4, B5, B6, B7, and B8 are fixedly connected in order.

At this time, if the clock signal represents the first sub-matrix 510 (see FIG. 10), the switch controller 332a will allocate the first portion of the input variable node message to the channel to be connected to the first fixed wiring block 10. . Here, the first portion of the variable node message refers to variable node values generated from variable nodes corresponding to the first N × N square matrix A of the first sub-matrix 510.

In this case, when the clock signal represents the second sub-matrix 520 (see FIG. 10), the switch controller 332a allocates the second portion of the input variable node message to the channel to be connected to the first fixed wiring block 10. something to do. Here, the second portion of the variable node message refers to variable node values generated from variable nodes corresponding to the second N × N square matrix A of the second sub-matrix 520. The variable node-check node concatenation of the second N × N square matrix A of the second sub-matrix 520 is the variable node-check of the first N × N square matrix A of the first sub-matrix 510. It has the same regularity as the node connection relationship. Therefore, even if the sub-matrix corresponding to the input variable node message is changed through the channel shift as described above, the variable node message is correctly assigned to the corresponding check node.

Referring to FIG. 17, the connection relationship between the N × N square matrix C and the first fixed wiring block 30 is shown. In the N × N square matrix C, the elements of the first row and the seventh column are '1' and the remaining elements of the first row are '0'. In the parity check matrix 500 (see FIG. 10) according to the present invention, the N × N square matrix C has a matrix structure circulating in units of rows. Accordingly, the N × N square matrix C is cyclically shifted by one in units of rows similarly to the N × N square matrix A. FIG.

Accordingly, according to the N × N square matrix C, the variable node terminals A1, A2, A3, A4, A5, A6, A7, and A8 of the third fixed wiring block 30 are connected to the test node terminals B3. , B4, B5, B6, B7, B8, B1, and B2 are fixedly connected in order.

At this time, if the clock signal represents the first sub-matrix 510 (see FIG. 10), the switch controller 332a will allocate a third portion of the input variable node message to the channel to be connected to the third fixed wiring block 30. . Here, the third portion of the variable node message refers to variable node values generated from variable nodes corresponding to the third N × N square matrix C of the first sub-matrix 510.

In this case, when the clock signal represents the second sub-matrix 520 (see FIG. 10), the switch controller 332a allocates the fourth portion of the input variable node message to the channel to be connected to the third fixed wiring block 30. something to do. Here, the fourth part of the variable node message refers to variable node values generated from variable nodes corresponding to the fourth N × N square matrix C of the second sub-matrix 520. As such, the first switch network 15 can correctly assign the variable node message to the corresponding check node by shifting the channel connected to the fixed wiring block.

Adjacent sub-matrices of the parity check matrix 500 are in a block-cyclic relationship by one block. Thus, by performing the simple channel shift as above, between all the variable nodes and the check nodes of the parity check matrix 500 through the same fixed wiring blocks 10, 20, 30, 40, 50, see FIG. You can perform the connection.

Here, only the configuration and operation of the first switch network 332 have been described. However, the second switch network 334 also operates substantially the same as the first switch network 332. However, the second switch network 334 receives a check node message from the check node block 333 and outputs the check node message to the variable node block 331.

Meanwhile, only an example of implementing the first and second switch networks 332 using fixed wiring blocks has been described. However, as described above, the first and second switch networks 332 may use a parallel shifter (not shown). Can be implemented.

The parity check matrix 500 of the present invention has a matrix structure in which blocks are circulated for each sub matrix. Accordingly, the parallel shifter relays data transmission between the variable node-checking nodes for the entire parity check matrix 500 by shifting the input / output paths in parallel based on the variable node-checking node connection relationship according to the first sub-block 510. can do.

In an embodiment, the first and second switch networks may include a control unit for controlling the parallel shifter and the parallel shifter. The detailed configuration and operation of the switch network including the parallel shifter is well known in the art, so a description thereof will be omitted.

18 is a block diagram illustrating an application example of the semiconductor memory system 1000 shown in FIG. 1. Referring to FIG. 18, the semiconductor memory system 2000 may include a storage device 2100 and a controller 2200. The storage device 2100 includes a plurality of storage chips. The plurality of storage chips are divided into a plurality of groups 2100a, 2100b, and 2100c.

The plurality of storage chips are configured to communicate with the controller 2200 through one common channel for each group. In exemplary embodiments, the plurality of storage chips may communicate with the controller 2200 through a plurality of channels respectively assigned to the plurality of groups.

The controller 2200 includes a plurality of ECC decoders ECC1, ECC2, and ECCn having the same configuration as the EEC decoder 300 described in FIG. 3. The ECC decoders ECC1, ECC2, and ECCn correct errors of data read from the storage device 2100.

The ECC decoders ECC1, ECC2, and ECCn are provided to correspond to the number of channels connecting the controller 2200 and the storage device 2100. One ECC decoder corrects errors of storage chips connected to one channel.

In the present embodiment, the ECC decoders ECC1, ECC2, and ECCn perform RS-LDPC decoding on data read from the storage device 2100. The ECC decoders ECC1, ECC2, and ECCn transmit data between the variable nodes and the check nodes using the parity check matrix 500 (see FIG. 10) described with reference to FIGS. 9 to 13, and read the data. Decode The parity check matrix 500 according to the present invention has a simple matrix structure while maintaining the error correction performance of the RS-LDPC code. Therefore, the memory system 2000 according to the present exemplary embodiment may have high error correction performance and simultaneously reduce hardware complexity of the ECC decoder 300. In addition, the computational throughput of the ECC decoder 300 may be reduced.

In FIG. 18, a plurality of storage chips are connected to one channel. However, the storage system 2000 may be modified such that one storage chip is connected to one channel.

19 illustrates a memory card 3000 according to an embodiment of the present invention. Referring to FIG. 19, the memory card 3000 may include a storage device 3100 and a controller 3200. The storage device 3100 may be a nonvolatile memory device including a flash memory.

The controller 3200 includes the same ECC decoder 3300 as described in FIG. 3. The ECC decoder 3300 corrects an error of data read from the storage device 3100.

As described above, the ECC decoder 3300 transmits data between the variable nodes and the check nodes and decodes the read data using the parity check matrix 500 (see FIG. 10) having a simplified structure. The parity check matrix 500 according to the present invention has a simple matrix structure while maintaining the error correction performance of the RS-LDPC code. Therefore, the memory card 3000 according to the present exemplary embodiment may have high error correction performance and simultaneously reduce hardware complexity of the ECC decoder 3300. In addition, the computational throughput of the ECC decoder 3300 may also be reduced.

The memory card 3000 may include a personal computer memory card international association (PCMCIA), a compact flash card (CF), a smart media card (SM, SMC), a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), Memory cards such as SD cards (SD, miniSD, microSD, SDHC), universal flash storage (UFS), and the like are constituted.

20 is a block diagram illustrating a solid state drive (SSD) according to an embodiment of the present invention. Referring to FIG. 20, the user device 4000 includes an SSD 4100 and a host 4200. The SSD 4100 includes a nonvolatile memory device 4130, an SSD controller 4110, an ECC decoder 4120, and a buffer memory 4140.

The SSD controller 4110 provides a physical connection between the host 4200 and the SSD 4100. That is, the SSD controller 4110 provides interfacing with the SSD 4100 in response to the bus format of the host 4200. In particular, the SSD controller 4110 decodes an instruction provided from the host 4200. According to the decoded result, the SSD controller 4110 accesses the nonvolatile memory device 4130. The bus format of the host 4200 is Universal Serial Bus (USB), Small Computer System Interface (SCSI), PCI express, ATA, Parallel ATA (PATA), Serial ATA (SATA), and Serial Attached SCSI (SAS). Etc. may be included.

In the buffer memory 4140, write data provided from the host 4200 or data read from the nonvolatile memory device 4130 are temporarily stored. When data present in the nonvolatile memory device 4130 is cached at the read request of the host 4200, the buffer memory 4140 supports a cache function of directly providing the cached data to the host 4200. . In general, the data transfer rate by the bus format (eg, SATA or SAS) of the host 4200 is much faster than the transfer rate of the memory channel of the SSD 4100. That is, when the interface speed of the host 4200 is extremely high, the performance degradation caused by the speed difference may be minimized by providing a large buffer memory 4140.

The buffer memory 4140 may be provided as a synchronous DRAM to provide sufficient buffering in the SSD 4100 used as a large auxiliary storage device. However, it is apparent to those who have acquired common knowledge in the art that the buffer memory 4140 is not limited to the disclosure herein.

The nonvolatile memory device 4130 is provided as a storage medium of the SSD 4100. For example, the nonvolatile memory device 4130 may be provided as a NAND flash memory device having a large storage capacity. The nonvolatile memory device 4130 may be configured of a plurality of memory devices. In this case, each of the memory devices is connected to the SSD controller 4110 in units of channels. Although the case in which the nonvolatile memory device 4130 is a NAND flash memory device has been described as an example, the nonvolatile memory device 4130 may be configured as other nonvolatile memory devices. For example, PRAM, ReRAM, FRAM, MRAM, NOR flash memory, or the like may be used as the storage medium, and a memory system in which heterogeneous memory devices are mixed may be applied.

In the SSD 4100 described above, the SSD controller 4110 includes the same ECC decoder 4120 as the ECC decoder described in FIG. 3. The ECC decoder 4120 corrects an error of data read from the nonvolatile memory device 4130.

As described above, the ECC decoder 4120 transmits data between the variable nodes and the check nodes using the parity check matrix 500 (see FIG. 10) having a simplified structure, and decodes the read data. The parity check matrix 500 according to the present invention has a simple matrix structure while maintaining the error correction performance of the RS-LDPC code. Accordingly, the SSD 4100 according to the present embodiment may have high error correction performance and simultaneously reduce hardware complexity of the ECC decoder 4120. In addition, the computational throughput of the ECC decoder 4120 may also be reduced.

21 is a diagram illustrating a schematic configuration of a semiconductor memory system and a computing system including the same according to an embodiment of the present disclosure. Referring to FIG. 21, a computing system 5000 according to the present invention includes a nonvolatile memory device 5510, a memory controller 5520, a microprocessor 5100, a random access memory 5200, electrically connected to a bus 5600. RAM) and a user interface 5300.

In the computing system 5000 of FIG. 21, the nonvolatile memory device 5510 may be substantially the same device as the nonvolatile memory device 4130 (see FIG. 20) described with reference to FIG. 20. The nonvolatile memory device 5510 may be a NAND flash memory device.

The memory controller 5520 may include the same ECC decoder 5530 as the ECC decoder 300 described with reference to FIG. 3. The ECC decoder 5530 corrects an error read from the nonvolatile memory device 5510. As described above, the ECC decoder 5530 uses the parity check matrix 500 (see FIG. 10) having a simplified structure to transmit data between the variable nodes and the check nodes, and decode the read data. The parity check matrix 500 according to the present invention has a simple matrix structure while maintaining the error correction performance of the RS-LDPC code. Therefore, the semiconductor memory system apparatus 5500 and the computing system 5000 including the same according to the present exemplary embodiment may have high error correction performance and simultaneously reduce hardware complexity of the ECC decoder 5530. In addition, the computational throughput of the ECC decoder 5530 can also be reduced.

When the computing system according to the present invention is a mobile device, a battery 5400 for supplying an operating voltage of the computing system may be additionally provided. Although not shown in the drawings, the computing system according to the present invention may further be provided with an application chipset, a camera image processor (CIS), a mobile DRAM, or the like. The memory controller 6200 and the nonvolatile memory device 6100 may configure, for example, an SSD (Solid State Drive / Disk) that uses a nonvolatile memory to store data.

The nonvolatile memory device and / or memory controller according to the present invention may be mounted using various types of packages. For example, the flash memory device and / or the memory controller according to the present invention may be a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carrier (PLCC), plastic dual in- Line Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP), Small Outline (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP), Wafer-Level Processed Stack Package ( It can be implemented using packages such as WSP).

In the detailed description of the present invention, a specific embodiment has been described, but each embodiment may be modified in various forms without departing from the scope of the present invention. In addition, although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not used to limit the scope of the present invention as defined in the meaning or claims. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be defined by the equivalents of the claims of the present invention as well as the following claims.

Claims (15)

A read data manager configured to store data read from the memory device;
A likelihood value mapping unit configured to output likelihood data by mapping likelihood ratio values to the data output from the read data management unit;
A decoding unit configured to perform low density parity check decoding on the mapping data using a parity check matrix;
The parity check matrix is a (k * N) × M matrix containing k N × M submatrices, where k is an integer greater than or equal to 2, and N and M are each an integer greater than or equal to 3,
One of the k N × M sub-matrixes is a first sub-matrix having an N × M size, and the other of the k N × M sub-matrixes is a second sub-matrix having an N × M size,
The second sub-matrix is located adjacent to the first sub-matrix, and includes an element array identical to the matrix obtained by cyclically shifting the first sub-matrix by N in a row direction according to a cyclic period M,
The first sub-matrix is:
A first row which is a binary permutation of converting a code word generated according to a Reed-Solomon code into a symbol position vector; And
Second to Nth rows consecutively adjacent to the first row;
Each of the second to Nth rows includes an element array identical to a row obtained by sequentially shifting the previous row by one in accordance with a cyclic period N; The method of claim 1,
The decoding unit
A variable node calculator configured to update values of variable nodes and check nodes with reference to a likelihood value or check node message and to decode the data according to the updated values of the variable nodes and check nodes;
A check node calculator which receives the updated values of the variable nodes as a variable node message and provides the check node message with reference to the received variable node message;
A first network portion configured to relay transmission of the variable node message from a variable node block to a check node block;
And a second network portion configured to relay transmission of the check node message from the check node block to the variable node block. The method of claim 2,
The first or second network portion is:
A switch controller configured to assign at least a portion of the variable node message input from the variable node block to any one of a plurality of channels; And
And a connection unit including a fixed wiring block to fix the plurality of input terminals connected to the one channel to the plurality of output terminals. The method of claim 3, wherein
And the switch controller is configured to allocate another portion of the variable node message to the one channel in place of at least a portion of the variable node message according to a clock signal. The method of claim 2,
The first network portion or the second network portion
A parallel shifter configured to divide and assign the variable node message to the check nodes according to the parity check matrix; And
And a shifter controller configured to control an operation of the parallel shifter. The method of claim 1,
Wherein N is the number of elements of a Galois field used to generate the code word according to a Reed-Solomon code. The method of claim 1,
And a syndrome check unit configured to determine an error correction state based on the low density parity check decoding. The method of claim 7, wherein
According to the determination result of the error correction state,
The decoding unit outputs a fail message,
The read data management unit stores additional data read from the memory device in response to the fail message,
The likelihood value mapping unit maps the likelihood values to the additional data to output additional mapping data,
And the decoding unit performs a low density parity check on the additional mapping data using the parity check matrix. The method of claim 8,
And a read voltage for reading the data and a read voltage for reading the additional data are different. The method of claim 1,
And a storage configured to store the parity check matrix. The method of claim 1,
The memory device includes a NAND flash memory. The method of claim 1,
The memory device includes a nonvolatile memory,
And the read data management unit, the likelihood value mapping unit, and the decoding unit constitute an error correction code (ECC) decoder of a memory controller of the semiconductor memory system. In the data reading method of a semiconductor memory system,
Reading data stored in the semiconductor memory system using first read voltages;
Performing low density parity check decoding on the read data using a parity check matrix; And
Outputting a result of correcting an error of the read data according to a result of the low density parity check decoding;
The parity check matrix is a (k * N) × M matrix containing k N × M submatrices, where k is an integer greater than or equal to 2, and N and M are each an integer greater than or equal to 3,
One of the k N × M sub-matrixes is a first sub-matrix having an N × M size, and the other of the k N × M sub-matrixes is a second sub-matrix having an N × M size,
The second sub-matrix is located adjacent to the first sub-matrix, and includes an element array identical to the matrix obtained by cyclically shifting the first sub-matrix by N in a row direction according to a cyclic period M,
The first sub-matrix is:
A first row which is a binary permutation of converting a code word generated according to a Reed-Solomon code into a symbol position vector; And
Second to Nth rows consecutively adjacent to the first row;
Each of the second to Nth rows includes the same element array as the row obtained by sequentially shifting the previous row by one according to a cyclic period N. The method of claim 13,
Rereading the stored data using a second read voltage different from a first read voltage according to a result of the low density parity check decoding; And
And performing low density parity check decoding on the read back data using the parity check matrix. The method of claim 13,
And said data is read from a NAND flash memory of said semiconductor memory system.

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