KR101877427B1 - Semiconductor device - Google Patents

Abstract

A semiconductor element according to an embodiment of the present invention includes a substrate, a semiconductor layer on the substrate, first and second electrodes which are ohmic-contacted on the semiconductor layer and are spaced apart from each other, And a third electrode adjacent to the electrode and including a second surface opposite to the first surface and adjacent to the second electrode, wherein the third electrode is arranged on the first surface line in the first electrode direction The protrusion being formed by the protrusion.

Description

Semiconductor device

Embodiments relate to semiconductor devices.

In addition to the information society, communication technologies for high-speed, large-capacity signal transmission are rapidly developing. For this purpose, research on electronic devices for wireless communication has been actively conducted and excellent research results have been reported. GaN-based compound semiconductors with excellent physical properties are attracting attention as materials for next-generation high-frequency and high-output electronic devices and are being actively studied worldwide.

Of the GaN-based electronic devices, heterojunction structure field effect transistors using an AlGaN / GaN heterojunction structure are mostly studied and their performance is also excellent.

Since GaN has an excellent breakdown field of about 4 MV / cm, a high RF output can be obtained when the drain operating voltage is increased.

High frequency, high power HFETs under high drain operating voltages must have good gate junctions. Much research is underway to form thermally and chemically stable gate junctions with high breakdown voltage and low leakage current.

Embodiments provide a semiconductor device that is easy to reduce the breakdown voltage and the operation resistance by being spaced apart from each other by a first and a second distance between the gate electrode and the drain electrode.

A semiconductor device according to an embodiment includes a substrate, a semiconductor layer on the substrate, first and second electrodes which are in ohmic contact with each other on the semiconductor layer and are disposed on the semiconductor layer, And a third electrode facing the first surface and having a second surface adjacent to the second electrode, wherein the third electrode has protrusions formed on the first surface line toward the first electrode can do.

The semiconductor device according to the embodiment includes the first and second regions of the gate electrode and is spaced apart from the first and second regions by the first and second distances between the adjacent drain electrodes, the E-field formed at the lower portion of the dege is extended to lower the peak field, thereby enlarging the depletion region in the semiconductor layer.

Further, in the semiconductor device according to the embodiment, the breakdown voltage is lowered due to the enlargement of the depletion region, and the operation resistance can be reduced.

1 is a perspective view showing a semiconductor device according to a first embodiment.
2 is a perspective view showing a semiconductor device according to the second embodiment.
FIG. 3 is a cross-sectional view of the semiconductor device shown in FIG. 1 taken along the line P1-P1 and the line P2-P2, and is a graph showing an electric field during power application.
4 is a perspective view showing a semiconductor device according to the third embodiment.
FIG. 5 is a cross-sectional view of the semiconductor device shown in FIG. 4 taken along the lines P3-P3 and P4-P4, and is a graph showing an electric field during power application.

In the description of the present embodiment, in the case where one element is described as being formed "on or under" of another element, the upper (upper) or lower (lower) on or under includes both the two elements being directly contacted with each other or one or more other elements being indirectly formed between the two elements. Also, when expressed as "on or under", it may include not only an upward direction but also a downward direction with respect to one element.

In the drawings, the thickness and size of each layer are exaggerated, omitted, or schematically illustrated for convenience and clarity. Therefore, the size of each component does not entirely reflect the actual size.

Further, the angles and directions mentioned in the description of the structure of the semiconductor device in this specification are based on those described in the drawings. In the description of the structure of the semiconductor device in the specification, reference points and positional relationship with respect to angles are not explicitly referred to, refer to the related drawings.

FIG. 1 is a perspective view showing a semiconductor device according to a first embodiment, and FIG. 2 is a perspective view showing a semiconductor device according to a second embodiment.

1 and 2, a semiconductor device 100 includes a substrate 10, first and second electrodes D and D disposed on the semiconductor layer 20 and the semiconductor layer 20 on the substrate 10, S and the semiconductor layer 20 and may include a third electrode G between the first and second electrodes D and S. [

The substrate 10 may be formed of any one of, for example, sapphire (Al ₂ O ₃ ), SiC, Si, GaAs, GaN, ZnO, Si, GaP, InP, Ge, Ga ₂ O _3, But is not limited thereto.

In addition, the substrate 10 can be made of a material capable of facilitating the release of heat and improving the thermal stability.

On the substrate 10, a buffer layer 12 using compound semiconductors of Group 2-Group 6 or Group 3-Group 5 elements may be disposed.

Here, the buffer layer 12 relaxes the lattice mismatch between the substrate 10 and the semiconductor layer 20, and can easily grow a plurality of semiconductor layers.

The buffer layer 12 can be grown as a single crystal on the substrate 10 and the buffer layer 12 grown with a single crystal can improve the crystallinity of the semiconductor layer 20 grown on the buffer layer 12

The buffer layer 12 may be formed of, for example, an AlInN / GaN laminated structure including AlN and GaN, an InGaN / GaN laminated structure, and a laminated structure of AlInGaN / InGaN / GaN.

The semiconductor layer 20 is made of a nitride semiconductor material and has advantages such as an energy bandgap higher than Si, GaAs, and InP materials, a high breakdown voltage, a high saturation rate of electrons, and excellent thermal characteristics It is very easily applied to a high output amplifier operating in the microwave frequency range.

The semiconductor layer 20 according to the embodiment may have a Wurtzite structure including an undoped GaN layer 22 doped with no dopant and an AlGaN layer 24 on the GaN layer 22.

That is, the semiconductor layer 20 having the wurtzite structure is formed in the piezoelectric polarization effect generated at the junction between the GaN layer 22 and the AlGaN layer 24, High density electrons can be induced in the subband of the quantum well formed in the junction plane between the GaN layer 22 and the AlGaN layer 24 by spontaneous polarization.

The electron gas gathering in the quantum well is bound to the bottom of the quantum well on the growth axis, but is free to move on a plane perpendicular to the growth axis, so that quasi two dimensional free electron gas can be formed.

Accordingly, the GaN layer 22 serves as a channel layer, and the AlGaN layer 24 serves as a barrier layer to form the quantum well.

The first and second electrodes D and S should form ohmic contacts on the AlGaN layer 24 and may be formed by heat treatment at a high temperature of 600 ° C or higher to obtain a low ohmic contact resistance.

The first and second electrodes D and S may be formed of a conductive material such as aluminum, copper, gold, silver, or other metal material or silicide, for example, in a nitrogen, argon or oxygen atmosphere. And is not limited to this.

The third electrode G should also form a Schottky contact on the AlGaN layer 24 and form a Schottky barrier when formed on, for example, CoSi ₂ , Al, Platinum, or AlGaN layer 24 Or may be formed of other materials to form.

The third electrode G includes a first surface G_s1 adjacent to the first electrode D and a second surface G_s2 facing the first surface G-s1 and adjacent to the second electrode S .

At this time, the third electrode G may be formed with a protrusion Gg in the direction from the first surface G_s1 to the first electrode D.

That is, the first surface G_s1 of the third electrode G is spaced apart from the first electrode D by a first distance d1, and the projection Gg of the third electrode G is spaced apart from the first electrode D And a second distance d2.

Here, the protrusions Gg protrude in the same direction in the direction of the first electrode D and have the same width, but are not limited thereto.

For example, the projections Gg include first and second projections (not shown) adjacent to each other, and the width of the first projections is 1 to 2 times the width of the second projections, The length may be one to two times the length of the second projection.

That is, the protrusion Gg includes a plurality of protrusions, and at least one protrusion of the plurality of protrusions has the same width or length as the protrusions of the other protrusions, thereby making it possible to adjust the distance from the first electrode D, There is an advantage that the amount of charge can be secured.

The second distance d2 may be 0.5 to 0.9 times the first distance d1, but is not limited thereto.

The semiconductor device 100 shown in FIG. 2 may include a dielectric layer 30 between the third electrode G and the AlGaN layer 24.

By adjusting the thickness of the dielectric layer 30, the channel potential can be effectively controlled by the gate voltage, thereby short-channel effect is reduced, gate length scaling is enabled, and the speed of the integrated circuit is improved due to the increase of the driving current .

At this time, the cross-sectional area of the dielectric layer 30 may be 1 to 1.2 times the cross-sectional area of the third electrode G, but is not limited thereto.

FIG. 3 is a cross-sectional view of the semiconductor device shown in FIG. 1 taken along the line P1-P1 and the line P2-P2, and is a graph showing an electric field during power application.

3 (a) is a cross-sectional view of the semiconductor device 100 taken along line P1-P1 shown in FIG. 1, and FIG. 2 (b) is a plan view of the semiconductor device 100 taken along the line P2- Fig.

Here, the third electrode G is separated from the first electrode D by the first and second distances d1 and d2, and the description thereof is omitted in FIG. 1.

(c) is a graph showing a peak current or voltage between the edge of the third electrode G and the edge of the first electrode D when power is applied to the third electrode G .

That is, as shown in (c), the first and second graphs gr1 and gw2 are obtained by multiplying the peak current or voltage between the first and third electrodes D and G shown in (a) and (b) Distance and an electric field.

Here, the first graph gr1 generates a peak current or voltage at the first surface G_s1 and the first electrode D of the third electrode G, and the second graph gr2 represents the peak current or voltage at the third electrode G G of the first electrode D and the protrusion Gg and the first electrode D of the second electrode G are generated.

The peak current or voltage shown in the first and second graphs (gr1, gr2) may have a higher breakdown voltage as the size is lower.

(d) shows a third graph gr3 obtained by synthesizing the first and second graphs gr1 and gr2.

The peak current or voltage of the third graph gr3 is lower than the peak current or voltage of the first and second graphs gr1 and gr2 so that the charge amount Q Q) can be increased and the breakdown voltage can be lowered.

As shown in FIG. 3, by controlling the first and second distances d1 and d2 between the first and third electrodes D and G, it is possible to easily control the voltage or the current, The reliability of the quality of the semiconductor device 100 is improved.

3 is a sectional view of the semiconductor device 100 shown in FIG. 1, but is the same as the cut surface of the semiconductor device 100 shown in FIG. 2, and the dielectric layer 30 may be further formed. Do not.

FIG. 4 is a perspective view showing a semiconductor device according to a third embodiment, FIG. 5 is a cross-sectional view of the semiconductor device shown in FIG. 4 taken along P3-P3 direction and P4-P4 direction, Fig.

4, a semiconductor device 200 includes a substrate 110, first and second electrodes D1 and S1, which are disposed on the semiconductor layer 120 and the semiconductor layer 120 on the substrate 110, And may include a third electrode G1 disposed between the first and second electrodes D1 and S1.

Here, the substrate 110 is, for example, formed with any one of a sapphire (Al ₂ O _3), S1iC, S1i, G1aAS1, G1aN, ZnO, S1i, G1aP, InP, G1e, G1a ₂ 0 ₃ and AlO But is not limited thereto.

In addition, the substrate 110 may be made of a material capable of facilitating the release of heat and improving the thermal stability.

On the substrate 110, a buffer layer 112 using compound semiconductors of Group 2-VI-VI or Group-VI-Group elements may be disposed.

Here, the buffer layer 112 may mitigate lattice mismatch between the substrate 110 and the semiconductor layer 120, and may facilitate the growth of a plurality of semiconductor layers.

The buffer layer 112 can be grown as a single crystal on the substrate 110 and the buffer layer 112 grown with a single crystal can improve the crystallinity of the semiconductor layer 120 grown on the buffer layer 112

In addition, the buffer layer 112 may be formed of a structure such as an AlInN / G1aN laminated structure including AlN and G1aN, an InG1aN / G1aN laminated structure, and a laminated structure of AlInG1aN / InG1aN / G1aN.

The semiconductor layer 120 is made of a nitride semiconductor material and has advantages such as an energy band gap (banD1G1ap) higher than S1i, G1aAS1 and InP materials, a high breakdown voltage (breakD1own voltaG1e), a high saturation rate of electrons and excellent thermal characteristics It is very easily applied to a high output amplifier operating in the microwave frequency range.

The semiconductor layer 120 according to an embodiment may have a Wurtzite structure including an undoped G1aN layer 122 doped with no dopant and an AlGaN layer 124 on the G1aN layer 122. [

That is, the semiconductor layer 120 of the wurtzite structure is formed in the piezoelectric polarization effect generated at the junction between the G1aN layer 122 and the AlGaN layer 124, The high density of electrons can be induced in the quantum well S1bubanD1 formed in the junction plane between the G1aN layer 122 and the AlGaN layer 124 by the spontaneous polarization (S1pontaneouS1 polarization).

The electron gas gathering in the quantum well is bound to the bottom of the quantum well on the growth axis, but is free to move on a plane perpendicular to the growth axis, so that quasi two dimensional free electron gas can be formed.

Accordingly, the G1aN layer 122 serves as a channel layer, and the AlGaN layer 124 serves as a barrier layer to form the quantum well.

The first and second electrodes D1 and S1 must form an ohmic contact on the AlGaN layer 124 and may be formed by heat treatment at a high temperature of 600 ° C or higher to obtain a low ohmic contact resistance.

The first and second electrodes D1 and S1 may be formed of a conductive material such as aluminum, copper, gold, silver, or other metal material or silicide, for example, in a nitrogen, argon or oxygen atmosphere. And is not limited to this.

In addition, the third electrode (G1) are to be formed in the shock key contacts on AlG1aN layer 124, for example, CoS1i _2, aluminum, platinum, or a Schottky barrier when formed on AlG1aN layer 124 Or may be formed of other materials to form.

The third electrode G1 includes a first surface G1_s11 adjacent to the first electrode D1 and a second surface G_s12 opposed to the first surface G-s11 and adjacent to the second electrode S1 .

At this time, the third electrode G1 may have a protrusion Gg1 in the direction of the first electrode D1 from the first surface G_s11, and the first electrode D1 may have a protrusion Gg1 corresponding to the protrusion Gg1, (Dd1) may be formed.

That is, the first surface G_s11 of the third electrode G1 is spaced apart from the corresponding protrusion Dd1 of the first electrode D1 by a first distance d11, and the protrusion Gg1 of the third electrode G1 May be spaced apart from the corresponding protrusion Dd1 of the first electrode D1 by a second distance d12.

Here, the protrusions Gg1 protrude in the same direction in the direction of the first electrode D1 and have the same width, and the protrusion Dd1 may be symmetrical with respect to the protrusion Gg1, but it is not limited thereto .

For example, the protrusion Gg1 includes first and second protrusions (not shown) adjacent to each other, and the width of the first protrusion is 1 to 2 times the width of the second protrusion, The length may be one to two times the length of the second projection.

In other words, the protrusion Gg1 and the corresponding protrusion Dd1 include a plurality of protrusions, and at least one protrusion of the plurality of protrusions has the same width or length as the protrusions of the other protrusions, D1), it is possible to secure the amount of charge.

The protrusion Gg1 and the corresponding protrusion Dd1 may include a plurality of protrusions, and each protrusion may have a different length, but is not limited thereto.

The second distance d12 may be 0.5 to 0.9 times the first distance d11, but is not limited thereto.

Although not shown in FIG. 4, the semiconductor device 200 may include a dielectric layer (not shown) between the third electrode G1 and the AlGaN layer 124. FIG.

5A is a cross-sectional view of the semiconductor device 200 taken along the line P3-P3 in FIG. 4, and FIG. 4B is a cross-sectional view of the semiconductor device 300 taken along line P4- Fig.

Here, the third electrode G1 is separated from the first electrode D1 by the first and second distances d11 and d12, and the description of the third electrode G1 is omitted in FIG. 4.

(c) is a graph showing a peak current or voltage between an edge of the third electrode G1 and an edge of the first electrode D1 when power is applied to the third electrode G1 .

That is, as shown in (c), the first and second graphs gr11 and gr12 are obtained by multiplying the peak current or voltage between the first and third electrodes D1 and G1 shown in (a) and (b) Distance and an electric field.

Here, the first graph gr11 generates a peak current or voltage at the first surface G_s11 and the first electrode D of the third electrode G1, and the second graph gr12 represents a peak current or voltage at the third electrode G1, A peak current or voltage is generated at the protrusion Gg1 of the first electrode G1 and the corresponding protrusion Dd1 of the first electrode D. [

The peak current or voltage shown in the first and second graphs (gr11, gr12) may have a higher breakdown voltage as the size is lower.

(d) shows a third graph (gr13) obtained by synthesizing the first and second graphs (gr11, gr12).

The peak current or voltage of the third graph gr13 is lower than the peak current or voltage of the first and second graphs gr11 and gr12 so that the charge amount Q Q) can be increased and the breakdown voltage can be lowered.

As shown in FIG. 5, by controlling the first and second distances d11 and d12 between the first and third electrodes D1 and G1, it is easy to control the voltage or the current, The reliability of the quality of the semiconductor device 200 can be improved.

Although the protrusions of the first electrode and the protrusions of the third electrode are shown as being angled at the edges, the protrusions may have a curvature, and the planar shape may be polygonal and semicircular. Do not.

The features, structures, effects and the like described in the embodiments are included in at least one embodiment of the present invention and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects and the like illustrated in the embodiments can be combined and modified by other persons skilled in the art to which the embodiments belong. Therefore, it should be understood that the present invention is not limited to these combinations and modifications.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of illustration, It will be appreciated that various modifications and applications are possible without departing from the scope of the present invention. For example, each component specifically shown in the embodiments can be modified and implemented. It is to be understood that all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

Claims (14)

Board;
A semiconductor layer on the substrate;
First and second electrodes which are ohmic-contacted on the semiconductor layer and are spaced apart from each other; And
And a third electrode disposed on the semiconductor layer and including a first surface adjacent to the first electrode and a second surface opposite the first surface and adjacent to the second electrode,
Wherein the third electrode comprises:
A protrusion is formed on the first face line in the direction of the first electrode,
Wherein the first electrode comprises:
A corresponding projection is formed at a position corresponding to the projection,
Wherein the first surface is spaced a first distance from the corresponding projection,
The projection being spaced a second distance from the corresponding projection,
And controlling the voltage or current by adjusting the first and second distances. delete 2. The method of claim 1,
Wherein the first distance is 0.5 to 0.9 times the first distance. The method according to claim 1,
The projection
And first and second projections adjacent to each other,
The width of the first projection
The width of the second protrusion is 1 to 2 times the width of the second protrusion,
The length of the first projection
Wherein the length of the second protrusion is 1 to 2 times the length of the second protrusion. delete 5. The method of claim 4,
The projection
And a third projection having a length different from the length of the first and second projections,
The planar shape of the projection
A polygon, a semicircle, and a shape having a curvature at an edge. delete The method according to claim 1,
And a dielectric layer between the semiconductor layer and the third electrode,
The plane area of the dielectric layer
And the second electrode is 1 to 1.2 times the plane area of the third electrode. delete The semiconductor device according to claim 1,
An undoped GaN layer on the substrate; And
And an AlGaN layer on the GaN layer. delete delete The method according to claim 1,
And the size of the projection is the same. delete

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