KR101806504B1 - Stereoscopic image display device - Google Patents

Abstract

The present invention relates to a stereoscopic image display apparatus of a pattern retarder type. The stereoscopic image display device of the present invention is characterized in that data lines, gate lines intersecting with the data lines, reset lines arranged in parallel with the gate lines are formed, and are defined by intersections of the data lines and the gate lines A display panel including a plurality of sub-pixels formed in a cell region; A data driver for converting the input digital video data into a data voltage and outputting the data voltage to the data lines; And a gate driver sequentially outputting a gate pulse synchronized with the data voltage to the gate lines and sequentially outputting a reset pulse having a pulse width larger than the gate pulse to the reset lines, , The shift register outputs a k-th gate pulse to a gate line at kth (k is a natural number satisfying 1? K? N, n is the number of gate lines of the display panel) And a k-th stage for outputting a k-th reset pulse.

Description

[0001] STEREOSCOPIC IMAGE DISPLAY DEVICE [0002]

The present invention relates to a stereoscopic image display apparatus of a pattern retarder type.

The stereoscopic display device displays a stereoscopic image using a stereoscopic technique or an autostereoscopic technique. The binocular parallax method uses parallax images of right and left eyes with large stereoscopic effect, and can be divided into a spectacular method and a non-spectacular method. In the spectacle method, the polarizing direction of the right and left parallax images is displayed on a direct view type display device or a projector, and a stereoscopic image is implemented using polarizing glasses. Alternatively, the glasses system displays the right and left parallax images on the direct-view type display device or the projector in a time-division manner, and realizes a stereoscopic image using the liquid crystal shutter glasses. In the non-eyeglass system, an optical plate such as a parallax barrier or a lenticular lens is generally used to separate the optical axes of the right and left parallax images to realize a stereoscopic image.

1 is a diagram showing a three-dimensional image display apparatus of a pattern retarder system. The stereoscopic image display apparatus of the pattern retarder system of FIG. 1 is provided with a polarizing characteristic of the patterned retarder 5 disposed on the display panel 3 and a polarizing characteristic of the polarizing glasses 6 worn by the user To realize a stereoscopic image. The pattern retarder type stereoscopic image display apparatus displays a left eye image L and a right eye image R on neighboring lines on the display panel 3 and enters the polarizing glasses 6 through the pattern retarder 5 Thereby switching the polarization characteristics. The pattern retarder type stereoscopic image display apparatus spatially divides the left eye image L and the right eye image R viewed by the user by making the polarization characteristics of the left eye image L and the right eye image R different from each other, 3D images can be implemented. In FIG. 1, reference numeral '1' designates a backlight unit for illuminating the display panel 3, reference numerals '2' and '4' designate the upper and lower plates of the display panel 3, Polarizing film.

The stereoscopic image display apparatus of the pattern retarder system is disadvantageous in that the visibility of the 3D image is deteriorated due to the crosstalk generated at the upper and lower viewing angle positions. The user can pass the light of the left eye image to the left eye of the user and pass only the light of the right eye image to the right eye of the user so that the user can view the optimum stereoscopic image. However, when both the light of the left eye image and the light of the right eye image are incident on the left eye (or right eye) of the user, the user can perform a 3D crosstalk that simultaneously sees the light of the left eye image and the right eye image through the left eye (or right eye) I feel. When the user views the display panel 3 above or below the front face, crosstalk occurs from a vertical angle of view larger than a predetermined angle with respect to the front viewing angle. Therefore, there is a disadvantage that the up and down viewing angles for viewing the 3D image without crosstalk in the pattern retarder type stereoscopic image display device are narrow.

Japanese Unexamined Patent Application Publication No. 2002-185983 discloses a method for enlarging the vertical viewing angle of a three-dimensional image display device of the pattern retarder type and a method of forming a black stripe (BS) on the pattern retarder 5 as shown in FIG. 2 . When the user observes the stereoscopic image display device at a position distant from the stereoscopic image display device by a predetermined distance D, the upper and lower viewing angles? At which no the crosstalk occurs theoretically can be detected by the black matrix The size of the black stripe BS formed in the pattern retarder 5 and the distance S between the display panel 3 and the pattern retarder 5. [ The upper and lower viewing angles a become wider as the size of the black matrix BM and the size of the black stripe BS become larger and wider as the distance between the display panel 3 and the pattern retarder 5 becomes smaller.

However, in a stereoscopic image display apparatus in which a black stripe (BS) is formed on the pattern retarder 5, the brightness is much lower than that of a display apparatus that displays only the conventional 2D due to the black stripe (BS). Further, in the stereoscopic image display apparatus in which the pattern retarder 5 is provided with black stripe (BS), precise alignment is required when the pattern retarder 5 is attached to the display panel 3. [ If the pattern retarder 5 is not aligned correctly, the black stripes (BS) do not play a role, so that the left eye image is displayed on the right eye or the right eye image is displayed on the left eye. Therefore, cross talk in which the left eye image and the right eye image overlap can occur.

In order to solve the problems of the stereoscopic image display device disclosed in Japanese Laid-Open Patent Publication No. 2002-185983, a technique of controlling some of the pixels of the display panel with an active black stripe (BS) has been proposed. In the case of a technique of controlling with an active black stripe (BS), each pixel of the display panel includes a pixel for displaying data and a pixel controlled by black stripe (BS). In order to prevent 3D luminance loss, pixels displaying data are generally formed larger than pixels controlled by black stripe (BS), since only pixels displaying data show only 3D images. Therefore, the liquid crystal cell capacity of a pixel displaying data is larger than the liquid crystal cell capacity of a pixel controlled by a black stripe (BS). The voltage charged in the liquid crystal cell of the pixel displaying the data and the voltage charged in the liquid crystal cell of the pixel controlled by the black stripe (BS) are the kickback voltage generated by the parasitic capacitance of the TFT (Thin Film Transistor) Feed Through Voltage, ΔVp). The kickback voltage (Vp) is expressed by Equation (1).

'Cgd' is the parasitic capacitance formed between the gate electrode of the TFT connected to the gate line and the drain electrode of the TFT connected to the pixel electrode of the liquid crystal cell, 'Clc' is the capacitance of the liquid crystal cell, Cst 'denotes the capacity of the storage capacitor. DELTA Vg is a difference voltage between the first gate high voltage VGH and the first gate low voltage VGL of the gate pulse supplied to the gate line.

Since the liquid crystal cell capacitance Clc of the pixel displaying the data and the liquid crystal cell capacitance Clc of the pixel controlled by the black stripe BS are different from each other in the expression (1), the kickback voltage? Vp of the pixel, And a kickback voltage (? Vp) of a pixel controlled by a black stripe (BS). That is, the kickback voltage DELTA Vp of the pixel controlled by the black stripe (BS) is larger than the kickback voltage DELTA Vp of the pixel representing the data. A voltage charged in a liquid crystal cell of a pixel controlled by a black stripe (BS) is largely lowered due to a kickback voltage (DELTA Vp), so that a pixel controlled by a black stripe (BS) can not display a perfect black gradation do. That is, a pixel controlled by a black stripe (BS) does not function as a black stripe (BS). Therefore, since the effect of the black stripe (BS) that can broaden the vertical viewing angle of the user is reduced by half, there arises a problem that the cross talk increases as the vertical angle of view of the user becomes wider.

The present invention provides a stereoscopic image display device capable of reducing a kickback voltage of a pixel controlled by a black stripe.

The stereoscopic image display device of the present invention is characterized in that data lines, gate lines intersecting with the data lines, reset lines arranged in parallel with the gate lines are formed, and are defined by intersections of the data lines and the gate lines A display panel including a plurality of sub-pixels formed in a cell region; A data driver for converting the input digital video data into a data voltage and outputting the data voltage to the data lines; And a gate driver sequentially outputting a gate pulse synchronized with the data voltage to the gate lines and sequentially outputting a reset pulse having a pulse width larger than the gate pulse to the reset lines, , The shift register outputs a k-th gate pulse to a gate line at kth (k is a natural number satisfying 1? K? N, n is the number of gate lines of the display panel) And a k-th stage for outputting a k-th reset pulse.

The present invention minimizes the difference voltage between the gate high voltage and the gate low voltage of the reset pulse supplied to the pixel controlled by the black stripe. As a result, the present invention can reduce the kickback voltage of a pixel controlled by a black stripe, and display a perfect black gradation on a pixel controlled by a black stripe. Therefore, the present invention can reduce the crosstalk that occurs when the vertical viewing angle is widened, and eventually the upper and lower viewing angles for viewing stereoscopic images are widened.

Further, the present invention generates a gate pulse and a reset pulse using one circuit. As a result, according to the present invention, an image is displayed on a pixel displaying data in a 2D mode and a pixel controlled by a black stripe without increasing the driving frequency of a shift register, displaying an image on a pixel displaying data in a 3D mode, The black gradation can be displayed on the pixel to be controlled. Thus, the present invention can reduce the circuit cost of the shift register. Furthermore, since the number of circuits of the shift register can be reduced, the circuit integration of the shift register can be reduced and the reliability of the shift register can be increased.

1 is a view showing a pattern retarder type stereoscopic image display apparatus.
2 is a view showing a stereoscopic image display apparatus in which a black stripe is formed on a pattern retarder.
3 is a block diagram schematically showing a stereoscopic image display apparatus according to an embodiment of the present invention.
4 is an exploded perspective view showing a display panel, a pattern retarder, and polarized glasses.
5 is a block diagram showing a display panel, a gate driving circuit, a data driving circuit, and a timing controller formed in a GIP scheme.
6 is a circuit diagram showing details of a part of pixels of a display panel according to an embodiment of the present invention.
7 is a waveform diagram showing a gate pulse, a reset pulse, a data voltage, and the voltages of the pixel electrode and the common electrode of the first pixel and the second pixel, respectively, supplied to the subpixel of FIG. 6 in the 2D mode.
8 is a view showing the display contents of the pixels in the 2D mode.
9 is a waveform diagram showing a gate pulse, a reset pulse, a data voltage, and a voltage of a pixel electrode and a common electrode of a first pixel and a second pixel, respectively, supplied to the subpixel of FIG. 6 in the 3D mode.
10 is a view showing the display contents of the pixels in the 3D mode.
11 is a detailed view of a shift register according to an embodiment of the present invention.
12 is a circuit diagram showing the k-th stage of Fig. 11 in detail.
FIG. 13 is a waveform diagram showing input / output signals of the k-th and (k + 6) -th stages in the 2D mode and voltage changes of the Q-node, QB1-node, and QB2-node.
14 is a waveform diagram showing input / output signals of the k-th and (k + 6) -th stages in the 3D mode and voltage changes of the Q-node, QB1-node, and QB2-node.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

The names of components used in the following description are selected in consideration of ease of specification, and may be different from actual product names.

3 is a block diagram schematically showing a stereoscopic image display apparatus according to an embodiment of the present invention. 4 is an exploded perspective view showing a display panel, a pattern retarder, and polarized glasses. 5 is a block diagram showing a display panel, a gate driving circuit, a data driving circuit, and a timing controller formed in a GIP scheme. 3 to 5, a stereoscopic image display apparatus according to the present invention includes a display panel 10, polarizing glasses 20, a gate driving circuit 110, a data driving circuit 120, a timing controller 130, Host system 140, and the like.

The stereoscopic image display device of the present invention can be applied to a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), an organic light emitting diode Diodes, and OLEDs). Although the present invention has been described with reference to liquid crystal display elements in the following embodiments, it should be noted that the present invention is not limited to liquid crystal display elements.

The display panel 10 displays an image under the control of the timing controller 130. In the display panel 10, a liquid crystal layer is formed between two glass substrates. On the lower glass substrate of the display panel 10, data lines and gate lines (or scan lines) are formed so as to intersect with each other, and pixels are formed in a matrix in the cell regions defined by the data lines and gate lines So that the arranged TFT array is formed. In the display panel 10, reset lines are formed in parallel with the gate lines. Each of the pixels of the display panel 10 is connected to the thin film transistor and driven by an electric field between the pixel electrode and the common electrode.

On the upper glass substrate of the display panel 10, a color filter array including a black matrix, a color filter, a common electrode, and the like is formed. The common electrode is formed on the upper glass substrate in a vertical electric field driving method such as a TN (Twisted Nematic) mode and a VA (Vertical Alignment) mode, and a horizontal electric field such as IPS (In Plane Switching) mode and FFS (Fringe Field Switching) Is formed on the lower glass substrate together with the pixel electrode in the driving method. Although the liquid crystal mode of the display panel 10 of the present invention has been described in the context of the IPS mode as shown in FIG. 6, it should be noted that the present invention is not limited thereto. The liquid crystal mode of the display panel 10 can be implemented in any liquid crystal mode as well as the TN mode, VA mode, IPS mode, and FFS mode described above.

The display panel 10 is typically a transmissive liquid crystal display panel that modulates light from the backlight unit. The backlight unit includes a light source, a light guide plate (or diffusion plate), and a plurality of optical sheets that are turned on in accordance with a driving current supplied from the backlight unit driving unit. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit. The light sources of the backlight unit may include any one of a light source of HCFL (Cold Cathode Fluorescent Lamp), CCFL (Cold Cathode Fluorescent Lamp), EEFL (External Electrode Fluorescent Lamp), LED .

The backlight unit driving unit generates a driving current for lighting the light sources of the backlight unit. The backlight unit driving unit turns ON / OFF the driving current supplied to the light sources under the control of the backlight control unit. The backlight control unit outputs backlight control data in which the backlight luminance and the lighting timing are adjusted in accordance with the global / local dimming signal (DIM) input from the host system to the backlight unit driving unit in the SPI (Serial Pheriipheral Interface) data format.

Referring to FIG. 4, an upper polarizer 11a is attached to the upper glass substrate of the display panel 10, and a lower polarizer 11b is attached to the lower glass substrate. The light transmission axis r1 of the upper polarizer plate 11a and the light transmission axis r2 of the lower polarizer plate 11b are orthogonal. An alignment film for setting a pre-tilt angle of the liquid crystal is formed on the upper glass substrate and the lower glass substrate. A spacer for maintaining a cell gap of the liquid crystal layer is formed between the upper glass substrate and the lower glass substrate of the display panel 10. [

In the 2D mode, the pixels of the odd lines of the display panel 10 and the pixels of the even lines display 2D images. In the 3D mode, the pixels of the odd lines of the display panel 10 display the left eye image (or the right eye image), and the pixels of the even lines display the right eye image (or the left eye image). The light of the image displayed on the pixels of the display panel 10 is incident on the patterned retarder 30 disposed on the display panel 10 through the upper polarizing film.

A first retarder 31 is formed on the odd number lines of the pattern retarder 30 and a second retarder 32 is formed on the even number lines. The pixels of the odd lines of the display panel 10 are opposed to the first retarder 31 formed in the odd lines of the pattern retarder 30 and the pixels of the even lines of the display panel 10 are opposed to the pattern retarder 30. [ And is opposed to the second retarder 32 formed on the even lines of the further 30.

The first retarder 31 delays the phase value of light from the display panel 10 by +? / 4 (? Is the wavelength of light). The second retarder 32 delays the phase value of light from the display panel 10 by -λ / 4. The optic axis r3 of the first retarder 31 and the optical axis r4 of the second retarder 32 are orthogonal to each other. The first retarder 31 of the pattern retarder 30 may be implemented to pass only the first circularly polarized light (left circularly polarized light). The second retarder 32 may be implemented to pass only the second circularly polarized light (right circularly polarized light).

The left eye polarizing filter of the polarizing glasses 20 has the same optical axis as the first retarder 31 of the pattern retarder 30. [ The right eye polarizing filter of the polarizing glasses 20 has the same optical axis as the second retarder 32 of the pattern retarder 30. [ For example, the left eye polarizing filter of the polarizing glasses 20 can be selected as a left circular polarization filter, and the right eye polarizing filter of the polarizing glasses 20 can be selected as a right circular polarization filter. The user wears polarized glasses when viewing 3D images, and polarized glasses should be removed when viewing 2D images.

As a result, in the three-dimensional image display apparatus of the pattern retarder type, the left eye image displayed on the pixels of the odd line of the display panel 10 passes through the first retarder 31 and is converted into the left circularly polarized light, The right eye image displayed on the right eye is converted to right-handed circularly polarized light by passing through the second retarder 32. The left circularly polarized light passes through the left eye polarizing filter of the polarizing glasses 20 to reach the left eye of the user and the right circularly polarized light passes through the right eye polarizing filter of the polarizing glasses 20 to reach the right eye of the user. Therefore, the user sees only the left eye image through the left eye, and only the right eye image through the right eye.

The data driving circuit 120 includes a plurality of source drive ICs 70. The source driver ICs 70 convert the digital video data RGB input from the timing controller 130 into a positive / negative gamma compensation voltage to generate positive / negative analog data voltages. Positive / negative polarity analog data voltages output from the source drive ICs are supplied to the data lines of the display panel 10.

The gate driving circuit 110 sequentially supplies gate pulses (Gate Pulse, GP) synchronized with the data voltage to the gate lines of the display panel 10 under the control of the timing controller 130. In addition, the gate driving circuit 110 sequentially supplies reset pulses (RP) to the reset lines of the display panel 10. The gate drive circuit 110 includes a level shifter 40, a shift register 50, and the like. The level shifter 40 outputs a TTL (Transistor-Transistor-Logic) logic level voltage of the clocks (Clocks, CLKs) input from the timing controller 130 to the first gate high voltage VGH and the first first gate low voltage (VGL). The shift register 50 sequentially generates the gate pulse GP and the reset pulse RP in accordance with the clocks CLKs input from the level shift 40. A detailed description of the shift register 50 will be given later with reference to FIGS. 6 and 10. FIG.

In the GIP (Gate Drive-IC In Panel) method, the level shifter 40 is mounted on a PCB (Printed Circuit Board) 60 and the shift register 50 is formed directly on the lower substrate of the display panel 10 do. Or the gate drive circuit 110 may be formed of gate drive integrated circuits including a level shifter 40 and a shift register 50 and may be attached to the display panel 10 by a TAB (Tape Automated Bonding) method.

The timing controller 130 receives the digital video data RGB, the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the data enable signal DE and the main clock MCLK output from the host system 140 Outputs the gate drive circuit control signal GCS to the gate drive circuit 110 and the data drive circuit control signal DCS to the data drive circuit 120 based on the timing signals and the mode signal MODE . The gate drive circuit control signal GCS includes a start voltage VST, clocks CLKs, and the like. The start voltage (VST) controls the timing of the first gate pulse (GP) of the shift register (50). The clocks CLKs can be generated on i (where i is a natural number equal to or greater than 3) and input to the shift register 50 to control the output of the shift register 50. [

The data driving circuit control signal DCS includes a source start pulse SSP, a source sampling clock SSC, a source output enable SOE, a polarity control signal POL, And the like. The source start pulse SSP controls the data sampling start timing of the data driving circuit 120. The source sampling clock is a clock signal for controlling the sampling operation of the data driving circuit 120 based on the rising or falling edge. The source start pulse SSP and the source sampling clock SSC may be omitted if the digital video data RGB to be input to the data driving circuit 120 is transmitted in accordance with the mini LVDS (Low Voltage Differential Signaling) interface standard. The polarity control signal POL inverts the polarity of the data voltage output from the data driving circuit 120 to L (L is a natural number) horizontal period period. The source output enable signal SOE controls the output timing of the data driving circuit 120.

The host system 140 supplies digital video data RGB to the timing controller 130 through an interface such as a Low Voltage Differential Signaling (LVDS) interface and a Transition Minimized Differential Signaling (TMDS) interface. The host system 140 also supplies the timing controller 130 with a timing signal (Vsync, Hsync, DE, MCLK), a mode signal (MODE) capable of distinguishing between the 2D mode and the 3D mode.

6 is a circuit diagram showing details of a part of pixels of a display panel according to an embodiment of the present invention. 6, a gate line (GLk, k is a natural number satisfying 1? K? N) and a data line (DLj, j are natural numbers satisfying 1? J? M) on the lower substrate of the display panel 10, and m is the number of data lines of the display panel). A reset line RLk is formed in a direction parallel to the gate line GLk and a common voltage line Vcom Line is formed in a direction parallel to the data line DLj.

The shift register 50 includes a plurality of stages ST (k). The k-th stage ST (k) is connected to the k-th gate line GLk and the (k-6) -th reset line RLk-6. The k-th stage ST (k) outputs the k-th gate pulse GPk to the k-th gate line GLk and the k-th reset pulse RPk to the k-6 reset line RLk-6 do. Further, the (k + 6) th stage ST (k + 6) is connected to the (k + 6) -th gate line GLk + 6 and the k-th reset line RLk. The k + 6th stage ST (k + 6) outputs the (k + 6) -th gate pulse GPk + 6 to the (k + 6) -th gate line GLk + 6) to the k < th > reset line RLk. The kth stage ST (k) in Fig. 6 is only one embodiment, and the kth stage ST (k) has the same structure as the kth gate line GLk and the kth reset line RLk, Lt; / RTI > In this case, the k-th stage ST (k) outputs the k-th gate pulse GPk to the k-th gate line GLk, and the k-th reset pulse RPk is reset before the k-th reset line RLk Line.

It should be noted that although each of the pixels 200 has been described as including a red subpixel R, a green subpixel G, and a blue subpixel B, it is not so limited. Each of the red subpixel R, the green subpixel G and the blue subpixel B includes a first pixel 210 and a second pixel 220. The first pixel 210 displays an image in 2D and 3D modes. The second pixel 220 displays the image in the 2D mode, while displaying the black gradation in the 3D mode. That is, the second pixel 220 serves as a black stripe in the 3D mode.

The first pixel 210 is connected to the first scan TFT 211 and driven by an electric field between the first pixel electrode 240 and the common electrode 250. The first pixel electrodes 240 of the first pixel 210 are connected to the drain electrode of the first scan TFT 211 and the common electrodes 250 are connected to the common voltage line Vcom Line. The first pixel electrode 240 and the common electrode 250 of the first pixel 210 are formed to be parallel to each other so that a horizontal electric field can be formed.

The first scan TFT 211 applies the data voltage of the jth data line DLj to the first pixel electrode 240 of the first pixel 210 in response to the kth gate pulse GPk of the kth gate line GLk . The gate electrode of the first scan TFT 211 is connected to the kth gate line GLk, the source electrode thereof is connected to the jth data line DLj, and the drain electrode is connected to the first pixel electrode 210 of the first pixel 210. [ (240).

The second pixel 220 is connected to the second and third scan TFTs 221 and 222 and driven by an electric field between the second pixel electrode 260 and the common electrode 250. The second pixel electrodes 260 of the second pixel 220 are connected to the drain electrode of the second scan TFT 221 and the source electrode of the third scan TFT 222 and the common electrodes 250 are connected to the common voltage line Vcom Line. The second pixel electrode 260 and the common electrode 250 of the second pixel 220 are formed to be parallel to each other so that a horizontal electric field can be formed.

The second scan TFT 221 applies the data voltage of the jth data line DLj to the second pixel electrode 260 of the second pixel 220 in response to the kth gate pulse GPk of the kth gate line GLk . The gate electrode of the second scan TFT 221 is connected to the kth gate line GLk and the source electrode thereof is connected to the jth data line DLj and the drain electrode thereof is connected to the second pixel electrode 220 of the second pixel 220. [ (Not shown). The third scan TFT 222 applies the common voltage of the common voltage line Vcom Line to the second voltage of the second pixel 220 in response to the (k + 6) -th reset pulse RPk + 6 of the kth reset line RLk. And supplies it to the pixel electrode 260. The gate electrode of the third scan TFT 222 is connected to the kth reset line RLk and the source electrode thereof is connected to the second pixel electrode 260 of the second pixel 220. The drain electrode of the third scan TFT 222 is connected to the common voltage line Vcom Line.

6, each of the red, green, and blue subpixels R, G, and B of the display panel 10 according to the exemplary embodiment of the present invention is described as being implemented in the IPS mode. However, . The liquid crystal mode of the display panel 10 can be implemented in any liquid crystal mode as well as the TN mode, VA mode, IPS mode, and FFS mode described above. Hereinafter, the operation of the signals and the subpixels R, G, B input to the subpixels R, G, B in the 2D mode and the 3D mode will be described with reference to FIGS. 7 to 10 .

7 is a waveform diagram showing a gate pulse, a reset pulse, a data voltage, and the voltages of the pixel electrode and the common electrode of the first pixel and the second pixel, respectively, supplied to the subpixel of FIG. 6 in the 2D mode. 8 is a view showing the display contents of the pixels in the 2D mode.

Referring to FIG. 7, the gate pulse GP is generated at the first gate high voltage VGH and polled at the first gate low voltage VGL. The gate pulse GP is generated in the 2D mode with the first gate high voltage VGH for approximately three horizontal periods 3H. One horizontal period (1H) refers to a one-line scanning time at which data is written to one line of pixels in the display panel 10. The reset pulse RP maintains the second gate low voltage VGL 'which is lower than the first gate low voltage VGL.

The first gate high voltage VGH is set to be higher than the threshold voltages of the first and second scan TFTs 211 and 221 and the first gate low voltage VGL is set to be higher than the threshold voltage of the first and second scan TFTs 211 and 221, Lt; / RTI > And the second gate high voltage VGH 'may be set to be higher than the threshold voltage of the third scan TFT 222. [ The second gate low voltage VGL 'may be set to be lower than the threshold voltage of the third scan TFT 222. [ That is, the threshold voltages of the first and second scan TFTs 211 and 221 are set higher than the threshold voltage of the third scan TFT 222. The third scan TFT 222 is turned on in response to the second gate high voltage VGH 'while the first and second scan TFTs 211 and 221 are turned on in response to the second gate high voltage VGH' It is not turned on. The first and second scan TFTs 211 and 221 are turned on in response to the first gate high voltage VGH.

The phase difference between the k-th gate pulse GPk and the (k + 1) -th gate pulse GPk + 1 that are sequentially generated is approximately one horizontal period (1H). Therefore, the k-th gate pulse GPk and the (k + 1) -th gate pulse GPk + 1 are generated so as to overlap in about two horizontal periods (2H).

The data voltage Vdata is supplied to the jth data line DLj in approximately one horizontal period (1H). That is, the k-th data voltage Vk is supplied to the j-th data line DLj in synchronization with the last one horizontal period (1H) of the k-th gate pulse GPk. 7, positive polarity voltages higher than the common voltage (Vcom) level are continuously applied to the j data line DLj during one frame period, and negative voltages lower than the common voltage (Vcom) level during the next one frame period Th row and the j-th data line DLj. However, the present invention is not limited to this, and it should be noted that any driving method such as a dot inversion method, a 2 horizontal version method, a 2 vertical version method, a line in version method, and a frame inversion method can be implemented do.

6 and 7, the first scan TFT 211 is connected to the k-th gate line GLk, the second scan TFT 221 is connected to the k-th gate line GLk, The operation of the first pixel 210 and the second pixel 220 in the 2D mode will be described in detail, focusing on the fact that the three-scan TFT 222 is connected to the kth reset line RLk. At this time, a k-th gate pulse GPk is output from the k-th stage ST (k) to the k-th gate line GLk, and a k-th stage ) Outputs a (k + 6) -th reset pulse (RPk + 6).

First, the operation of the first pixel 210 during t1 to t4 will be discussed.

During the period t1, the first scan TFT 211 is turned on in response to the k-th gate pulse GPk of the first gate high voltage VGH to turn the (k-2) -th data voltage Vk- To the first pixel electrode (240) of the pixel electrode (210). Accordingly, the voltage Vp1 of the first pixel electrode 240 of the first pixel 210 rises to the k-2 data voltage Vk-2 with respect to the common voltage Vcom.

During the period t2, the first scan TFT 211 is turned on in response to the k-th gate pulse GPk of the first gate high voltage VGH to turn the (k-1) -th data voltage Vk- To the first pixel electrode (240) of the pixel electrode (210). Therefore, the voltage Vp1 of the first pixel electrode 240 of the first pixel 210 rises to the k-1 data voltage Vk-1 with respect to the common voltage Vcom.

During the period t3, the first scan TFT 211 is turned on in response to the k-th gate pulse GPk of the first gate high voltage VGH to output the k-th data voltage Vk to the first pixel 210 And supplies it to the first pixel electrode 240. Accordingly, the voltage Vp1 of the first pixel electrode 240 of the first pixel 210 rises to the kth data voltage Vk with respect to the common voltage Vcom.

During the period t4, the first scan TFT 211 is turned off by the k-th gate pulse GPk of the first gate-low voltage VGL. The first pixel electrode 240 of the first pixel 210 holds the kth data voltage Vk for about one frame period by a storage capacitor. Accordingly, a voltage difference occurs between the first pixel electrode 240 and the common electrode 250 of the first pixel 210, so that the first pixel 210 displays an image as shown in FIG.

Second, the operation of the second pixel 220 during t1 to t4 will be discussed. During the period from t1 to t4, the third scan TFT 222 is not turned on by the kth reset pulse RPk of the second gate low voltage VGL '.

During the period t1, the second scan TFT 221 is turned on in response to the k-th gate pulse GPk of the first gate high voltage VGH to turn the (k-2) -th data voltage Vk- To the second pixel electrode (260) of the pixel electrode (220). Accordingly, the voltage Vp2 of the second pixel electrode 260 of the second pixel 220 rises up to the k-2 data voltage Vk-2 with respect to the common voltage Vcom.

During the period t2, the second scan TFT 221 is turned on in response to the k-th gate pulse GPk of the first gate high voltage VGH to turn on the (k-1) -th data voltage Vk- To the second pixel electrode (260) of the pixel electrode (220). Therefore, the voltage Vp2 of the second pixel electrode 260 of the second pixel 220 rises up to the (k-1) th data voltage Vk-1 with respect to the common voltage Vcom.

During the period t3, the second scan TFT 221 is turned on in response to the k-th gate pulse GPk of the first gate high voltage VGH to supply the k-th data voltage Vk to the second pixel 220 And supplies it to the second pixel electrode 260. Therefore, the voltage Vp2 of the second pixel electrode 260 of the second pixel 220 rises to the kth data voltage Vk with respect to the common voltage Vcom.

During the period t4, the second scan TFT 221 is turned off by the k-th gate pulse GPk of the first gate-low voltage VGL. The second pixel electrode 260 of the second pixel 220 maintains the kth data voltage Vk for about one frame period by a storage capacitor. Therefore, a voltage difference occurs between the second pixel electrode 260 of the second pixel 220 and the common electrode 250, so that the second pixel 220 displays an image as shown in FIG.

8, in the 2D mode, the first pixel 210 of the R sub-pixel R displays the R image Red and the first pixel 210 of the G sub-pixel G displays the G image , And the first pixel 210 of the B sub-pixel B displays a B image (Blue). The second pixel 220 of the R subpixel R represents the R image, the second pixel 220 of the G subpixel G represents the G image Green, And the second pixel 220 of the pixel B displays a B image (Blue). That is, in the 2D mode, the first and second pixels 210 and 220 of the R subpixel R, the first and second pixels 210 and 220 of the G subpixel G, and the B subpixel B, The brightness of the 2D image can be increased compared with the case where the black stripes are formed on the pattern retarder 30, because the first and second pixels 210 and 220 of the first and second pixels 210 and 220 are displayed.

9 is a waveform diagram showing a gate pulse, a reset pulse, a data voltage, and a voltage of a pixel electrode and a common electrode of a first pixel and a second pixel, respectively, supplied to the subpixel of FIG. 6 in the 3D mode. 10 is a view showing the display contents of the pixels in the 3D mode.

Referring to Fig. 9, the gate pulse GP is generated at the first gate high voltage VGH and polled at the first gate low voltage VGL. The gate pulse GP is generated in the 3D mode at the first gate high voltage VGH for approximately three horizontal periods 3H. The reset pulse GP is generated at the second gate high voltage VGH 'and polled at the second gate low voltage VGL'. The pulse width of the reset pulse RP is larger than the pulse width of the gate pulse GP. The reset pulse RP may occur at the second gate high voltage VGH 'for approximately six horizontal periods 6H as shown in FIG.

The first gate high voltage VGH is set to be higher than the threshold voltages of the first and second scan TFTs 211 and 221 and the first gate low voltage VGL is set to be higher than the threshold voltage of the first and second scan TFTs 211 and 221, Lt; / RTI > And the second gate high voltage VGH 'may be set to be higher than the threshold voltage of the third scan TFT 222. [ The second gate low voltage VGL may be set lower than the threshold voltage of the third scan TFT 222. [ That is, the threshold voltages of the first and second scan TFTs 211 and 221 are set higher than the threshold voltage of the third scan TFT 222. The third scan TFT 222 is turned on in response to the second gate high voltage VGH 'while the first and second scan TFTs 211 and 221 are turned on in response to the second gate high voltage VGH' It is not turned on. The first and second scan TFTs 211 and 221 are turned on in response to the first gate high voltage VGH.

The phase difference between the k-th gate pulse GPk and the (k + 1) -th gate pulse GPk + 1 that are sequentially generated is approximately one horizontal period (1H). Therefore, the k-th gate pulse GPk and the (k + 1) -th gate pulse GPk + 1 are generated so as to overlap in about two horizontal periods (2H). The phase difference between the k-th reset pulse RPk and the (k + 1) -th reset pulse RPk + 1 that are sequentially generated is approximately one horizontal period (1H). Therefore, the k < th > reset pulse RPk and the (k + 1) -th reset pulse RPk + 1 occur to overlap in about 5 horizontal periods 5H.

The data voltage Vdata is supplied to the jth data line DLj in approximately one horizontal period (1H). That is, the k-th data voltage Vk is supplied to the j-th data line DLj in synchronization with the last one horizontal period (1H) of the k-th gate pulse GPk. 9, positive voltages higher than the common voltage (Vcom) level are continuously applied to the j data line DLj during one frame period, and negative voltages lower than the common voltage (Vcom) level for the next one frame period Th row and the j-th data line DLj. However, the present invention is not limited to this, and it should be noted that any driving method such as a dot inversion method, a 2 horizontal version method, a 2 vertical version method, a line in version method, and a frame inversion method can be implemented do.

6 and 9, the first scan TFT 211 is connected to the k-th gate line GLk, the second scan TFT 221 is connected to the k-th gate line GLk, The operation of the first pixel 210 and the second pixel 220 in the 3D mode will be described in detail with reference to the fact that the three-scan TFT 222 is connected to the kth reset line RLk. At this time, a k-th gate pulse GPk is outputted from the k-th stage ST (k) to the k-th gate line GLk, and a k-th stage ) Outputs a (k + 6) -th reset pulse (RPk + 6).

First, the operation of the first pixel 210 during t1 to t5 will be discussed.

During the period t1, the first scan TFT 211 is turned on in response to the k-th gate pulse GPk of the first gate high voltage VGH to turn the (k-2) -th data voltage Vk- To the first pixel electrode (240) of the pixel electrode (210). Accordingly, the voltage Vp1 of the first pixel electrode 240 of the first pixel 210 rises to the k-2 data voltage Vk-2 with respect to the common voltage Vcom.

During the period t2, the first scan TFT 211 is turned on in response to the k-th gate pulse GPk of the first gate high voltage VGH to turn the (k-1) -th data voltage Vk- To the first pixel electrode (240) of the pixel electrode (210). Therefore, the voltage Vp1 of the first pixel electrode 240 of the first pixel 210 rises to the k-1 data voltage Vk-1 with respect to the common voltage Vcom.

During the period t3, the first scan TFT 211 is turned on in response to the k-th gate pulse GPk of the first gate high voltage VGH to output the k-th data voltage Vk to the first pixel 210 And supplies it to the first pixel electrode 240. Accordingly, the voltage Vp1 of the first pixel electrode 240 of the first pixel 210 rises to the kth data voltage Vk with respect to the common voltage Vcom.

During the periods t4 and t5, the first scan TFT 211 is turned off by the k-th gate pulse GPk of the first gate-low voltage VGL. The first pixel electrode 240 of the first pixel 210 holds the kth data voltage Vk for about one frame period by a storage capacitor. Therefore, a voltage difference occurs between the first pixel electrode 240 of the first pixel 210 and the common electrode 250, so that the first pixel 210 displays an image as shown in FIG.

Secondly, the operation of the second pixel 220 during t1 to t5 will be discussed.

During the period t1, the second scan TFT 221 is turned on in response to the k-th gate pulse GPk of the first gate high voltage VGH to turn the (k-2) -th data voltage Vk- To the second pixel electrode (260) of the pixel electrode (220). Accordingly, the voltage Vp2 of the second pixel electrode 260 of the second pixel 220 rises up to the k-2 data voltage Vk-2 with respect to the common voltage Vcom.

During the period t2, the second scan TFT 221 is turned on in response to the k-th gate pulse GPk of the first gate high voltage VGH to turn on the (k-1) -th data voltage Vk- To the second pixel electrode (260) of the pixel electrode (220). Therefore, the voltage Vp2 of the second pixel electrode 260 of the second pixel 220 rises up to the (k-1) th data voltage Vk-1 with respect to the common voltage Vcom.

During the period t3, the second scan TFT 221 is turned on in response to the k-th gate pulse GPk of the first gate high voltage VGH to supply the k-th data voltage Vk to the second pixel 220 And supplies it to the second pixel electrode 260. Therefore, the voltage Vp2 of the second pixel electrode 260 of the second pixel 220 rises to the kth data voltage Vk with respect to the common voltage Vcom.

During the period t4, the second scan TFT 221 is turned off by the k-th gate pulse GPk of the first gate-low voltage VGL. The third scan TFT 222 is turned on in response to the second gate high voltage VGH 'to supply the common voltage Vcom to the second pixel electrode 260 of the second pixel 220. Accordingly, the voltage Vp2 of the second pixel electrode 260 of the second pixel 220 is lowered to the common voltage Vcom.

During the period t5, the third scan TFT 222 is turned off by the kth reset pulse RPk of the second gate-low voltage VGL '. The second pixel electrode 260 of the second pixel 220 maintains the common voltage Vcom for about one frame period by a storage capacitor. Accordingly, since the voltage difference does not occur between the second pixel electrode 260 of the second pixel 220 and the common electrode 250, the second pixel 220 displays black gradation as shown in FIG.

10, in the 3D mode, the first pixel 210 of the R subpixel R displays the R image Red and the first pixel 210 of the G subpixel G displays the G image Green , And the first pixel 210 of the B sub-pixel B displays a B image (Blue). The second pixel 220 of the R subpixel R, the second pixel 220 of the G subpixel G and the second pixel 220 of the B subpixel B are black gradations, . That is, in the 3D mode, the second pixel 220 of the R subpixel R, the second pixel 220 of the G subpixel G, and the second pixel 220 of the B subpixel B, .

11 is a detailed view of a shift register according to an embodiment of the present invention. The shift register 50 according to the embodiment of the present invention has a plurality of stages connected in a dependent manner. Each of the stages ST (1) to ST (n) is connected in a 1: 1 relationship with a gate line, outputs a gate pulse, and is connected in a 1: 1 relationship with reset lines to output a reset pulse. In Fig. 11, only the k-th to (k + 4) th stages ST (k) to ST (k + 4) are illustrated for convenience of explanation.

In the following description, the term "front stage" means that the stage is located above the reference stage. For example, on the basis of the k-th stage ST (k), the front stage indicates either the first stage ST (1) to the k-th stage ST (k). Quot; rear stage "refers to a stage located at the bottom of the reference stage. For example, with respect to the k-th stage ST (k), the trailing stage designates any one of the k-th stage ST (k) to the n-th stage ST (n).

The start voltage VST is supplied to the start voltage line VL and each of the first to sixth clocks C1 to C6 is supplied to each of the first to sixth clock lines CL1 to CL6. Each of the stages ST (1) to ST (n) includes an initialization terminal INI, a start terminal START, a reset terminal RESET, a first clock terminal CLK1, a second clock terminal CLK2, 1 output terminal OUT1, a second output terminal OUT2, and a carry signal output terminal CARRY.

The start voltage VST is input to the initializing terminal INI of each of the stages ST (1) to ST (n). Each of the stages ST (1) to ST (n) initializes the Q node Q to the voltage of the first low potential voltage source VSS1 by the start voltage VST input to the initialization terminal INI.

The carry signal of the front stage is inputted to the start terminal START of each of the stages ST (1) to ST (n). The carry signal of the (k-3) th stage ST (k-3) is inputted to the start terminal START of the k-th stage ST (k). The start voltage VST may be input to the start terminal START of the first to third stages ST (1) to ST (3). In this case, the start voltage VST is not inputted to the initializing terminal INI of the first to third stages ST (k).

The carry signal of the subsequent stage is inputted to the reset terminal RESET of each of the stages ST (1) to ST (n). The carry signal of the (k + 3) th stage ST (k + 3) is input to the reset terminal RESET of the k-th stage ST (k). The carry signals of the first to third dummy stages DST (1) to DST (3) are supplied to the reset terminals RESET of the n-3 to n-th stages ST (n-3) to ST Can be input. In this case, the first to third dummy stages DST (1) to DST (3) do not output the gate pulse GP or the reset pulse RP, -3) to ST (n).

Any one of i (i is a natural number equal to or greater than 3) phase clocks sequentially delayed in phase is input to the first clock terminal CLK1 of each of the stages ST (1) to ST (n). For example, when the fourth clock C4 is input to the k-th stage ST (k), the fifth clock C5 is input to the (k + 1) th stage ST (k + 1). The i-phase clocks have a pulse width of a predetermined time, and are sequentially delayed in phase. For example, the i-phase clocks may have a pulse width of about 3 horizontal periods (3H) as shown in Figs. 13 and 14, and may be implemented with 6-phase clocks whose phases are sequentially delayed by one horizontal period (1H) . The i-phase clocks swing between the first gate high voltage (VGH) and the first gate low voltage (VGL).

The DC voltage Vdc from the multiplexer MUX is input to the second clock terminal CLK2 of each of the stages ST (1) to ST (n). The multiplexer MUX receives the second gate high voltage VGH 'and the second gate low voltage VGL' and outputs a voltage according to the mode signal MODE. The multiplexer MUX outputs the second gate low voltage VGL 'in the 2D mode and the second gate high voltage VGH' in the 3D mode.

Each of the stages ST (1) to ST (n) has first and second output terminals OUT1 and OUT2 and a carry signal output terminal CARRY. The first output terminal OUT1 of the k-th stage ST (k) is connected to the k-th gate line GLk. The k-th gate pulse GPk from the first output terminal OUT1 of the k-th stage ST (k) is outputted to the k-th gate line GLk. The second output terminal OUT2 of the k-th stage ST (k) is connected to the (k-6) th reset line RLk-6. The k-th reset pulse RPk from the second output terminal OUT2 of the k-th stage ST (k) is outputted to the (k-6) -th reset line RLk-6. The carry signal output terminal CARRY of the k-th stage ST (k) is connected to the reset terminal RESET of the (k-3) th stage ST (k- ) To the start terminal (START).

The voltages of the high potential voltage source VDD and the voltages of the first and second low potential potential sources VSS1 and VSS2 are supplied to the stages ST (1) to ST (n), respectively. The voltage of the high potential power source VDD may be set to the first gate high voltage VGH and the voltage of the first low potential potential source VSS1 may be set to the first gate low voltage VGL, And the voltage of the low potential voltage source VSS2 may be set to the second gate low voltage VGL '. In the present invention, the first gate high voltage VGH is approximately 28V, the first gate low voltage VGL is approximately -10V, and the second gate high voltage VGH ', which is lower than the first gate high voltage VGH, 15V and the second gate-low voltage VGL 'higher than the first gate-low voltage VGL may be set to approximately -5V. A detailed description of the internal circuits of each of the stages ST (1) to ST (n) will be described later with reference to FIG.

12 is a circuit diagram showing the k-th stage of Fig. 11 in detail. The circuit diagram of each of the stages ST (1) to ST (n) in Fig. 11 is substantially the same as the circuit diagram of the k-th stage ST (k).

12, the k-th stage ST (k) includes an initialization unit 10 for initializing a Q-node Q in response to a signal input through an initialization terminal INI, a start terminal START, A Q node controller 20 for controlling charging and discharging of the Q node Q in response to a signal input through a terminal RESET, a node controller 30 for controlling charging and discharging of the Q node, QB1 node, and QB2 node, And an output unit 40 for outputting a pulse according to the voltages of the nodes Q, QB1 and QB2.

The initialization unit 10 includes a fifteenth TFT (T15). The fifteenth TFT T15 initializes the Q node Q with the voltage of the first low potential potential source VSS1 in response to a signal input through the initialization terminal INI. The gate electrode of the fifteenth TFT T15 is connected to the initialization terminal INI, the source electrode thereof is connected to the Q node Q, and the drain electrode thereof is connected to the first low potential voltage source VSS1.

The Q node control unit 10 includes first and second TFTs T1 and T2. The first TFT (T1) charges the Q node (Q) with the voltage of the high potential voltage source (VDD) in response to the signal inputted through the start terminal (START). The gate electrode of the first TFT T1 is connected to the start terminal START, the source electrode thereof is connected to the high potential voltage source VDD, and the drain electrode thereof is connected to the Q node Q. The second TFT T2 discharges the Q-node Q to the voltage of the first low potential voltage source VSS1 in response to a signal input through the reset terminal RESET. The gate electrode of the second TFT T2 is connected to the reset terminal RESET, the source electrode thereof is connected to the Q node Q, and the drain electrode thereof is connected to the first low potential voltage source VSS1.

The node control unit 30 includes third and fourth TFTs T3 and T4 for controlling the Q node Q and a 10th to 14th TFTs T10 to T14 for controlling the QB1 node QB1, And the fifth to ninth TFTs T5 to T9 for controlling the QB2 node QB2.

The third TFT T3 discharges the Q node Q to the voltage of the first low potential voltage source VSS1 according to the voltage of the QB1 node QB1. The gate electrode of the third TFT T3 is connected to the QB1 node QB1, the source electrode thereof is connected to the Q node Q, and the drain electrode thereof is connected to the first low potential voltage source VSS1. The fourth TFT T4 discharges the Q node Q to the voltage of the first low potential voltage source VSS1 according to the voltage of the QB2 node QB2. The gate electrode of the fourth TFT T4 is connected to the QB2 node QB2, the source electrode thereof is connected to the Q node, and the drain electrode thereof is connected to the first low potential voltage source VSS1.

The fifth TFT T5 is diode-connected to apply the voltage of the even frame AC drive voltage source VDD_E to the first node N1. The gate electrode and the source electrode of the fifth TFT (T5) are connected to the well frame AC drive voltage source (VDD_E), and the drain electrode is connected to the first node (N1). The sixth TFT T6 switches the current path between the first node N1 and the first low potential voltage source VSS1 according to the voltage of the Q node Q. The gate electrode of the sixth TFT T6 is connected to the Q node Q, the source electrode thereof to the first node N1, and the drain electrode thereof to the first low potential voltage source VSS1. The seventh TFT T7 charges the QB2 node QB2 to the voltage of the even frame AC drive voltage source VDD_E in accordance with the voltage of the first node N1. The gate electrode of the seventh TFT T7 is connected to the first node N1, the source electrode thereof is connected to the source electrode of the fifth TFT T5, and the drain electrode thereof is connected to the QB2 node QB2.

The eighth TFT T8 discharges the QB2 node QB2 to the voltage of the first low potential voltage VSS1 according to the voltage of the Q node Q. [ The gate electrode of the eighth TFT T8 is connected to the Q node Q, the source electrode thereof to the QB2 node QB2 and the drain electrode thereof to the first low potential voltage source VSS1. The ninth TFT T9 discharges the QB2 node QB2 to the voltage of the first low potential voltage source VSS1 in response to the signal inputted through the start terminal START. The gate electrode of the ninth TFT T9 is connected to the start terminal START, the source electrode thereof is connected to the QB2 node QB2, and the drain electrode thereof is connected to the first low potential voltage source VSS1.

The tenth TFT (T10) is diode-connected to apply the voltage of the odd frame AC drive voltage source (VDD_O) to the second node (N2). The gate electrode and the source electrode of the tenth TFT (T10) are connected to the odd frame AC drive voltage source (VDD_O), and the drain electrode is connected to the second node (N2). The eleventh TFT T11 switches the current path between the second node N2 and the first low potential voltage source VSS1 according to the voltage of the Q node (Q). The gate electrode of the eleventh TFT T11 is connected to the Q node Q, the source electrode thereof to the second node N2, and the drain electrode thereof to the first low potential voltage source VSS1. The twelfth TFT T12 charges the QB1 node QB1 with the voltage of the odd frame AC drive voltage source VDD_O according to the voltage of the second node N2. The gate electrode of the twelfth TFT T12 is connected to the second node N2, the source electrode thereof is connected to the source electrode of the tenth TFT T10, and the drain electrode thereof is connected to the QB1 node QB1.

The thirteenth TFT (T13) discharges the QB1 node (QB1) to the voltage of the first low potential voltage (VSS1) in accordance with the voltage of the Q node (Q). The gate electrode of the thirteenth TFT T13 is connected to the Q node Q, the source electrode thereof to the QB1 node QB1, and the drain electrode thereof to the first low potential voltage source VSS1. The fourteenth TFT (T14) discharges the QB1 node (QB1) to the voltage of the first low potential voltage source (VSS1) in response to the signal inputted through the start terminal (START). The gate electrode of the fourteenth TFT T14 is connected to the start terminal START, the source electrode thereof is connected to the QB1 node QB1, and the drain electrode thereof is connected to the first low potential voltage source VSS1.

The output section 40 includes a carry signal output section 41, a gate pulse output section 42, and a reset pulse output section 43. The carry signal output section 41 includes a first pull-up TFT TU1 which is turned on in response to the voltage of the Q node Q to charge the first output node NO1 to a voltage input from the first clock terminal CLK1, A first pull-down TFT (TD1) which is turned on in accordance with the voltage of the QB1 node (QB1) to discharge the first output node (NO1) to the voltage of the first low potential voltage source (VSS1) And a second pull-down TFT (TD2) that is turned on according to the voltage to discharge the first output node NO1 to the voltage of the first low potential voltage source (VSS1).

The first pull-up TFT TU1 is turned on by the Q node Q of the voltage VGH " at a level higher than the first gate high voltage VGH due to the bootstrapping and is supplied from the first clock terminal CLK1 The first output node NO1 is charged with an input voltage to generate a carry signal. The gate electrode of the first pull-up TFT TU1 is connected to the Q node Q, the source electrode thereof is connected to the first clock terminal CLK1, and the drain electrode thereof is connected to the first output node NO1. The first pull-down TFT TD1 discharges the first output node NO1 to the voltage of the first low potential voltage source VSS1 according to the voltage of the QB1 node QB1. The gate electrode of the first pull-down TFT TD1 is connected to the QB1 node QB1, the source electrode thereof is connected to the first output node NO1, and the drain electrode thereof is connected to the first low potential voltage source VSS1. The second pull-down TFT (TD2) discharges the first output node NO1 to the voltage of the first low potential voltage source (VSS1) according to the voltage of the QB2 node (QB2). The gate electrode of the second pull-down TFT (TD2) is connected to the QB2 node (QB2), the source electrode thereof to the first output node (NO1), and the drain electrode thereof to the first low potential voltage source (VSS1).

The gate pulse output section 42 includes a second pull-up TFT TU2 that is turned on in accordance with the voltage of the Q node Q to charge the second output node NO2 to a voltage input from the first clock terminal CLK1, A third pull-down TFT (TD3) which is turned on in accordance with the voltage of the QB1 node (QB1) to discharge the second output node (NO2) to the voltage of the first low potential voltage source (VSS1) And a fourth pull-down TFT (TD4) that is turned on according to the voltage to discharge the second output node (NO2) to the voltage of the first low potential voltage source (VSS1).

The second pull-up TFT TU2 is turned on by the Q node Q of the voltage VGH " at a level higher than the first gate high voltage VGH due to bootstrapping and is supplied from the first clock terminal CLK1 And charges the second output node NO2 with an input voltage to generate a gate pulse GP. The gate electrode of the second pull-up TFT TU2 is connected to the Q node Q, the source electrode thereof to the first clock terminal CLK1, and the drain electrode thereof to the second output node NO2. The third pull-down TFT TD3 discharges the second output node NO2 to the voltage of the first low potential voltage source VSS1 according to the voltage of the QB1 node QB1. The gate electrode of the third pull-down TFT TD3 is connected to the QB1 node QB1, the source electrode thereof to the second output node NO2, and the drain electrode thereof to the first low potential voltage source VSS1. The fourth pull-down TFT (TD4) discharges the second output node (NO2) to the voltage of the first low potential voltage source (VSS1) in accordance with the voltage of the QB2 node (QB2). The gate electrode of the fourth pull-down TFT (TD4) is connected to the QB2 node (QB2), the source electrode thereof to the second output node (NO2), and the drain electrode thereof to the first low potential voltage source (VSS1).

The reset pulse output section 43 includes a third pull-up TFT TU3 that is turned on according to the voltage of the Q node Q to charge the third output node NO3 to a voltage input to the second clock terminal CLK2, A fifth pull-down TFT (TD5) which is turned on according to the voltage of the QB1 node (QB1) to discharge the third output node (NO3) to the voltage of the second low potential voltage source (VSS2) And a sixth pull-down TFT (TD6) that is turned on in response to the voltage to discharge the third output node (NO3) to the voltage of the second low potential voltage source (VSS2).

The third pull-up TFT TU3 is turned on by the Q node Q of the first gate high voltage VGH to charge the third output node NO3 with the voltage input from the second clock terminal CLK2 And generates a reset pulse RP. The gate electrode of the third pull-up TFT TU3 is connected to the Q node Q, the source electrode thereof to the second clock terminal CLK2, and the drain electrode thereof to the third output node NO3. The fifth pull-down TFT (TD5) discharges the third output node (NO3) to the voltage of the second low potential voltage source (VSS2) in accordance with the voltage of the QB1 node (QB1). The gate electrode of the fifth pull-down TFT (TD5) is connected to the QB1 node (QB1), the source electrode thereof to the third output node (NO3), and the drain electrode thereof to the second low potential voltage source (VSS2). The sixth pull-down TFT (TD6) discharges the third output node (NO3) to the voltage of the second low potential voltage source (VSS2) in accordance with the voltage of the QB2 node (QB2). The gate electrode of the sixth pull-down TFT (TD6) is connected to the QB2 node (QB2), the source electrode thereof to the third output node (NO3), and the drain electrode thereof to the second low potential voltage source (VSS2).

The threshold voltages of the first and second pull-up TFTs TU2 are set higher than the threshold voltage of the third pull-up TFT TU3. The first and second pull-up TFTs TU1 and TU2 are turned on in response to the first gate high voltage VGH while the third pull-up TFT TU3 is turned on in response to the first gate high voltage VGH. (VGH "). The semiconductor layers of the first to fourteenth TFTs T1 to T14, the first to third pull-up TFTs TU1 to TU3 and the first to sixth pull-down TFTs TD1 to TD6 are a-Si , Poly-Si, or an oxide semiconductor. The first through the seventeenth pull-down TFTs (Tl through T14), the first through third pull-up TFTs (TU1 through TU3), and the first through sixth pull- Type MOS-FET. However, the present invention is not limited to this, and it may be implemented as a P-type MOS-FET.

FIG. 13 is a waveform diagram showing input / output signals of the k-th and (k + 6) -th stages in the 2D mode and voltage changes of the Q-node, QB1-node, and QB2-node. 13, the start voltage VST input to the initializing terminal INI of each of the stages ST (1) to ST (n) and the start voltage VST input to the first clock terminal CLK1 6 clocks C1 to C6 and a DC voltage Vdc input to the second clock terminal CLK2. The voltage change of the Q node Q, QB1 node QB1 and QB2 node QB2 of the k stage (ST (k)) and the voltage change of the kth gate pulse ( And a k-th reset pulse RPk output from the second output terminal OUT2 are shown. Further, the voltage change of the Q node Q, the QB1 node QB1, and the QB2 node QB2 of the (k + 6) th stage ST (k + 6) a k-th gate pulse GPk, and a k-th reset pulse RPk output from the second output terminal OUT2.

Although the present invention has been described with reference to the case in which the i-phase clocks are implemented as the 6-phase clocks of the first to sixth clocks (C1 to C6) in FIG. 13, the present invention is not limited thereto. In addition, the start voltage VST, the first to sixth clocks C1 to C6 have a pulse width of 3 horizontal periods 3H, and the first to sixth clocks C1 to C6 have a pulse width of 2 horizontal periods 2H). However, it should be noted that the present invention is not limited to this.

Hereinafter, the operation of the k-th stage ST (k) and the (k + 6) th stage ST (k + 6) in the 2D mode will be described in detail with reference to Figs. 12 and 13. The output of the (k + 3) th stage ST (k-3) is input to the start terminal START of the k-th stage ST (k) 3) is input to the first clock terminal CLK1 and the fourth clock C4 is input to the first clock terminal CLK1. Also, the description has been made mainly on the fact that the k-th stage ST (k) operates in an odd frame. In the odd frame, the odd frame AC drive voltage VDD_O may be input at a first gate high voltage (VGH) level and the even frame AC drive voltage VDD_E may be input at a first gate low voltage (VGL) level. In this case, since the QB2 node QB2 is kept at the first gate low voltage (VGL) level, the TFTs TD2, TD4, TD6, and T4 to which the gate electrode is connected to the QB2 node QB2 continue to turn- Off state (i.e., maintained in the idle drive state).

During the period t1, the start voltage VST of the first gate high voltage VGH is input through the initialization terminal INI. The fifteenth TFT T15 is turned on in response to the start voltage VST of the first gate high voltage VGH so that the Q node Q is connected to the first low potential potential source VSS1. Thus, the Q node Q is discharged to the first gate low voltage VGL of the first low potential potential source VSS1.

During the period t2, since the start voltage VST is inverted to the first gate low voltage VGL, the fifteenth TFT T15 is turned off. The Q node Q maintains the first gate low voltage VGL.

During the period t3, the carry signal of the (k-3) th stage ST (k-3) of the first gate high voltage VGH is input via the start terminal START. The first TFT T1 is turned on in response to the carry signal of the k-3 stage ST (k-3) of the first gate high voltage VGH so that the Q node Q is turned on at the high potential voltage source VDD. Thus, the Q node Q is charged with the first gate high voltage VGH. The third pull-up transistor TU3 is turned on due to the charging of the Q node Q so that the DC voltage Vdc input to the second clock terminal CLK2 is supplied to the third output node NO3. Since the DC voltage Vdc of the second gate low voltage VGL 'is input to the second clock terminal CLK2 in the 2D mode, the reset pulse RP is outputted to the second gate low voltage VGL'.

The ninth TFT T9 is turned on in response to the carry signal of the k-3 stage ST (k-3) of the first gate high voltage VGH so that the QB2 node QB2 is turned on And is connected to the voltage source VSS1. Thus, the QB2 node QB2 is discharged to the first gate low voltage VGL. Since the fourteenth TFT T14 is turned on in response to the carry signal of the k-3 stage ST (k-3) of the first gate high voltage VGH, the QB1 node QB1 is turned on at the first low potential And is connected to the voltage source VSS1. Thus, the QB1 node QB1 is discharged to the first gate-low voltage VGL.

In addition, since the eighth and thirteenth TFTs T8 and T13 are turned on by charging the Q node Q, QB1 and QB2 nodes QB1 and QB2 are connected to the first low potential voltage source VSS1. Thus, QB1 and QB2 nodes QB1 and QB2 are discharged to first gate-low voltage VGL. Further, due to the charging of the Q node Q, the sixth and eleventh TFTs T6 and T11 are turned on. The fifth TFT T5 is turned off by the excellent frame AC driving voltage VDD_E of the first gate low voltage VGL and the odd frame AC driving voltage VDD_O of the first gate high voltage VGH is turned off. The tenth TFT (T10) is turned on. The first node N1 maintains the first gate low voltage VGL by connection with the first low potential potential source VSS1 due to turn-on of the sixth TFT T6. Therefore, the seventh TFT T7 is not turned on. The second node N2 is supplied with the odd frame AC drive voltage VDD_O of the first gate high voltage VGH due to the turn-on of the tenth TFT T10, Has a voltage level lower than the first gate high voltage (VGH) by connection with the first low potential potential source (VSS) due to the second gate potential. Therefore, the twelfth TFT T12 is not turned on.

During the period t4, the first TFT (T1), the ninth TFT (T9), and the fourteenth TFT (T14) maintain the turn-on state so that the Q node Q maintains the first gate high voltage VGH And QB1 and QB2 nodes QB1 and QB2 maintain the first gate-low voltage VGL. The kth reset pulse RPk of the second gate-low voltage VGL 'is output due to the turn-on of the third pull-up TFT TU3.

The fourth clock C4 from the first clock terminal CLK1 is input to the source electrode of the first pull-up TFT TU1. Therefore, the voltage of the Q node Q is bootstrapped by the parasitic capacitance between the gate and source electrodes of the first pull-up TFT TU1, thereby to be at a voltage level VGH " higher than the first gate high voltage VGH So that the first pull-up TFT TU1 is turned on. The voltage of the first output node NO1 rises to the first gate high voltage VGH, so that the carry signal of the first gate high voltage VGH is output.

A fourth clock C4 from the first clock terminal CLK1 is input to the source electrode of the second pull-up TFT TU2. Therefore, the voltage of the Q node Q is bootstrapped by the parasitic capacitance between the gate and source electrodes of the second pull-up TFT TU2, thereby to be at a voltage level VGH " higher than the first gate high voltage VGH And the second pull-up TFT TU2 is turned on. Since the voltage of the second output node NO2 rises to the first gate high voltage VGH, the kth gate pulse GPk of the first gate high voltage VGH is outputted.

During the period t5, the carry signal of the (k + 3) th stage (ST (k + 3)) of the gate high voltage VGH is input via the reset terminal RESET. The second TFT T2 is turned on in response to the carry signal of the (k + 3) th stage k + 3 of the gate high voltage VGH so that the Q node Q is turned on at the first low potential voltage source VSS1. Thus, the Q node Q is discharged to the first gate low voltage VGL.

The eighth and thirteenth TFTs T8 and T13 are turned off due to the discharge of the Q node Q so that the QB1 and QB2 nodes QB1 and QB2 are disconnected from the first low potential voltage source VSS1. In addition, the sixth and eleventh TFTs T6 and T11 are turned off due to the discharge of the Q node Q. The fifth node T5 is turned off by the strong frame AC driving voltage VDD_E of the first gate low voltage VGL so that the first node N1 maintains the gate low voltage VGL. Therefore, since the seventh TFT T7 is not turned on, the QB2 node QB2 maintains the first gate-low voltage VGL. The tenth TFT T10 is turned on in response to the first gate high voltage VGH in response to the odd frame AC drive voltage VDD_O so that the second node N2 is charged to the gate high voltage VGH. Therefore, since the twelfth TFT T12 is turned on, the QB1 node QB1 is charged to the gate high voltage VGH.

The first pull-down TFT (TD1) is turned on due to the charging of the QB1 node (QB1), so that the first output node (NO1) is connected to the first low potential voltage source (VSS1). Since the first output node NO1 falls to the first gate low voltage VGL, the carry signal of the first gate low voltage VGL is output. The third pull-down TFT (TD3) is turned on due to the charging of the QB1 node (QB1), so that the second output node (NO2) is connected to the first low potential voltage source (VSS1). Since the second output node NO2 falls to the first gate-low voltage VGL, the k-th gate pulse GPk of the first gate-low voltage VGL is output. Because the fifth pull-down TFT (TD5) is turned on due to the charging of the QB1 node (QB1), the third output node (NO3) is connected to the second low potential voltage source (VSS2). Since the third output node NO3 maintains the second gate low voltage VGL ', the kth reset pulse RPk of the second gate low voltage VGL' is output.

The operation of the k-th stage ST (k) during the period from t3 to t5 is substantially the same as the operation of the (k + 6) th stage ST (k + 6) during the period from t5 to t7. Therefore, the description of the operation of the (k + 6) th stage (ST (k + 6)) during the period from t5 to t7 is omitted.

14 is a waveform diagram showing input / output signals of the k-th and (k + 6) -th stages in the 3D mode and voltage changes of the Q-node, QB1-node, and QB2-node. 14, the start voltage VST input to the initialization terminal INI of each of the stages ST (1) to ST (n) and the start voltage VST input to the first clock terminal CLK1 6 clocks C1 to C6 and a DC voltage Vdc input to the second clock terminal CLK2. The voltage change of the Q node Q, QB1 node QB1 and QB2 node QB2 of the k stage (ST (k)) and the voltage change of the kth gate pulse ( And a k-th reset pulse RPk output from the second output terminal OUT2 are shown. Further, the voltage change of the Q node Q, the QB1 node QB1, and the QB2 node QB2 of the (k + 6) th stage ST (k + 6) a k-th gate pulse GPk, and a k-th reset pulse RPk output from the second output terminal OUT2.

Although the present invention has been described with reference to the case where the i-phase clocks are implemented as the six-phase clocks of the first to sixth clocks (C1 to C6) in FIG. 14, it should be noted that the present invention is not limited thereto. In addition, the start voltage VST, the first to sixth clocks C1 to C6 have a pulse width of 3 horizontal periods 3H, and the first to sixth clocks C1 to C6 have a pulse width of 2 horizontal periods 2H). However, it should be noted that the present invention is not limited to this.

14, the k-th reset pulse RPk occurs before the k-th gate pulse GPk, and is polled at the same time as the k-th gate pulse GPk. However, this is only one embodiment centered on the case of being implemented with six-phase clocks, and the kth reset pulse RPk occurs before the kth gate pulse GPk, and the kth gate pulse GPk is generated before the kth gate pulse GPk, May be polled after being polled.

The operation of the k-th stage ST (k) and the (k + 6) th stage ST (k + 6) k + 6)). However, since the third pull-up transistor TU3 is turned on due to the charging of the Q node Q during the period t3, the DC voltage Vdc input to the second clock terminal CLK2 is supplied to the third output node NO3 . The DC voltage Vdc of the second gate high voltage VGH 'is input to the second clock terminal CLK2 in the 3D mode so that the reset pulse RP of the second gate high voltage VGH' is output. The description of the operation of the k-th stage ST (k) and the (k + 6) th stage ST (k + 6) in the 3D mode is as described in Fig.

As described above, according to the present invention, the reset pulse RP supplied to the third scan TFT 222 of the second pixel 220 controlled by the black stripe is applied to the second gate 220, which is lower than the first gate high voltage VGH, And is polled to a second gate-low voltage VGL ', which occurs at a high voltage VGH' and is higher than the first gate-low voltage VGL. As a result, since the difference voltage between the second gate high voltage VGH 'and the second gate low voltage VGL' of the reset pulse RP is reduced, the second pixel 220 controlled by the black stripe, The kickback voltage can be reduced. Accordingly, the second pixel 220 controlled by the black stripe can display a perfect black gradation in the 3D mode. In addition, the present invention can reduce the crosstalk that occurs when the vertical viewing angle is widened by controlling the second pixel 220 in a black stripe in the 3D mode. Accordingly, the present invention can broaden the vertical viewing angle for viewing stereoscopic images.

Further, the present invention generates a gate pulse GP and a reset pulse RP in one stage ST. As a result, the present invention displays an image on the first pixel 210 displaying data in the 2D mode and the second pixel 220 controlled by the black stripe, without increasing the driving frequency of the shift register 50, It is possible to display an image on the first pixel 210 displaying data in the 3D mode and display the black gradation on the second pixel 220 controlled by the black stripe. Thus, the present invention can reduce the circuit cost of the shift register 50. Furthermore, since the number of circuits of the shift register 50 can be reduced, the circuit integration of the shift register 50 can be reduced and the reliability of the shift register 50 can be increased.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the present invention should not be limited to the details described in the detailed description, but should be defined by the claims.

10: display panel 20: polarizing glasses
30: pattern retarder 31: first retarder
32: second retarder 40: level shifter
50: shift register 60: printed circuit board
70: Source drive IC 110: Gate driver
120: Data driver 130: Timing controller
140: host system 200: pixel
210: first pixel 211: first scan TFT
220: second pixel 221: second scan TFT
222: Third scan TFT 240: First pixel electrode
250: common electrode 260: second pixel electrode

Claims (11)

delete A plurality of data lines, gate lines intersecting with the data lines, reset lines arranged side by side to the gate lines, and a plurality of sub-cells formed in a cell region defined by intersection of the data lines and the gate lines. A display panel including pixels;
A data driver for converting the input digital video data into a data voltage and outputting the data voltage to the data lines; And
And a shift register which sequentially outputs a gate pulse synchronized with the data voltage to the gate lines and sequentially outputs a reset pulse having a pulse width wider than the gate pulse to the reset lines,
The shift register includes:
(K is a natural number satisfying 1? K? N, n is the number of gate lines of the display panel) and outputs a k-th reset pulse to the reset line before the k-th reset line And a k-th stage for outputting,
In the 3D mode, the k-th gate pulse is generated at a first gate high voltage and is polled at a first gate low voltage, the k-th reset pulse occurring at a second gate high voltage lower than the first gate high voltage, A second gate-low voltage higher than the first gate-low voltage,
In the 2D mode, the k-th gate pulse is generated at the first gate high voltage and is polled at the first gate low voltage, and the k-th reset pulse maintains the second gate low voltage. Display device. 3. The method of claim 2,
Wherein in the 3D mode, the k-th reset pulse occurs before the k-th gate pulse and is polled simultaneously with the k-th gate pulse. 3. The method of claim 2,
Wherein in the 3D mode, the k-th reset pulse occurs before the k-th gate pulse and is polled after the k-th gate pulse is polled. 3. The method of claim 2,
Each of the sub-
A first pixel for displaying an image in the 2D and 3D modes by using a first scan TFT which supplies a data voltage of the data line to a first pixel electrode in response to a k-th gate pulse output from the k-th stage; And
A second scan TFT for supplying the data voltage to the second pixel electrode in response to the k-th gate pulse output from the k-th stage, and a second scan TFT for applying a common voltage And a second pixel for displaying the image in the 2D mode and displaying black gradation in the 3D mode by using a third scan TFT which supplies the second pixel electrode to the second pixel electrode, . 6. The method of claim 5,
The gate electrode of the first scan TFT is connected to the kth gate line, and the source electrode is connected to the data line of j (j is a natural number satisfying 1? J? M and m is the number of data lines of the display panel) And a drain electrode is connected to the first pixel electrode of the first pixel,
The gate electrode of the second scan TFT is connected to the kth gate line, the source electrode is connected to the jth data line, the drain electrode is connected to the second pixel electrode of the second pixel,
The gate electrode of the third scan TFT is connected to the reset line before the kth reset line, the source electrode is connected to the second pixel electrode of the second pixel, and the drain electrode is connected to the common line. Dimensional image display device. The method according to claim 6,
The first gate high voltage is set to be higher than the threshold voltages of the first and second scan TFTs, the first gate low voltage is set to be lower than the threshold voltages of the first and second scan TFTs, Is set to be higher than the threshold voltage of the third scan TFT and the second gate low voltage is set to be lower than the threshold voltage of the third scan TFT. 3. The method of claim 2,
The k < th >
A start terminal for receiving a carry signal of the previous stage from the kth stage; a reset terminal for receiving a carry signal of a stage after the kth stage; A second clock terminal for receiving a DC voltage, a carry signal output terminal for outputting a carry signal, a first output terminal for outputting a k-th gate pulse, And a second output terminal for outputting a k-th reset pulse. 9. The method of claim 8,
Wherein the direct current voltage is input to the second clock terminal at the second gate low voltage in the 2D mode and is input to the second clock terminal at the second gate high voltage in the 3D mode. 9. The method of claim 8,
And the i-phase clocks swing between the first gate high voltage and the second gate high voltage. 9. The method of claim 8,
The k < th >
An initialization unit for initializing a Q node in response to the start voltage inputted through the initialization terminal;
A Q node controller for charging the Q node in response to a carry signal of the front stage inputted through the start terminal and discharging the Q node in response to a carry signal of the rear stage inputted through the reset terminal;
A node controller for controlling charging and discharging of the Q node, the QB1 node, and the QB2 node; And
And an output unit for outputting a carry signal, a k-th gate pulse, and a k-th reset pulse in accordance with the voltages of the Q-node, the QB1-node, and the QB2-node.

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