KR101770550B1 - Driving method of display device - Google Patents

Abstract

The display device has a pixel array including a plurality of pixels arranged in a matrix and a backlight provided to face the substrate on which the pixel array is formed, and the display element portions and the optical sensor portions are formed in the pixels. In the display device, in one frame period for displaying a black image inserted between two consecutive periods for forming an image or in a backlighting stop period in one frame period for holding a display element-added image, An operation is performed, pixels are selectively selected for each row, and a signal corresponding to the potential of the signal charge storage portion of the photosensor portion is output.

Description

[0001] DRIVING METHOD OF DISPLAY DEVICE [0002]

Embodiments of the present invention relate to a display device in which pixels each having an optical sensor are arranged in a matrix, and a driving method of the display device. Further, an embodiment of the present invention relates to an electronic device including a display device.

Recently, a display device provided with a light-detecting sensor (also referred to as an optical sensor) has attracted attention. A touch panel, a touch screen, or the like (hereinafter, simply referred to as a "touch panel") can be used as a display device having an optical sensor in a display area, . This optical sensor provided in the display area allows the display area to be used also as an input area; As an example, a semiconductor device having an image loading function is disclosed in Patent Document 1.

Japanese Laid-Open Patent Application No. 2001-292276

A display device including such an optical sensor recognizes the fingertip or the shade of the pen tip near the display area and functions as a touch panel. However, when the display device includes a backlight, the light transmitted from the backlight is reflected at the fingertip or the pen tip, and the light sensor often detects the reflected light.

In the case of external light having high illuminance, it is easy to recognize the shade of the fingertip, the pen tip, and the like with respect to the optical sensor. However, in the case of external light having a low illuminance, the difference between the intensities of the light and the external light emitted from the backlight and reflected is insufficient, and the optical sensor can not recognize the shade such as the fingertip, the pen tip, The performance of the display device is insufficient.

Therefore, the embodiment of the present invention disclosed in this specification is a method of driving a display device or a display device capable of solving the above problems.

An embodiment of the present invention disclosed in this specification relates to a display device that recognizes the shade of an object to be detected by an optical sensor included in a display area when the backlight is turned off.

An embodiment of the present invention disclosed in this specification relates to a pixel array including a plurality of pixels provided in a matrix form, display element portions included in pixels, optical sensor portions included in pixels, and a substrate on which a pixel array is formed Is a display device having a backlight that is provided to face the display device. In the display device, the photosensor section accumulates charges for all of the pixels within a period in which the backlight is turned off.

The charge accumulation operation of the photosensor section is performed during the period of backlight shutoff, and not during the other periods. Thus, the light sensor does not detect the light that is emitted from the backlight and is reflected, and therefore, the shadow of the object to be detected generated by the external light can be accurately recognized. Here, the backlighting stop period is a portion of one frame period in which the display element portion retains the image.

An embodiment of the present invention disclosed in this specification is a display device having a pixel array including a plurality of pixels provided in a matrix form, display element portions included in pixels, and optical sensor portions included in pixels. In the display device, the photosensor section accumulates charge by using all the pixels within a period in which the display element section displays a black image.

Here, the display of the black image and the display of the main image are alternately performed. The "main image" is an image intentionally displayed by a user of the display device; For example, it should be noted that there are images of television programs and images recorded on a recording medium.

An embodiment of the present invention disclosed in this specification relates to a pixel array including a plurality of pixels provided in a matrix form, display elements included in the pixels, photosensors included in the pixels, and a substrate on which the pixel array is formed A method of driving a display device having a backlight provided to face a display device. The display device performs the following operations: turns on the backlight, displays an image on the display element portion, turns off the backlight, resets the potential of the signal charge storage portion of the photosensor portion, And outputs a signal corresponding to the potential of the signal charge storage portion of the photosensor portion after the pixels are successively selected for each row. The charge stored in the signal charge storage portion of the photosensor portion is retained, and the backlight is turned on.

Here, the operation from turning off the backlight to outputting the signal is performed within one frame period in which the display element retains the image, whereby the accumulation operation of the photosensor can be performed in all the frame periods .

An embodiment of the present invention disclosed in this specification is a driving method of a display device having a pixel array including a plurality of pixels provided in a matrix form, display element portions included in pixels, and optical sensor portions included in pixels . The display device performs an operation of displaying an image on the display element portion and displaying a black image on the display element portion. During the period in which the black image is displayed on the display element portion, the display device performs the following operation: resets the potential of the signal charge storage portion of the photosensor portion, accumulates charge in the signal charge storage portion of the photosensor portion, Holds the charge of the signal charge storage portion, and outputs a signal corresponding to the potential of the signal charge storage portion of the photosensor portion after the pixels are successively selected for each row.

Here, the display of the main image and the display of the black image with respect to the display element portion are performed alternately. Further, since the black image is displayed for a period of one frame or less or the backlight is turned off, the display device can have the effect of reducing the afterimages of the moving image.

According to the embodiment of the present invention, since the light sensor unit detects a small amount of light emitted from the backlight and reflected on the object to be detected, the light sensor can accurately recognize the shade generated by the external light. Therefore, a high-resolution touch panel can be provided.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a diagram showing a structure of a display device in which both a display element and an optical sensor are provided in a display area. Fig.
2 is a circuit diagram showing a structure of a display device including both a display element and an optical sensor in a display area.
Figures 3a and 3b are timing diagrams of operations of the optical sensor.
4 is a timing diagram of the operations of the optical sensor.
5 is a timing diagram of the operations of the optical sensor.
6 is a timing diagram of the operations of the optical sensor.
7A to 7C are views showing examples of imaging of a rolling shutter system and a global shutter system, respectively.
Figures 8A-8E illustrate scientific calculations.
9 is a diagram showing a circuit structure of a pixel of an optical sensor;
10 is a diagram showing a circuit structure of a pixel of an optical sensor;
11 is a diagram showing a circuit structure of a pixel of an optical sensor;
12A and 12B are timing charts showing the operation of the pixel circuit of the optical sensor, respectively.
13 is a diagram showing a circuit structure of a pixel of an optical sensor;
14A and 14B are timing charts showing the operation of the pixel circuit of the optical sensor, respectively.
15 is a diagram showing a circuit structure of a pixel of an optical sensor;
16A and 16B are timing charts showing the operation of the pixel circuit of the optical sensor, respectively.
17 is a diagram showing a circuit structure of a pixel of an optical sensor;
18 is a timing chart showing the operation of the pixel circuit of the optical sensor;
19 is a diagram showing a circuit structure of a pixel of a photosensor;
20 is a timing chart showing the operation of the pixel circuit of the optical sensor;
21 is a cross-sectional view of a display device including both a display element and an optical sensor in a display area;
22 is a cross-sectional view of a display device including both a display element and an optical sensor in a display area;
23 is a cross-sectional view of a display device including both a display element and an optical sensor in a display area.
24 is a cross-sectional view of a display device including both a display element and an optical sensor in a display area.
25 is a view showing a specific example of an electronic device;
26 is a view showing a structure of a display device;
27A to 27D are views showing specific examples of electronic devices, respectively.
28 is a diagram showing a circuit structure of a pixel of an optical sensor;
29 is a diagram showing a circuit structure of a pixel of an optical sensor;

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, it is not intended that the present invention be limited to the following description, and that those skilled in the art will readily appreciate that the forms and details disclosed herein may be modified in various ways without departing from the spirit and scope of the invention. Accordingly, the present invention is not construed as being limited to the description of the embodiments. In the drawings for illustrating the embodiments, it is to be noted that portions having the same or similar functions are denoted by the same reference numerals, and description of the portions is not repeated.

(Embodiment 1)

In this embodiment, a transmissive liquid crystal display device having a backlight which is an embodiment of the present invention is described with reference to the drawings. Fig. 1 shows an example of the structure of a transmissive liquid crystal display device.

The display device 100 includes a pixel array 101, a display element control circuit 102, and an optical sensor control circuit 103. The pixel array 101 includes a plurality of pixels 104 arranged in a matrix. Each pixel 104 includes, for example, a display element portion 105 and a photosensor portion 106. [

The photosensor section 106 is provided for imaging, but it is not necessary to provide the photosensor section to all the pixels. The optical sensor units may be formed according to purposes.

The display element control circuit 102 shown in Fig. 1 is a circuit for controlling the display element parts 105 and inputs signals to the display element parts 105 through source signal lines (such as video-data signal lines) And a display element driving circuit 108 for inputting a signal to the display element units 105 through gate signal lines (scanning lines).

For example, the display element driving circuit 108 connected to the scanning line has a function of selecting a display element included in a pixel located in a specific row. Further, the display element driving circuit 107 connected to the signal line has a function of applying a predetermined potential to the display element included in the pixel located in the selected row. It should be noted that, in the display element portion to which the high potential is applied to the gate signal line from the display element driving circuit 108, the transistor is turned on and the potential applied to the source signal line from the display element driving circuit 107 is supplied to the display element portion do.

The optical sensor control circuit 103 is a circuit for controlling the optical sensor unit 106 and is a circuit for controlling the light of the signal lines such as an optical sensor output signal line (hereinafter referred to as an output signal line), an optical sensor reference signal line A sensor reading circuit 109, and an optical sensor driving circuit 110 of scanning lines such as a reset signal line, a row selection gate signal line (hereinafter referred to as a selection signal line), and the like.

The optical sensor drive circuit 110 has a function of performing a reset operation, a storage operation, and a selection operation described below with respect to the optical sensor unit 106 included in each of the pixels in a specific row. Further, the optical sensor reading circuit 109 has a function of extracting the output signals of the optical sensor units included in the selected pixels in the row. The optical sensor reading circuit 109 is a system in which an analog signal output from the optical sensor units is extracted as an analog signal to the outside by an OP amplifier; Or that the output is converted to a digital signal by the A / D converter circuit and then extracted to the outside.

A circuit diagram of the pixel 104 is described with reference to Fig. It should be noted that the transistors and wirings in this embodiment are conveniently named. Any of the nomenclature is acceptable provided that the functions of the transistors and wirings are described.

First, the display element portion 105 is described.

One of the source and the drain of the transistor 201 is electrically connected to the source signal line 216 and the other of the source and the drain of the transistor 201 is connected to the source signal line 216. The gate of the transistor 201 is electrically connected to the gate signal line 215, One of which is electrically connected to one of the electrodes of the holding capacitor 202 and one of the electrodes of the liquid crystal element 203. [ The other electrode of the holding capacitor 202 and the other electrode of the liquid crystal element 203 are each held at a predetermined potential. The liquid crystal element 203 is an element including a liquid crystal layer provided between a pair of electrodes.

The transistor 201 has a function of controlling the charging or discharging of electric charge to / from the holding capacitor 202. For example, when a high potential is applied to the gate signal line 215, the potential of the source signal line 216 is applied to the holding capacitor 202 and the liquid crystal element 203. [ The holding capacitor 202 has a function of holding a charge corresponding to a voltage applied to the liquid crystal element 203. [

The image display is realized in such a manner that the contrast (gray scale) of light passing through the liquid crystal element 203 is achieved by using a phenomenon in which the polarization direction is changed by applying a voltage to the liquid crystal element 203. [

Although a semiconductor layer such as amorphous silicon, microcrystalline silicon, polycrystalline silicon and the like can also be used, it is preferable that an oxide semiconductor is used for the transistor 201. [ For a transistor comprising an oxide semiconductor, it exhibits extremely low off-state current characteristics; Therefore, the function of holding the charge can be improved.

Next, the optical sensor unit 106 is described.

The photodiode 204 generates a current in accordance with the amount of light incident on the pixel. The amplifying transistor 207 outputs a signal corresponding to the potential of the signal charge storage section 210 (FD). The charge storage control transistor 205 controls the charge accumulation in the signal charge storage portion 210 performed by the photodiode 204. [ The reset transistor 206 controls the initialization of the potential of the signal charge storage part 210. [ The selection transistor 208 controls the selection of the pixel upon reading. The signal charge storage portion 210 is a charge holding node, and changes depending on the amount of light received by the photodiode 204 holds the charge.

The charge storage control signal line 213 is a signal line for controlling the charge storage control transistor 205. The reset signal line 214 is a signal line for controlling the reset transistor 206. The selection signal line 209 is a signal line for controlling the selection transistor 208. The output signal line 211 is a signal line serving as an output destination of the signal generated by the amplifying transistor 207. The power supply line 230 is a signal line for supplying a power supply voltage. The reference signal line 212 is a signal line for setting the reference potential.

The gate of the charge accumulation control transistors 205 is connected to the charge accumulation control signal line 213 and one of the source and the drain of the charge accumulation control transistors 205 is connected to the cathode of the photodiode 204, And the other of the drains is connected to the signal charge storage portion 210. Further, the anode of the photodiode 204 is connected to the reference signal line 212. Here, the charge holding capacitor may be connected between the signal charge storage portion 210 and the reference signal line 212.

The substantial signal charge storage portion is the capacitance of the depletion layer near the source region or drain region of the transistor, the gate capacitance of the amplification transistor, etc.; It should be noted that the signal charge storage section is described herein for convenience as part of the circuit diagram. Therefore, the description of the layout should follow the circuit diagram.

One of the source and the drain of the amplification transistor 207 is connected to the power supply line 230 and the source and the drain of the amplification transistor 207 are connected to the signal charge storage section 210. [ And the other is connected to one of the source and the drain of the selection transistor 208. [

One of the source and the drain of the reset transistor 206 is connected to the power supply line 230 and the other of the source and the drain of the reset transistor 206 is connected to the reset signal line 214, Is connected to the signal charge storage section 210. [

The gate of the selection transistor 208 is connected to the selection signal line 209 and the other of the source and the drain of the selection transistor 208 is connected to the output signal line 211.

Next, the structure of each element of the optical sensor unit 106 is described.

The photodiode 204 may be formed using a silicon semiconductor having a PN junction or a PIN junction. Here, a PIN photodiode in which an i-type semiconductor layer is formed using amorphous silicon is used. Since the amorphous silicon has light absorptivities in the visible light wavelength range, there is no need to provide an infrared cut filter; Therefore, amorphous silicon can be formed at a low cost. In contrast, when the i-type semiconductor layer of the PIN photodiode is formed using crystalline silicon and is combined with an infrared ray transmission filter, only infrared rays are incident on the infrared ray transmission filter, because the crystalline silicon has light absorptances in the infrared wavelength region outside the visible light wavelength region Can be detected.

The charge accumulation control transistor 205, the reset transistor 206, the amplification transistor 207, and the selection transistor 208 may also be formed using a silicon semiconductor, but they are preferably formed using an oxide semiconductor. A transistor including an oxide semiconductor has a very low off-state current.

In particular, if the charge accumulation control transistor 205 and the reset transistor 206 connected to the signal charge storage section 210 have a large leakage current, the time for which the charge can be retained in the signal charge storage section 210 is sufficient without doing; Therefore, it is preferable that at least the transistors are formed using an oxide semiconductor. When a transistor including an oxide semiconductor is used for transistors, leakage of unwanted charge through the transistor can be prevented.

In the oxide semiconductor, a thin film which is represented by the formula _{InMO 3 (ZnO) m (m} > 0) can be used. Here, M represents one or more metal elements selected from Zn, Ga, Al, Mn and Co. For example, M may be Ga, Ga and Al, Ga and Mn, Ga and Co, and the like. Since the transistor is formed using an oxide semiconductor, the off-state current can be extremely reduced.

Next, a precharge circuit included in the optical sensor readout circuit 109 is described. In Fig. 2, the precharge circuit 300 for one column of pixels includes a transistor 301, a holding capacitor 302, and a precharging signal line 303. Fig. Here, a p-channel transistor is used as the transistor 301. [ It should be noted that the OP amplifier or the A / D converter circuit may be connected to the subsequent stage of the precharge circuit 300.

In the precharge circuit 300, the potential of the output signal line 211 is set to the reference potential before the operation of the photosensor section of the pixel. 2, the potential of the output signal line 211 can be set to the reference potential (here, high potential) by setting the potential of the precharge signal line 303 to a low level so that the transistor 301 is turned on. The holding capacitor 302 is provided to the output signal line 211 so that the potential of the output signal line 211 is stabilized. It should be noted that if the output signal line 211 has a large parasitic capacitance, the holding capacitor 302 is not necessarily required. It should be noted that the reference potential may be set to a low potential. In this case, the potential of the precharge signal line 303 is set to the high level by using the n-channel transistor as the transistor 301, whereby the potential of the output signal line 211 can be set to the low potential.

Next, with reference to the timing charts of Figs. 3A and 3B, the read operations of the optical sensor provided in the display device of this embodiment will be described.

The potential 513 of the charge storage control signal line 213, the potential 514 of the reset signal line 214, the potential 509 of the selection signal line 209, the signal charge storage portion 210, The potential 511 of the output signal line 211 and the potential 503 of the precharge signal line 303 are shown in order from the top.

First, the operation mode according to Fig. 3A is described.

When the potential 513 of the charge accumulation control signal line 213 is set to the high level in the time 231 and the potential 514 of the reset signal line 214 is set to the high level in the time 232, The potential 510 of the portion 210 is initialized to the potential of the power supply line 230 and becomes a reset potential. This is the beginning of the reset operation.

When the potential 503 of the precharge signal line 303 is set to a low level, the potential 511 of the output signal line 211 is precharged to a high level.

The potential 514 of the reset signal line 214 is set to the low level at the time 233, and the reset operation is ended. At this time, the potential 510 of the signal charge storage portion 210 is held, and a reverse bias voltage is applied to the photodiode 204. [ This step is the start of the accumulation operation. Then, a reverse current corresponding to the light amount flows in the photodiode 204, and the potential 510 of the signal charge storage portion 210 changes.

Subsequently, the potential 503 of the precharge signal line 303 is set to a high level, and the precharge of the output signal line 211 is terminated. Precharging can be terminated any time before the selection transistor 208 is turned on.

When the potential 513 of the charge storage control signal line 213 is set to the low level in the time 234, the movement of the charge from the signal charge storage portion 210 to the photodiode 204 is stopped, do. In addition, the potential 510 of the signal charge storage portion 210 is held at a specific value.

When the potential 509 of the selection signal line 209 is set to the high level in the time 235, the selection operation is started and the potential 511 of the output signal line 211 changes in accordance with the potential 510 of the signal charge storage portion .

The potential 511 of the output signal line 211 has a specific value when the potential 509 of the selection signal line 209 is set to the low level at the time 236. [ In this step, the selecting operation and the reading operation are ended. Thereafter, the operation at time 231 is performed and the same operations are repeated, so that a sensed image can be formed.

Next, the operation mode according to Fig. 3B is described.

When the potential 513 of the charge storage control signal line 213 is set to the high level in the time 231 and the potential 514 of the reset signal line 214 is set to the high level in the time 232, The potential 510 of the portion 210 and the potential of the cathode of the photodiode 204 are initialized to the potential of the power supply line 230 to be the reset potential. This is the beginning of the reset operation.

When the potential 503 of the precharge signal line 303 is set to a low level, the potential 511 of the output signal line 211 is precharged to a high level.

When the potential 513 of the charge storage control signal line 213 is set to the low level in the time 237 and the potential 514 of the reset signal line 214 is set to the low level in the time 238, End; Therefore, a reverse current corresponding to the amount of light flows to the photodiode 204 to which the reverse bias is applied, so that the potential of the cathode of the photodiode 204 changes.

When the potential 513 of the charge storage control signal line 213 is set to the high level in the time 233, the potential difference between the potential 510 of the signal charge storage portion 210 and the cathode of the photodiode 204 causes the current And the potential 510 of the signal charge storage portion 210 changes.

The subsequent steps are the same as the operation mode according to FIG.

The reset operation, the accumulation operation, and the selection operation are sequentially repeated for each row of the pixel matrix, and the output from each pixel is read, whereby the object to be detected, which is touched or near to the display panel, can be picked up.

The series of operations is an example in which the cathode of the photodiode 204 is connected to one of the source and the drain of the charge accumulation control transistor 205. [ This operation of generating the output signal can also be performed when the anode of the photodiode 204 is connected to one of the source and the drain of the charge accumulation control transistor 205. [

According to the above series of operations, the potential 510 of the signal charge storage portion 210 is initialized to a high level and discharged by the reverse current generated by light irradiated to the photodiode 204, and the amplification transistor 207 The output signal is determined.

On the other hand, when the photodiode 204 is reversely connected, the potential 510 of the signal charge storage portion 210 is initialized to a low level and charged with a reverse current generated by transferring light to the photodiode 204, The output signal is determined through the amplifying transistor 207.

As a system of accumulation and read operations in all pixels, the following two systems are known: a rolling shutter system and a global shutter system. In an embodiment of the present invention, a rolling shutter system may also be employed; A global shutter system is preferably used.

An image can be picked up without distortion by the global shutter system, especially when the object moves at high speed, because the accumulation operation can be performed substantially simultaneously on all pixels. It is preferable that the object also moves in the case of the touch panel and that a global shutter system is used to obtain accurate position information in the display area.

A display device including an optical sensor described in this embodiment has a CMOS sensor type system in which pixel signals are sequentially read out for each row. Thus, when the global shutter system is used, the periods from the end of the accumulation operation to the start of the selection operation differ depending on the pixels. Also, the longer the charge retention period, the worse the signal due to the outflow of charge, and in some cases the image can not be captured normally.

However, in the embodiment of the present invention, a transistor including an oxide semiconductor is used for the transistor connected to the signal charge storage portion for accumulating charge, so that the outflow of the charge can be suppressed as much as possible. As described above, a transistor including an oxide semiconductor exhibits an extremely low off-state current; Thus, irrespective of the amount of light transmitted to the photodiode, leakage of unwanted current can be prevented. Thus, the global shutter system can be easily driven.

A display device in an embodiment of the present invention is a transmissive liquid crystal display device having a backlight. Thus, the light sensor detects light that is emitted from the backlight and that reflects the object to be detected, and often does not recognize the shadow of the object.

In order to solve this problem, in the embodiment of the present invention, the backlight is stopped and the accumulation operation of the photosensor is performed during the stop period. By the driving method, the optical sensor does not detect the light emitted from the backlight and reflected to the object, thereby preventing the touch panel from being misidentified.

Here, in order not to deteriorate the performance of the display device, it is preferable that the backlighting stop period is very short. The backlighting stop is performed in a portion of one frame period in which the display element portion retains the image. In order to perform the accumulation operation of the optical sensor within a very short time, the global shutter system is more preferable. Rolling shutter systems can also be used, but it should be noted that images need to be captured at high speed in order to prevent the backlighting suspension period from becoming long.

In addition, stopping backlighting can provide an effect of improving the display characteristics of the display device.

The liquid crystal display device has a problem that a residual image occurs when a moving image is displayed. As a method for improving the moving picture characteristics of a liquid crystal display device, a driving technique called a black frame insertion is known, wherein black is displayed on the entire screen every other frame period or in a part of one frame period.

The driving method of the liquid crystal element is a hold type, and the same image is held for one frame period. Thus, the human eye will see the same image until just before the next frame arrives, thereby recognizing the after-images. One way to remove the residual images is a black frame insertion technique in which a black image is inserted to remove afterimages.

One specific method of black frame insertion is backlighting stop. Therefore, in the embodiment of the present invention, the misalignment of the touch panel can be prevented, and the moving picture display characteristics can be improved.

By the method of displaying a black image for one frame period, the accumulation operation of the photosensor may be performed during this period. In this case, backlighting stop is not necessary. Since a small amount of backlight passes through the liquid crystal element when displaying a black image, light emitted from the backlight and reflected to the object is not generated during the frame period. Therefore, misalignment of the touch panel can be prevented by performing the accumulation operation of the photosensor within the frame period in which the black image is displayed. The black image and the main image are alternately displayed, whereby the effect of black frame insertion as described above can be obtained; Therefore, it should be noted that moving picture display characteristics can be improved.

Next, the imaging operation of the display apparatus including the photosensor section 106 of FIG. 2 including the backlighting stop operation will be described with reference to the timing chart of FIG. It should be noted that the imaging operation is driven in the global shutter system but can also be driven in the rolling shutter system.

First, the backlight is turned off at time 4721 or before time 4721.

When the potentials 4701 to 4705 of all the lines of the first charge accumulation control signal line to the n-th charge accumulation control signal line are simultaneously set to the high level, the accumulation operation of the pixels in the first row to the n- do.

When the potentials 4701 to 4705 of all the lines of the first charge accumulation control signal line through the n-th charge accumulation control signal line are simultaneously set to the low level at the time 4722, Is completed.

Then, the backlight is turned on. Here, the period 4720 during which the backlight is stopped may be acceptable if the period 4720 includes at least a period from the time 4721 to the time 4722, and may include a period of the next reading operation.

When the potential 4711 of the first selection signal line is set to the high level in the time 4723, the operation of reading the pixels of the first row is started.

When the potential 4711 of the first selection signal line is set to the low level and the potential 4712 of the second selection signal line is set to the high level in the time 4724, the operation of reading the pixels of the first row is completed The operation of reading the pixels of the second row is started.

When the potential 4712 of the second selection signal line is set to the low level and the potential 4713 of the third selection signal line is set to the high level in the time 4725, the operation of reading the pixels of the second row is completed The operation of reading the pixels of the third row is started.

When the potential 4713 of the third selection signal line is selected to the low level in the time 4726, the operation of reading the pixels of the third row is completed.

When the potential 4714 of the (n-1) th selection signal line is set to the high level in the time 4727, the operation of reading the pixels of the (n-1) th row is started.

When the potential 4714 of the (n-1) th selection signal line is set to the low level and the potential 4715 of the n-th selection signal line is set to the high level in the time 4728, The operation of reading the pixels of the n-th row is completed and the operation of reading the pixels of the n-th row is started.

When the potential 4715 of the n-th selection signal line is set to the low level in the time 4729, the operation of reading the pixels of the n-th row is completed. Thereafter, the operation at the time 4721 is performed and the same operations are repeated, so that a display device of a high-resolution image pickup can be provided.

Through the above steps, in the embodiment of the present invention, the global shutter system is used and the backlight is stopped during the accumulation operation of the optical sensor, so that the object can be detected more accurately. In addition, by the method of stopping the backlighting, the accumulation operation of the photosensor can be performed in all successive frames and the perception accuracy of the touch panel can be improved.

In addition, the object can be detected more accurately by performing the accumulation operation of the photosensor within the frame period in which the black image is displayed. In this case, the operation is similar to the operation described with reference to FIG. 4, but a backlighting stop is not required. This method is also effective for driving a rolling shutter system with a long accumulation time.

In addition, the insertion of the backlighting stop or the black image display can provide the display device with a so-called black frame insertion effect, whereby the moving image display characteristics can be improved.

This embodiment can be implemented in appropriate combination with any other embodiment or example.

(Embodiment 2)

In this embodiment, systems of the accumulation operation and the read operation of the imaging apparatus are described. It should be noted that the display device of the embodiment of the present invention includes the functions of the optical sensor part and the imaging device.

As a system of accumulation and readout operations of an imaging device, the following two systems are known: a rolling shutter system and a global shutter system. Differences between these systems are briefly described using the potential of the charge accumulation control signal line and the potential of the selection signal line.

5 is a timing chart when a rolling shutter system is used. First, the potential 3001 of the first charge accumulation control signal line is set to a high level, and the charge corresponding to the light amount is accumulated in the signal charge accumulation portion of the pixel of the first row in the accumulation period 311. [ Next, the potential 3001 of the first charge accumulation control signal line is set to a low level, and after the charge retention period 312, the potential 3501 of the first select signal line is set to a high level. After the voltage corresponding to the storage potential is read in the period 313, the potential 3501 of the first selection signal line is set to a low level.

In the period 313, the potential 3002 of the second charge accumulation control signal line is set to a high level, and the charge corresponding to the light amount is accumulated in the signal charge accumulation portion of the pixel of the second row. Next, the potential 3002 of the second charge accumulation control signal line is set to a low level, and after the charge retention period 314, the potential 3502 of the second select signal line is set to a high level. After the voltage corresponding to the storage potential is read in the period 315, the potential 3502 of the second selection signal line is set to a low level.

Likewise, when the last row is, for example, the 480th row, the potentials from the potential 3003 of the third charge storage control signal line to the potential 3480 of the 480th charge storage control signal line and the potential of the third select signal line ( 3503 to the potential 3980 of the 480th charge accumulation control signal line are sequentially controlled, thereby performing a read operation in all the pixels. In this manner, reading of one frame is completed.

In a rolling shutter system, charge accumulation for a signal charge storage portion of a pixel is performed for each row; Therefore, the timing of charge accumulation differs from row to column. In other words, the rolling shutter system is a system in which the accumulation operation of the charge is not performed at all the pixels at the same time, but the time difference of the accumulation operation occurs every row. It should be noted that the charge retention period from the accumulation operation to the read operation is the same in all rows.

Next, the global shutter system is described using the timing diagram of Fig. Similarly to the above example, when the last row is the 480th row, potentials from the potential 4001 of the first charge storage control signal line in the first row to the potential 4480 of the 480th charge storage control signal line in the 480th row Are simultaneously set to the high levels, whereby the accumulation operation of the charge is simultaneously performed in all the pixels in the period 401. [ In the period 403 after the charge retention period 402, the potential 4501 of the first selection signal line is set to a high level, the pixels of the first row are selected, and a voltage corresponding to the accumulated potential is output.

Next, the potential 4501 of the selection signal line is set to a low level. In the period 405 after the charge retention period 404, the potential 4502 of the second selection signal line is set to the high level, the pixel of the second row is selected, and the voltage corresponding to the accumulated potential is output.

Thereafter, the reading of each row is performed sequentially. In the last row, the potential of the 480th selection signal line 4980 is set to the high level after the charge retention period 406, the pixel of the 480th row is selected, and the voltage corresponding to the accumulated potential is output. In this way, reading of one frame is completed.

In the global shutter system, the timing of charge accumulation with respect to the signal charge storage portion is the same in all pixels. It should be noted that the time period from the charge accumulation operation to the read operation varies from row to row and the charge retention period 406 to the reading of the last row is the longest.

As described above, since the global shutter system has no time difference in charge accumulation in all the pixels, there is an advantage that the image can be captured without distortion to the moving object. However, the charge retention period is longer; Therefore, compared with the rolling shutter system, there is a problem that the sensor is easily affected by the leakage due to the off-state current of the charge accumulation control transistor or the reset transistor or the like.

Next, examples of imaging using a rolling shutter system and a global shutter system are described with reference to Figs. 7A to 7C. Here, as an example of the case where the object moves fast, it is considered that an image of a moving car is picked up as shown in Fig. 7A.

When a rolling shutter system is used, the timing of the charge accumulation of the pixels differs from row to row; Thus, the imaging of the upper portion of the image and the imaging of the lower portion of the image can not be performed at the same time, and the image is generated as a distorted object, as shown in Fig. 7B. In a rolling shutter system, the distortion of the picked-up image is particularly increased when a fast-moving object is perceived; Therefore, it is difficult to capture an image of the actual shape of the object.

Conversely, when the global shutter system is used, the charge accumulation timing of the pixel is the same in all the pixels. Thus, the entire image can be instantaneously captured; Thus, a distortion-free image can be picked up as shown in Fig. 7C. The Global Shutter System is an excellent system for capturing images of fast-moving objects.

As described above, it has been found that a global shutter system, rather than a rolling shutter system, is suitable for capturing images of fast-moving objects. It should be noted that, due to the large off-state current of conventional transistors including silicon semiconductors, a normal image can not be imaged by simply changing from a rolling shutter system to a global shutter system in a CMOS image sensor.

In order to solve this problem, it is preferable that a transistor having a low off-state current is used for the transistor connected to the signal charge storage portion. As a transistor having an extremely low off-state current, a transistor including an oxide semiconductor or the like is provided.

Next, the scientific calculation results for the image are described. The object used for the scientific calculation is an image with three blades acting as the rotor shown in Figure 8A. These three blades can be rotated using the connection point as a central axis. This scientific calculation aims at obtaining an image for one frame when an image of three rotating blades is picked up.

The software used for the scientific calculation is image processing software written in the C language. In order to make an image, the charge accumulation operation in each pixel of the image sensor and the timing of the read operation and the amount of leakage from the signal charge accumulation portion per row are calculated .

Figures 8b-8e show scientific calculation results. It should be noted that the scientific calculation results were performed under the following four conditions.

The first condition is a VGA image sensor (light sensor) that has the pixel circuit shown in Fig. 28 and drives the rolling shutter system. In the pixel circuit structure of Fig. 28, the charge accumulation control transistor 803, the reset transistor 804, the amplification transistor 802, and the selection transistor 805 are transistors including a silicon semiconductor.

The second condition is a VGA image sensor having the pixel circuit of Fig. 28 and driving the global shutter system. The structure of the circuit is the same as the first condition, and only the shutter system is different.

The third condition is a VGA image sensor that has the pixel circuit of Fig. 29 and drives the rolling shutter system. The pixel circuit structure of FIG. 29 is basically the same as the pixel circuit of the photosensor section 106 of FIG. 2, except that the charge storage control transistor 903 and the reset transistor 904 are transistors including an oxide semiconductor, The selection transistor 902 and the selection transistor 905 are transistors including a silicon semiconductor.

The fourth condition is a VGA image sensor having the pixel circuit of Fig. 29 and driving the global shutter system. The structure of the circuit is the same as the third condition, and only the shutter system is different.

Each transistor including the silicon semiconductor in the pixel circuits of Figs. 28 and 29 has a channel length L of 3 mu m, a channel width W of 5 mu m, and a thickness d of the gate insulating film of 20 nm It should be noted that. Each transistor including an oxide semiconductor has a channel length ( L ) of 3 mu m, a channel width ( W ) of 5 mu m, and a thickness ( d ) of a gate insulating film of 200 nm.

Further, the imaging frequency was set to 60 Hz, the electrical characteristics of the transistor including the silicon semiconductor satisfied Icut = 10 kV, and the electrical characteristics of the transistor including the oxide semiconductor satisfied Icut = 0.1 aA. In this embodiment, the term Icut refers to the amount of current flowing between the source and the drain when the gate voltage is set to 0 V and the drain voltage is set to 5 V. [

The condition of the rotational motion of the three blades shown in Fig. 8A was set to 640 rpm in the clockwise direction. It should be noted that when the number of revolutions is 640 rpm, the three blades rotate about 60 degrees during one frame (1 / 60s) during the accumulation operation of the rolling shutter.

In the case of the first condition (in which the transistors are only silicon semiconductor transistors and the rolling shutter system is driven), the timing for accumulating charges in the signal charge storage portion of the pixel is different for each row; Therefore, distortion occurs in the image as shown in Fig. 8B.

In the second condition (in which the transistors are only silicon semiconductor transistors and the global shutter system is driven), the change in grayscale appears as shown in Fig. 8C, which results in the charge accumulation control transistor 803 and the reset transistor RTI ID = 0.0 > 804 < / RTI > The charge retention time becomes longer toward the lower last row; Thus, the change becomes noticeable.

In the case of the third condition (in which the charge accumulation control transistor and the reset transistor are oxide semiconductor transistors and the rolling shutter system is driven), the image is distorted as shown in Fig. 8D, which is similar to the case of the first condition .

In the case of the fourth condition (in which the charge accumulation control transistor and the reset transistor are oxide semiconductor transistors and the global shutter system is driven), as shown in Fig. 8A, the charge due to the off- Leakage is low and grayscale is properly displayed.

From the results shown in Figs. 8B to 8E, it can be seen that the rolling shutter system causes image distortion in the pixel circuit of either Fig. 9 or Fig. 10, and there is no strong correlation between image distortion and off- . In other words, in order to reduce the distortion of the image, it is effective that the timing for accumulating charge in the signal charge storage portion of the pixel drives the same global shutter system in all the pixels.

However, when the circuit is formed using a conventional transistor including a silicon semiconductor, the global shutter system has a problem that the gray scale changes due to charge leakage due to the off-state current of the charge accumulation control transistor and the reset transistor I found out.

On the other hand, it has been found that when a transistor including an oxide semiconductor is used for the charge storage control transistor and the reset transistor, the charge is prevented from flowing due to an extremely low off-state current and the gray scale is accurately displayed. Therefore, an imaging device having a pixel circuit including a transistor including an oxide semiconductor can easily drive the global shutter system.

This embodiment may be suitably implemented in combination with any other embodiments or examples.

(Embodiment 3)

In this embodiment, the circuit structure of the photosensor portion of the display device according to one embodiment of the present invention is described.

In the display device of the embodiment of the present invention, various circuits can be used in the photosensor portion. In this embodiment, a circuit structure other than the circuit structure of the photosensor section 106 shown in Fig. 2 of the first embodiment is described.

The names of the transistors and wirings described in this embodiment have been named for convenience; Thus, it should be noted that any of the nomenclature is acceptable provided that the functions of the transistors and wirings are described.

9 is a pixel circuit structure of four transistors similar to the photosensor section 106 of Fig. The pixel circuit is formed of a photodiode 1601, an amplification transistor 1602, a charge accumulation control transistor 1603, a reset transistor 1604, and a selection transistor 1605. The circuit structure of FIG. 9 differs from FIG. 1 in the location of the selection transistor 1605.

The gate of the charge accumulation control transistor 1603 is connected to the charge accumulation control signal line 1613. One of the source and the drain of the charge accumulation control transistor 1603 is connected to the cathode of the photodiode 1601, And the other of the source and the drain of the signal charge storage portion 1603 is connected to the signal charge storage portion 1612. [ The anode of the photodiode 1601 is connected to the reference signal line 1631.

One of the source and the drain of the amplification transistor 1602 is connected to one of the source and the drain of the selection transistor 1605 and the amplification transistor 1602 is connected to the signal charge storage portion 1612. The gate of the amplification transistor 1602 is connected to the signal charge storage portion 1612, Is connected to the output signal line 1620. The other one of the source and the drain of the transistor Q1 is connected to the output signal line 1620. [

One of the source and the drain of the reset transistor 1604 is connected to the power supply line 1630 and the other of the source and the drain of the reset transistor 1604 is connected to the reset signal line 1614, Is connected to the signal charge storage portion 1612.

The gate of the selection transistor 1605 is connected to the selection signal line 1615 and the other of the source and the drain of the selection transistor 1605 is connected to the power supply line 1630. Here, the charge holding capacitor may be connected between the signal charge storage portion 1612 and the reference signal line 1631.

Next, the functions of the elements forming the pixel circuit of Fig. 9 are described. The photodiode 1601 generates a current according to the amount of light incident on the pixel. The amplifying transistor 1602 outputs a signal corresponding to the potential of the signal charge storage portion 1612. The charge accumulation control transistor 1603 controls the charge accumulation in the signal charge accumulation portion 1612 performed by the photodiode 1601. [ The reset transistor 1604 controls the initialization of the potential of the signal charge storage portion 1612. The selection transistor 1605 controls the selection of pixels upon reading. The signal charge storage portion 1612 is a charge holding node and holds charges that vary depending on the amount of light received by the photodiode 1601. [

The charge accumulation control signal line 1613 is a signal line for controlling the charge accumulation control transistor 1603. The reset signal line 1614 is a signal line for controlling the reset transistor 1604. The selection signal line 1615 is a signal line for controlling the selection transistor 1605. The output signal line 1620 is a signal line serving as an output destination of a signal generated by the amplification transistor 1602. [ The power supply line 1630 is a signal line for supplying a power supply voltage. The reference signal line 1631 is a signal line for setting the reference potential.

The operation of the pixel circuit shown in Fig. 9 is similar to that of the pixel circuit of the photosensor section 106 of Fig. 2 described in the first embodiment.

Next, the pixel circuit structure of the three transistors shown in Fig. 10 is described. The pixel circuit is formed of a photodiode 1701, an amplification transistor 1702, a charge accumulation control transistor 1703, and a reset transistor 1704.

The gate of the charge accumulation control transistor 1703 is connected to the charge accumulation control signal line 1713. One of the source and the drain of the charge accumulation control transistor 1703 is connected to the cathode of the photodiode 1701, And the other of the source and the drain of the signal charge storage portion 1703 is connected to the signal charge storage portion 1712. [ The anode of the photodiode 1701 is connected to the reference signal line 1731.

One of the source and the drain of the amplifying transistor 1702 is connected to the power source supply line 1730 and the source and the drain of the amplifying transistor 1702 are connected to the signal charge storage section 1712, And the other is connected to the output signal line 1720.

One of the source and the drain of the reset transistor 1704 is connected to the power supply line 1730 and the other of the source and the drain of the reset transistor 1704 is connected to the reset signal line 1714, Is connected to the signal charge storage portion 1712. Here, the charge holding capacitor may be connected between the signal charge storage portion 1712 and the reference signal line 1731.

Next, the functions of the elements forming the pixel circuit of Fig. 10 are described. The photodiode 1701 generates a current according to the amount of light incident on the pixel. The amplifying transistor 1702 outputs a signal corresponding to the potential of the signal charge storage portion 1712. The charge accumulation control transistor 1703 controls the charge accumulation in the signal charge accumulation portion 1712 performed by the photodiode 1701. [ The reset transistor 1704 controls the initialization of the potential of the signal charge storage portion 1712. The signal charge storage portion 1712 is a charge holding node and holds charge that varies depending on the amount of light received by the photodiode 1701. [

The charge storage control signal line 1713 is a signal line for controlling the charge storage control transistor 1703. The reset signal line 1714 is a signal line for controlling the reset transistor 1704. The output signal line 1720 is a signal line serving as an output destination of a signal generated by the amplifying transistor 1702. The power supply line 1730 is a signal line for supplying a power supply voltage. The reference signal line 1731 is a signal line for setting the reference potential.

The pixel circuit structure of the three transistors, which is different from that of Fig. 10, is shown in Fig. The pixel circuit includes a photodiode 3801, an amplifying transistor 3802, a charge accumulation control transistor 3803, and a reset transistor 3804.

The gate of the charge accumulation control transistor 3803 is connected to the charge accumulation control signal line 3813. One of the source and the drain of the charge accumulation control transistor 3803 is connected to the cathode of the photodiode 3801, And the other of the source and the drain of the signal charge storage portion 3803 is connected to the signal charge storage portion 3812. [ The anode of the photodiode 3801 is connected to the reference signal line 3831.

One of the source and the drain of the amplifying transistor 3802 is connected to the power supply line 3830 and the source and the drain of the amplifying transistor 3802 are connected to the signal charge storage section 3812, And the other is connected to the output signal line 3820.

One of the source and the drain of the reset transistor 3804 is connected to the reset power supply line 3832 and the other of the source and the drain of the reset transistor 3804 is connected to the reset signal line 3814, And one is connected to the signal charge storage portion 3812. Here, the charge holding capacitor may be connected between the signal charge storage portion 3812 and the reference signal line 3831.

Next, the functions of the elements forming the pixel circuit of Fig. 11 are described. The photodiode 3801 generates a current in accordance with the amount of light incident on the pixel. The amplifying transistor 3802 outputs a signal corresponding to the potential of the signal charge storage portion 3812. The charge accumulation control transistor 3803 controls the charge accumulation in the signal charge accumulation portion 3812 performed by the photodiode 3801. [ The reset transistor 3804 controls the initialization of the potential of the signal charge storage portion 3812. The signal charge storage portion 3812 is a charge holding node, and holds charge that varies depending on the amount of light received by the photodiode 3801. [

The charge accumulation control signal line 3813 is a signal line for controlling the charge accumulation control transistor 3803. The reset signal line 3814 is a signal line for controlling the reset transistor 3804. The output signal line 3820 is a signal line serving as an output destination of a signal generated by the amplifying transistor 3802. [ The reset power supply line 3832 is a power supply line different from the power supply line 3830 and the reset power supply line 3832 can initialize the potential of the signal charge storage portion 3812 different from the potential of the power supply line 3830 . The power supply line 3830 is a signal line for supplying a power supply voltage. The reference signal line 3831 is a signal line for setting the reference potential.

Next, the operations of the pixel circuits of Figs. 10 and 11 are described using the timing diagrams shown in Figs. 12A and 12B. The operation of the circuit shown in Fig. 10 is basically the same as that shown in Fig. 11; Therefore, it should be noted that the structure of Fig. 10 is described here.

12A and 12B, the potential 3913 of the charge accumulation control signal line 1713 and the potential 3914 of the reset signal line 1714 are signals which change between two levels. It should be noted that since each potential is an analog signal, the potential is not actually limited to two levels and may have various levels depending on the circumstances.

First, an operation mode according to Fig. 12A is described.

The potential 3913 of the charge storage control signal line 1713 is set to the high level at the time 3930. [ Next, when the potential 3914 of the charge accumulation control signal line 1714 is again set to the high level in the time 3931, the potential of the power supply line 1730 connected to one of the source and the drain of the reset transistor 1704 Is supplied as the potential 3912 of the signal charge storage portion 1712. These steps are called reset operations.

When the potential 3914 of the reset signal line 1714 is set to the low level at the time 3932, the potential 3912 of the signal charge storage portion holds the potential equal to the potential of the power supply line 1730, A bias is applied to the photodiode 1701. [ At this stage, the accumulation operation is started.

Then, since the reverse current corresponding to the amount of light flows in the photodiode 1701, the amount of charge accumulated in the signal charge storage portion 1712 varies depending on the amount of light. At the same time, electric charges are supplied from the power supply line 1730 to the output signal line 1720 in accordance with the potential 3912 of the signal charge storage portion 1712. At this stage, the read operation is started.

When the potential 3913 of the charge storage control signal line 1713 is set to the low level in the time 3933, the movement of the charge from the signal charge storage portion 1712 to the photodiode 1701 is stopped, The amount of charge accumulated in the charge accumulating portion 1712 is determined. Here, the accumulation operation ends.

Subsequently, the supply of electric charge from the power supply line 1730 to the output signal line 1720 is stopped, and the potential 3920 of the output signal line is determined. Here, the read operation is ended.

Next, the operation mode according to Fig. 12B is described.

The potential 3913 of the charge storage control signal line 1713 is set to the high level at the time 3930. [ Next, when the potential 3914 of the reset signal line 1714 is set to a high level at time 3931, the potential 3912 of the signal charge storage portion 1712 and the potential of the cathode of the photodiode 1701 are reset And is initialized to the potential of the power supply line 1730 connected to one of the source and the drain of the transistor 1704. These steps are called reset operations.

When the potential 3913 of the charge storage control signal line 1713 is set to the low level in the time 3934 and the potential 3914 of the reset signal line 1714 is set to the low level in the time 3935, End; Therefore, a reverse current corresponding to the amount of light flows to the photodiode to which the reverse bias is applied, thereby changing the potential of the cathode of the photodiode 1701. [

The potential 3912 of the signal charge storage portion 1712 and the potential of the cathode of the photodiode 1701 when the potential 3913 of the charge storage control signal line 1713 is again set to the high level at the time 3932 And the potential 3912 of the signal charge storage portion 1712 changes.

The subsequent steps are the same as the operation mode according to FIG.

Next, the pixel circuit structure of the three transistors, which is different from that described above, is described in Fig. The pixel circuit is formed of a photodiode 2001, an amplifying transistor 2002, a charge accumulation control transistor 2003, and a reset transistor 2004. The anode of the photodiode 2001 is connected to the reference signal line 2031. [

The gate of the charge accumulation control transistor 2003 is connected to the charge accumulation control signal line 2013. One of the source and the drain of the charge accumulation control transistor 2003 is connected to the cathode of the photodiode 2001, And the other of the source and the drain of the signal charge storage part 2003 is connected to the signal charge storage part 2012. [

One of the source and the drain of the amplification transistor 2002 is connected to the power supply line 2030 and the source and the drain of the amplification transistor 2002 are connected to the signal charge storage section 2012, And the other is connected to the output signal line 2020.

The gate of the reset transistor 2004 is connected to the reset signal line 2014 and one of the source and the drain of the reset transistor 2004 is connected to the signal charge storage part 2012 and the source and the drain of the reset transistor 2004 And the other is connected to the output signal line 2020. Here, the charge holding capacitor may be connected between the signal charge storage portion 2012 and the reference signal line 2031. [

Next, the functions of the elements forming the pixel circuit of Fig. 13 are described. The photodiode 2001 generates a current according to the amount of light incident on the pixel. The amplifying transistor 2002 outputs a signal corresponding to the potential of the signal charge storage part 2012. [ The charge storage control transistor 2003 controls the charge accumulation in the signal charge storage part 2012 performed by the photodiode 2001. [ The reset transistor 2004 controls the initialization of the potential of the signal charge storage part 2012. [ The signal charge storage portion 2012 is a charge holding node and holds charge that varies depending on the amount of light received by the photodiode 2001. [

The charge accumulation control signal line 2013 is a signal line for controlling the charge accumulation control transistor 2003. The reset signal line 2014 is a signal line for controlling the reset transistor 2004. The output signal line 2020 is a signal line serving as an output destination of a signal generated by the amplifying transistor 2002. The power supply line 2030 is a signal line for supplying a power supply voltage. The reference signal line 2031 is a signal line for setting the reference potential.

Next, the operations of the pixel circuits of Fig. 13 are described using the timing diagrams shown in Figs. 14A and 14B.

14A and 14B, the potential 2113 of the charge accumulation control signal line 2013 and the potential 2114 of the reset signal line 2014 are signals which change between two levels. It should be noted that since each potential is an analog signal, the potential can have various levels depending on the situation without actually being limited to the two levels.

First, an operation mode according to Fig. 14A is described.

The potential 2113 of the charge storage control signal line 2013 is set to the high level in the time 2130. [ Next, when the potential 2114 of the reset signal line 2014 is set to the high level in the time 2131, the potential 2120 of the output signal line 2020 connected to the other of the source and the drain of the reset transistor 2004 To the signal charge storage part 2012 is supplied as the potential 2112 of the signal charge storage part 2012. [ These steps are called reset operations.

When the potential 2114 of the reset signal line 2014 is set to the low level in the time 2132, the potential 2112 of the signal charge storage portion 2012 holds the reset potential, whereby the reverse bias is applied to the photodiode (2001). At this stage, the accumulation operation is started.

Then, since a reverse current corresponding to the amount of light flows in the photodiode 2001, the amount of charge accumulated in the signal charge storage part 2012 changes depending on the amount of light. At the same time, charge is supplied from the power supply line 2030 to the output signal line 2020 along the potential 2112 of the signal charge storage part 2012. [ At this stage, the read operation is started.

When the potential 2113 of the charge accumulation control signal line 2013 is set to the low level in the time 2133, the movement of the charge from the signal charge accumulator 2012 to the photodiode 2001 is stopped, The amount of charge accumulated in the charge accumulation portion 2012 is determined. Here, the accumulation operation ends.

Subsequently, the supply of electric charge from the power supply line 2030 to the output signal line 2020 is stopped, and the potential 2120 of the output signal line is determined. Here, the read operation is ended.

Next, an operation mode according to Fig. 14B is described.

The potential 2113 of the charge storage control signal line 2013 is set to the high level in the time 2130. [ Next, when the potential 2114 of the reset signal line 2014 is set to the high level at the time 2131, the potential 2112 of the signal charge storage portion 2012 and the potential of the cathode of the photodiode 2001 are reset Is initialized to the potential 2120 of the output signal line 2020 connected to the other of the source and the drain of the transistor 2004. [ These steps are called reset operations.

When the potential 2113 of the charge storage control signal line 2013 is set to the low level in the time 2134 and the potential 2114 of the reset signal line 2014 is set to the low level in the time 2135, End; Therefore, a reverse current corresponding to the amount of light flows to the photodiode to which the reverse bias is applied, thereby changing the potential of the cathode of the photodiode 2001. [

The potential 2112 of the signal charge storage portion 2012 and the potential difference of the potential of the cathode of the photodiode 2001 when the potential 2113 of the charge accumulation control signal line 2013 is again set to the high level at the time 2132 And the potential 2112 of the signal charge storage portion 2012 is changed.

The subsequent steps are the same as the operation mode according to FIG.

Next, a pixel circuit structure of three transistors, which is different from that described above, is shown in Fig. The pixel circuit includes a photodiode 2201, an amplification transistor 2202, a charge accumulation control transistor 2203, and a selection transistor 2205. The anode of the photodiode 2201 is connected to the reset signal line 2216.

The gate of the charge accumulation control transistor 2203 is connected to the charge accumulation control signal line 2213. One of the source and the drain of the charge accumulation control transistor 2203 is connected to the cathode of the photodiode 2201, And the other of the source and the drain of the signal charge storage portion 2203 is connected to the signal charge storage portion 2212.

One of the source and the drain of the amplifying transistor 2202 is connected to the power source supply line 2230 and the source and the drain of the amplifying transistor 2202 are connected to the signal charge storage portion 2212, And the other is connected to one of the source and the drain of the selection transistor 2205.

The gate of the selection transistor 2205 is connected to the selection signal line 2215 and the other of the source and the drain of the selection transistor 2205 is connected to the output signal line 2220. Here, the charge holding capacitor may be connected between the signal charge storage portion 2212 and the reference signal line.

Next, the functions of the elements forming the pixel circuit of Fig. 15 are described. The photodiode 2201 generates a current in accordance with the amount of light incident on the pixel. The amplifying transistor 2202 outputs a signal corresponding to the potential of the signal charge storage portion 2212. The charge accumulation control transistor 2203 controls the charge accumulation in the signal charge accumulation portion 2212 performed by the photodiode 2201. The selection transistor 2205 controls the selection of pixels upon reading. The signal charge storage portion 2212 is a charge holding node and holds charge that varies depending on the amount of light received by the photodiode 2201. [

The charge storage control signal line 2213 is a signal line for controlling the charge storage control transistor 2203. The reset signal line 2216 is a signal line for supplying a reset potential to the signal charge storage portion 2212. The output signal line 2220 is a signal line serving as an output destination of a signal generated by the amplifying transistor 2202. The selection signal line 2215 is a signal line for controlling the selection transistor 2205. The power supply line 2230 is a signal line for supplying a power supply voltage.

Next, the operations of the pixel circuits of Fig. 15 are described using the timing diagrams shown in Figs. 16A and 16B.

The potential 2313 of the charge accumulation control signal line 2213, the potential 2316 of the reset signal line 2216 and the potential 2315 of the selection signal line 2215 are set to two levels Lt; / RTI > It should be noted that since each potential is an analog signal, the potential can have various levels depending on the situation without actually being limited to the two levels.

First, an operation mode according to Fig. 16A is described.

The potential 2313 of the charge accumulation control signal line 2213 is set to the high level at the time 2330. Next, when the potential 2316 of the reset signal line 2216 is set to a high level at the time 2331, the potential 2312 of the signal charge storage portion 2212 and the potential of the cathode of the photodiode 2201 become Is initialized to a potential lower than the potential 2316 of the reset signal line 2216 by the forward voltage of the diode 2201. [ These steps are called reset operations.

The potential 2312 of the signal charge storage portion 2212 is held at the high level when the potential 2316 of the reset signal line 2216 is set to the low level at the time 2332, (2201). At this stage, the accumulation operation is started.

Then, since a reverse current corresponding to the amount of light flows in the photodiode 2201, the amount of charge accumulated in the signal charge storage portion 2212 varies depending on the amount of light.

The movement of the charge from the signal charge storage portion 2212 to the photodiode 2201 is stopped when the potential 2313 of the charge storage control signal line 2213 is set to the low level in the time 2333, The amount of charge accumulated in the charge accumulating portion 2212 is determined. Here, the accumulation operation ends.

When the potential 2315 of the selection signal line 2215 is set to the high level in the time 2334, charges are transferred from the power supply line 2230 to the output signal line 2220 in accordance with the potential 2312 of the signal charge storage portion 2212 . At this stage, the read operation is started.

When the potential 2315 of the selection signal line 2215 is set to the low level in the time 2335, the supply of the electric charge from the power supply line 2230 to the output signal line 2220 is stopped and the potential of the output signal line 2220 2320) is determined. Here, the read operation is ended.

Next, the operation mode according to Fig. 16B is described.

The potential 2313 of the charge accumulation control signal line 2213 is set to the high level at the time 2330. Subsequently, when the potential 2316 of the reset signal line 2216 is set to a high level at the time 2331, the potential 2312 of the signal charge storage portion 2212 and the potential of the cathode of the photodiode 2201 are set to the potential of the photodiode Is reset to the reset potential lower than the potential 2316 of the reset signal line by the forward voltage of the reset signal line 2201. These steps are called reset operations.

When the potential 2313 of the charge storage control signal line 2213 is set to the low level in the time 2336 and the potential 2316 of the reset signal line 2216 is set to the low level in the time 2337, End; Therefore, a reverse current corresponding to the amount of light flows in the photodiode to which the reverse bias is applied, whereby the potential of the cathode of the photodiode 2201 changes.

When the potential 2313 of the charge accumulation control signal line 2213 is set to the high level in the time 2332, the potential difference between the potential 2312 of the signal charge storage portion 2212 and the potential of the cathode of the photodiode 2201 Whereby the potential 2312 of the signal charge storage portion 2212 is changed.

The subsequent steps are the same as the operation mode according to FIG.

Next, a two-transistor type pixel circuit structure shown in Fig. 17 is described.

The pixel circuit includes a photodiode 4401, an amplification transistor 4402, and a selection transistor 4405.

One of the source and the drain of the amplifying transistor 4402 is connected to the power source supply line 4430 and the source and the drain of the amplifying transistor 4402 are connected to the signal charge storage section 4412, And the other is connected to one of the source and the drain of the selection transistor 4405. [

The gate of the selection transistor 4405 is connected to the selection signal line 4415 and the other of the source and the drain of the selection transistor 4405 is connected to the output signal line 4420.

The cathode of the photodiode 4401 is connected to the signal charge storage portion 4412 and the anode of the photodiode 4401 is connected to the reset signal line 4416. Here, the charge holding capacitor is connected between the signal charge storage portion 4412 and the reference signal line.

Next, the function of the element included in the pixel circuit of Fig. 17 is described. The photodiode 4401 generates a current according to the amount of light incident on the pixel. The amplifying transistor 4402 outputs a signal corresponding to the potential of the signal charge storage portion 4412. The selection transistor 4405 controls the selection of the pixel upon reading. The signal charge storage portion 4412 is a charge holding node, and holds charges that vary depending on the amount of light received by the photodiode 4401. [

The reset signal line 4416 is a signal line for supplying a reset potential to the signal charge storage portion 4412. The output signal line 4420 is a signal line serving as an output destination of the signal generated by the amplifying transistor 4402. [ The selection signal line 4415 is a signal line for controlling the selection transistor 4405. The power supply line 4430 is a signal line for supplying a power supply voltage.

Next, the operations of the pixel circuits of Fig. 17 are described using the timing diagrams shown in Fig.

18, the potential 3716 of the reset signal line 4416 and the potential 3715 of the selection signal line 4415 are signals that change between two levels. Since each potential is an analog signal, the potential can have various levels depending on the situation, without actually being limited to two levels.

The potential 3712 of the signal charge storage portion 4412 is reset by the forward voltage of the photodiode 4401 when the potential 3716 of the reset signal line 4416 is set to the high level at the time 3730, The reset potential is lower than the potential 3716 thereof. These steps are called reset operations.

The potential 3712 of the signal charge storage portion 4412 holds the reset potential when the potential 3716 of the reset signal line 4416 is set to the low level at the time 3731, (2001). At this stage, the accumulation operation is started.

Then, since the reverse current corresponding to the amount of light flows in the photodiode 4401, the amount of charges accumulated in the signal charge storage portion 4412 varies depending on the amount of light.

When the potential 3715 of the selection signal line 4415 is set to the high level in the time 3732, the charge 3712 is transferred from the power supply line 4430 to the output signal line 4420 in accordance with the potential 3712 of the signal charge storage portion 4412 . At this stage, the read operation is started.

The charge transfer from the signal charge storage portion 4412 to the photodiode 4401 is stopped when the potential 3715 of the selection signal line 4415 is set to the low level in the time 3733, The amount of charge accumulated in the capacitor 4412 is determined. Here, the accumulation operation ends.

Subsequently, the supply of electric charge from the power supply line 4430 to the output signal line 4420 is stopped, and the potential 3720 of the output signal line is determined. Here, the read operation is ended.

Next, the pixel circuit structure of the transistor is shown in Fig. The pixel circuit includes a photodiode 2601, an amplification transistor 2602, and a capacitor 2606.

One of the source and the drain of the amplifying transistor 2602 is connected to the power source supply line 2630 and the source and the drain of the amplifying transistor 2602 are connected to the signal charge storage portion 2612, And the other is connected to the output signal line 2620.

The cathode of the photodiode 2601 is connected to the signal charge storage portion 2612 and the anode of the photodiode 2601 is connected to the reset signal line 2616. One of the terminals of the capacitor 2606 is connected to the signal charge storage portion 2612, and the other is connected to the selection signal line 2615. Here, a charge holding capacitor is connected between the signal charge storage portion 2612 and the reference signal line.

Next, the functions of the elements forming the pixel circuit of Fig. 19 are described. The photodiode 2601 generates a current according to the amount of light incident on the pixel. The amplification transistor 2602 outputs a signal corresponding to the potential of the signal charge storage portion 2612. The signal charge storage portion 2612 is a charge holding node, and holds charges that vary depending on the amount of light received by the photodiode 2601. [ It should be noted that the selection signal line 2615 controls the potential of the signal charge storage portion 2612 using capacitive coupling.

The reset signal line 2616 is a signal line for supplying a reset potential to the signal charge storage portion 2612. The output signal line 2620 is a signal line serving as an output destination of the signal generated by the amplifying transistor 2602. [ The selection signal line 2615 is a signal line for controlling the capacitor 2606. The power supply line 2630 is a signal line for supplying a power supply voltage.

Next, the operations of the pixel circuits of Fig. 19 are described using the timing diagrams shown in Fig.

20, the potential 2716 of the reset signal line 2616 and the potential 2715 of the select signal line 2615 are signals that change between two levels. Since each potential is an analog signal, the potential can have various levels depending on the situation, without actually being limited to the two levels.

The potential 2712 of the signal charge storage portion 2612 is reset by the forward voltage of the photodiode 2601 when the potential 2716 of the reset signal line 2616 is set to the high level at the time 2730, The reset potential is lower than the potential 2716 thereof. These steps are called reset operations.

Next, when the potential 2716 of the reset signal line 2616 is set to the low level in the time 2731, the potential 2712 of the signal charge accumulation portion 2612 holds the reset potential, Is applied to the photodiode 2601. At this stage, the accumulation operation is started.

Then, since a reverse current corresponding to the amount of light flows in the photodiode 2601, the amount of charges accumulated in the signal charge storage portion 2612 varies depending on the amount of light.

The potential 2715 of the selection signal line 2615 is set to the high level at the time 2732 so that the potential 2712 of the signal charge storage portion 2612 becomes high due to capacitive coupling; Thereby, the amplifying transistor 2602 is turned on. Charge is also supplied from the power supply line 2630 to the output signal line 2620 in accordance with the potential 2712 of the signal charge storage portion 2612. At this stage, the read operation is started.

The potential 2712 of the signal charge storage portion 2612 is reduced by the capacitive coupling and the signal charge stored in the signal charge storage portion 2612 is supplied from the signal charge storage portion 2612 when the potential 2715 of the selection signal line 2615 is set to the low level at the time 2733 The charge transfer to the photodiode 2601 is stopped, whereby the amount of charge accumulated in the signal charge storage portion 2612 is determined. Here, the accumulation operation ends.

Subsequently, the supply of electric charge from the power supply line 2630 to the output signal line 2620 is stopped, and the potential 2720 of the output signal line 2620 is determined. Here, the read operation is ended.

It is to be noted that the pixel circuit structures of Figs. 17 and 19 preferably have a structure for shielding incident light to the photodiode because the charge of the signal charge storage portion flows through the photodiode having the structures.

This embodiment can be suitably implemented in combination with any other embodiment or example.

(Fourth Embodiment)

In this embodiment, a liquid crystal display, which is an example of the display device disclosed in the present application, is described.

21 shows an example of a cross-sectional view of a liquid crystal display device. In the liquid crystal display device of this embodiment, the photodiode 1002, the transistor 1003a, the transistor 1003b, the transistor 1003c, the transistor 1003d, the holding capacitor 1004, and the liquid crystal element 1005 are insulated Is provided on the substrate 1001 having a surface. The optical sensors and display elements are partially shown on the left and right sides, respectively, of the dotted line across the liquid crystal display of Fig. 21, and these structures correspond to the structure of the photosensor portion 106 of Fig. 2 described in Embodiment 1 It should be noted that it is the same. It should be noted that the transistor corresponding to the reset transistor is not shown.

Although a top-gate structure is shown as a typical example of the structure of each of the transistor 1003a, the transistor 1003b, the transistor 1003c, and the transistor 1003d, it is not limited thereto, Another structure such as a structure may be applied.

The transistor 1003a provided in the optical sensor corresponds to the charge accumulation control transistor. The wiring 1030 is connected to one of the source electrode and the drain electrode of the transistor 1003a and is electrically connected to the cathode of the photodiode 1002. [ The other of the source electrode and the drain electrode of the transistor 1003a is connected to the wiring 1036 and the gate electrode of the transistor 1003b. It is to be noted that the wiring 1030 and the wiring 1036 may be formed on the insulating film 1033 instead of the protective insulating film 1031. [

The transistor 1003b corresponds to an amplification transistor. One of the source electrode and the drain electrode of the transistor 1003b is connected to a power supply line not shown. The other of the source electrode and the drain electrode of the transistor 1003b is connected to one of the source electrode and the drain electrode of the transistor 1003c.

The transistor 1003c corresponds to the selection transistor. The other of the source electrode and the drain electrode of the transistor 1003c is connected to an output signal line not shown.

Here, one of the source electrode and the drain electrode of the transistor corresponding to the reset transistor (not shown) is connected to the wiring 1036, and the other of the source electrode and the drain electrode of the transistor is connected to a power supply line not shown.

The photodiode 1002 includes a p-type semiconductor layer 1041 containing an impurity imparting p-type conductivity, an i-type semiconductor layer 1042 having intrinsic semiconductor characteristics, And a n-type semiconductor layer 1043 containing an impurity.

As a typical example, a photodiode in which amorphous silicon is used for the i-type semiconductor layer 1042 may be provided. In this case, although amorphous silicon can be used for the p-type semiconductor layer 1041 and the n-type semiconductor layer 1043, it is preferable to use microcrystalline silicon having high electrical conductivity. A photodiode in which amorphous silicon is used for the i-type semiconductor layer 1042 has photosensitivity in a visible light region and can prevent malfunction due to infrared rays.

Here, the p-type semiconductor layer 1041, which is the anode of the photodiode 1002, is electrically connected to the signal wiring 1035, and the n-type semiconductor layer 1043 which is the cathode of the photodiode 1002, And is electrically connected to one of the source electrode and the drain electrode of the transistor 1003a. It should be noted that the signal line 1035 corresponds to the reference signal line.

It should be noted that although not shown, a light-transmitting conductive layer may be provided on the light-incident surface of the p-type semiconductor layer 1041. Further, the conductive layer may be provided on the interface side of the n-type semiconductor layer 1043 with the insulating film 1033. For example, the wiring 1030 may be extended to cover the n-type semiconductor layer 1043. By providing such a conductive layer, the loss of electric charge due to the resistance of the p-type semiconductor layer 1041 or the n-type semiconductor layer 1043 can be reduced.

Note that although the photodiode 1002 is a PIN diode in this embodiment, it is to be noted that the photodiode 1002 may be a PN diode. In this case, high-quality crystalline silicon is preferably used for the p-type semiconductor layer and the n-type semiconductor layer.

The photodiode may have a horizontal junction structure as shown in Fig. In the PIN horizontal junction photodiode, the p-type semiconductor layer 1041, the i-type semiconductor layer 1042, and the n-type semiconductor layer 1043 may be provided as follows: An impurity imparting p-type conductivity and an impurity imparting n-type conductivity are added to a part of the i-type semiconductor layer.

The transistor 1003d is provided in the display element for driving the liquid crystal element. One of the source electrode and the drain electrode of the transistor 1003d is electrically connected to the pixel electrode 1007 and the other of the source electrode and the drain electrode of the transistor 1003d is electrically connected to the signal line .

The holding capacitor 1004 may be formed in the step of forming the transistor 1003a, the transistor 1003b, the transistor 1003c, and the transistor 1003d. The capacitor wiring and the capacitor electrode are formed in the respective steps of forming the gate electrode of the transistor and forming the source or drain electrode of the transistor and the insulating film which is the capacity of the holding capacitor 1004 is formed in the step of forming the gate insulating film of the transistor do. The holding capacitor 1004 is electrically connected to one of the source electrode and the drain electrode of the transistor 1003d in parallel with the liquid crystal element 1005. [

The liquid crystal element 1005 includes a pixel electrode 1007, liquid crystals 1008, and a counter electrode 1009. The pixel electrode 1007 is formed on the planarization insulating film 1032 and is electrically connected to one of the source electrode and the drain electrode of the transistor 1003d and the holding capacitor 1004. Further, the counter electrode 1009 is provided on the counter substrate 1013, and the liquid crystals 1008 are provided between the pixel electrode 1007 and the counter electrode 1009.

The cell gap between the pixel electrode 1007 and the counter electrode 1009 can be controlled using the spacer 1016. [ The cell gap is controlled using a spacer 1016 selectively formed by photolithography and has a columnar shape in FIGS. 21 and 22, but the cell gap is alternately arranged between the pixel electrode 1007 and the counter electrode 1009 And can be controlled by spherical spacers that are diffused. The position of the spacer 1016 in Figs. 21 and 22 is exemplary, and the position of the spacer can be suitably determined by the practitioner.

Further, between the substrate 1001 and the counter substrate 1013, the liquid crystals 1008 are surrounded by the sealing material. The liquid crystals 1008 may be injected by a dispenser method (droplet method) or a dipping method (pumping method).

The pixel electrode 1007 is formed of indium tin oxide (ITO), indium tin oxide containing silicon oxide, indium zinc oxide (IZO) containing organic indium, organotin, zinc oxide, zinc oxide, zinc oxide containing gallium, A transparent conductive material such as tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide or the like can be used.

Furthermore, since the transmissive liquid crystal element 1005 is provided as an example in this embodiment, the counter electrode 1009 can also be formed using the transmissive conductive material as in the case of the pixel electrode 1007. [

An alignment film 1011 is provided between the pixel electrode 1007 and the liquid crystals 1008 and an alignment film 1012 is provided between the counter electrode 1009 and the liquid crystals 1008. The alignment film 1011 and the alignment film 1012 may be formed using an organic resin such as polyimide or polyvinyl alcohol. In order to align the liquid crystal molecules in a specific direction, an orientation treatment such as rubbing is performed on the surfaces. The rubbing can be performed so that the surface of the alignment film is rubbed in a specific direction by rolling rollers covered with a cloth such as nylon while applying pressure to the alignment film. By using an inorganic material such as silicon oxide, the alignment film 1011 and the alignment film 1012 having alignment properties can be formed directly by the deposition method without performing the alignment treatment.

A color filter 1014 capable of transmitting light having a specific wavelength is provided on the counter substrate 1013 so as to overlap with the liquid crystal element 1005. [ The color filter 1014 can be selectively formed as follows: an organic resin such as an acrylic resin to which a pigment is diffused is applied to an opposing substrate 1013 and photolithography is performed. Alternatively, the color filter 1014 can be selectively formed as follows: A polyimide-based resin into which a pigment is diffused is applied to an opposing substrate 1013 to perform etching. Alternatively, the color filter 1014 may be selectively formed by a droplet discharge method such as an ink-jet method. It should be noted that a structure in which the color filter 1014 is not provided is also possible.

A shielding film 1015 capable of shielding light is provided on the counter substrate 1013 so as to overlap with the photodiode 1002. [ The shielding film 1015 can prevent direct irradiation of the photodiode 1002 with the light of the backlight passing through the counter substrate 1013. [ Further, the shielding film 1015 can prevent the observation of disclination due to the disarrangement of the orientation of the liquid crystals 1008 between the pixels. The shielding film 1015 may be formed using an organic resin containing a black pigment such as carbon black or low-order titanium oxide. Alternatively, the shielding film 1015 may be formed using a chromium film.

A polarizing plate 1017 is provided on the side of the substrate 1001 opposite to the side where the pixel electrode 1007 is provided and a polarizing plate 1017 is provided on the side of the opposite substrate 1013 opposite to the side on which the counter electrode 1009 is provided. Is provided.

The liquid crystal device may be a twisted nematic (TN) type, a VA (vertical alignment) type, an OCB (optically compensated birefringence) type, an IPS (in-plane switching) type or the like. In this embodiment, a liquid crystal element 1005 in which liquid crystals 1008 are provided between the pixel electrode 1007 and the counter electrode 1009 is described as an example, but the display device according to the embodiment of the present invention has the structure It is not limited. A liquid crystal element in which a pair of electrodes are provided on the substrate 1001 side as in an IPS type liquid crystal element may also be used.

External light detected by the photodiode 1002 is applied to the substrate 1001 in the direction indicated by an arrow 1025 and reaches the photodiode 1002. [ For example, when the object 1021 to be detected exists, the object 1021 to be detected is shielded from external light, thereby preventing external light from being incident on the photodiode 1002. The display device can function as a touch panel by detecting light incident on the photodiode and its shadow.

Further, the object to be detected may be in close contact with the substrate 1001, and external light passing through the object to be detected may be detected by the photodiode, so that the display device can function as a contact type image sensor.

This embodiment can be suitably implemented in combination with any other embodiment or example.

(Embodiment 5)

In this embodiment, a liquid crystal display device which is an example of a display device according to an embodiment of the present invention, which is different from Embodiment 4, is described.

Except for the description to be described below, Embodiment 3 can be referred to. For example, transistors, a photodiode, a liquid crystal element, and the like may be formed using the same materials as in Embodiment 3. [

23 is an example of a cross-sectional view of a display device different from that of the fourth embodiment. Unlike Embodiment 4 in which light is incident from the substrate side on which the optical sensor is manufactured, light is incident on the optical sensor from the counter substrate side, that is, in this embodiment, through the liquid crystal layer.

Therefore, it is necessary to form an opening in the region of the shielding film 1015 provided on the counter substrate 1013 overlapping with the photodiode 1002. [ As shown in the figure, a color filter 1014 may be formed in the opening. A plurality of optical sensors provided with color filters of R (red), G (green) and B (blue) may be provided in a pixel to form a color sensor, and a color image sensor function may be provided.

In the fourth embodiment, light is incident from the p-type semiconductor layer 1041 side of the photodiode 1002. However, when the photodiode has a structure similar to that of the fourth embodiment, in this embodiment, the n- type semiconductor layer 1043, Light is incident from the side. The reason why light is made incident from the p-type semiconductor layer side is that holes having a short diffusion length can be effectively obtained, that is, a large amount of current can be obtained from the photodiode, and when the design current value is satisfied, n -Type semiconductor layer side.

In this embodiment, the p-type semiconductor layer 1041 and the n-type semiconductor layer 1043 may be replaced with each other in the photodiode 1002, whereby light can easily enter from the p- can do. Note that, in that case, since the gate electrode is connected to the transistor 1003a on the p-type semiconductor layer (anode) side, the operation method is different from that described in the fourth embodiment. Embodiment 1 can be referred to for each operation method.

The photodiode 1002 may be formed to overlap with and on the transistor 1003a as shown in Fig. Needless to say, the photodiode 1002 may overlap with another transistor. In this case, one of the source electrode and the drain electrode of the transistor 1003a can be easily connected to the n-type semiconductor layer 1043 of the photodiode 1002, and light can be emitted from the p-type semiconductor layer 1041 side You can join. Further, the photodiode can be formed to have a large area, thereby improving light receiving sensitivity.

Although not shown, a transmissive conductive layer may be provided on the light incident side of the photodiode 1002 in any one of Figs. 23 and 24. Fig. The conductive layer may be provided on the side opposite to the light incidence side of the photodiode 1002. [ By providing such a conductive layer, the loss of electric charge due to the resistance of the p-type semiconductor layer 1041 or the n-type semiconductor layer 1043 can be reduced.

In this embodiment, a shielding film 2015 is provided on the side opposite to the light receiving side of the photodiode 1002. [ The shielding film 2015 prevents light from the backlight passing through the substrate 1001 and entering the display panel from being directly irradiated onto the photodiode 1002, so that high-precision imaging can be performed. The shielding film 2015 may be formed using an organic resin containing a black pigment such as carbon black or titanium dioxide having a low specific gravity. Alternatively, the shielding film 2015 may be formed using a chromium film.

The external light detected by the photodiode 1002 is incident on the counter substrate 1013 in the direction indicated by the arrow 1025 and reaches the photodiode 1002. [ For example, when the object 1021 to be detected exists, the object 1021 to be detected blocks the external light, and the entrance of the external light to the photodiode 1002 is blocked. The display device can function as a touch panel by detecting the intensity of light entering the photodiode.

Further, the object to be detected may be in close contact with the counter substrate 1013, and external light passing through the object may be detected by the photodiode, so that a display device capable of functioning as a contact type image sensor can be provided.

This embodiment can be suitably implemented in combination with any other embodiment or example.

(Embodiment 6)

In this embodiment, an example of a recording board (such as a blackboard and a whiteboard) using a display panel including an optical sensor is described.

For example, a display panel including an optical sensor is provided at the position of the display panel 9696 in Fig.

The display panel 9696 has an optical sensor and a display element.

Here, it is possible to freely record on the surface of the display panel 9696 with a marker pen or the like.

It is important to note that if letters are written with a marker pen or the like without a fixer, the characters are easily erased.

In addition, in order that the ink of the marker pen can be easily removed, it is preferable that the surface of the display panel 9696 is suitably smooth.

For example, when a glass substrate or the like is used on the surface of the display panel 9696, the surface of the display panel 9696 is sufficiently smooth.

Alternatively, a transparent synthetic resin sheet or the like may be adhered to the surface of the display panel 9696.

As the synthetic resin, for example, an acrylic resin is preferably used. In this case, the surface of the synthetic resin sheet is preferably smooth.

Also, since the display panel 9696 includes a display element, the display panel 9696 can display a specific image, and at the same time, recording characters or the like on the surface of the display panel 9696 with a marker pen It is possible.

Further, the display panel 9696 includes an optical sensor, and therefore, when the display panel 9696 is connected to a printer or the like, the characters recorded with the marker pen can be read and printed.

Further, since the display panel 9696 includes the optical sensor and the display element, by writing characters or drawing pictures on the surface of the display panel 9696 in which the image is displayed, Can be synthesized and displayed on the display panel 9696.

It should be noted that sensing by resistive touch sensors, capacitive touch sensors, etc. may be performed at the same time as writing with a marker pen or the like.

On the other hand, the detection by the optical sensor is excellent in that detection can be performed at any time after something is recorded by a marker or the like even if time elapses.

This embodiment can be suitably implemented in combination with any other embodiment or example.

(Example 1)

In this embodiment, the positions and light sources of the panel are described. 26 is an example of a perspective view showing the structure of the display panel. The display panel shown in Fig. 26 includes a panel 1801 in which pixels including a liquid crystal element, a photodiode, a thin film transistor, and the like are formed between a pair of substrates; A first diffusion plate 1802; A prism sheet 1803; A second diffusion plate 1804; A light guide plate 1805; Reflector 1806; A plurality of backlight light sources 1807; And a circuit board 1809.

A panel 1801, a first diffusion plate 1802, a prism sheet 1803, a second diffusion plate 1804, a light guide plate 1805, and a reflector 1806 are stacked in this order. The light sources 1807 of the backlight are provided at the end portion of the light guide plate 1805. Light from the backlight light sources 1807 diffused by the light guide plate 1805 is transmitted from the opposite substrate side to the panel 1801 by the first diffusion plate 1802, the prism sheet 1803, and the second diffusion plate 1804. [ Lt; / RTI >

In this example, the first diffusion plate 1802 and the second diffusion plate 1804 are used, but the number of diffusion plates is not limited thereto. The number of diffusion plates may be one, or may be three or more. If the diffuser plate is provided between the light guide plate 1805 and the panel 1801, the diffuser plate can be in any position. The diffusion plate may be provided only on the side closer to the panel 1801 than on the prism sheet 1803 or only on the side closer to the light guide plate 1805 than the prism sheet 1803. [

The cross-sectional shape of the prism sheet 1803 shown in Fig. 26 is not limited to the saw-tooth shape, and the shape thereof may be such that the light from the light guide plate 1805 is collected on the panel 1801 side.

The circuit board 1809 is provided with a circuit for generating or processing various signals input to the panel 1801, a circuit for processing various signals output from the panel 1801, and the like. 26, the circuit board 1809 and the panel 1801 are connected to each other via a flexible printed circuit (FPC) It should be noted that the circuit may be connected to the panel 1801 by a chip on glass (COG) method, or a part of the circuit may be connected to the FPC 1811 by a COF (chip on film) method.

26 shows an example in which a control circuit for controlling the driving of the backlight light source 1807 is provided on the circuit board 1809 and the light sources 1807 of the control circuit and the backlight are connected to each other through the FPC 1810 do. However, the control circuit may be formed on the panel 1801, in which case the panel 1801 and the backlight's light sources 1807 are connected to each other via an FPC or the like.

26 shows an edge-light type light source in which backlight light sources 1807 are provided at the edge of the panel 1801, a display panel according to an embodiment of the present invention includes a backlight light source 1807 But it may be a direct-below type display panel that is provided directly under the panel 1801.

For example, when the finger 1812 to be detected approaches from the upper side to the panel 1801, part of the light passing through the panel 1801 is reflected by the finger 1812 and enters the panel 1801 again. The color image data of the finger 1812 to be detected can be obtained by sequentially illuminating the backlight light sources 1807 corresponding to the individual colors and acquiring image data of all colors. Further, the position of the finger 1812 to be detected can be recognized from the image data, and the data of the display image can be combined to provide a function as a touch panel.

This embodiment can be suitably implemented in combination with any other embodiments or examples.

(Example 2)

A display device according to an embodiment of the present invention is characterized by acquiring image data. Therefore, an electronic device using a display device according to an embodiment of the present invention can be further refined by adding a display device as a component.

For example, the display device may be a display device, a laptop computer, or a device having a display for reproducing the content of a recording medium (generally, a recording medium such as digital versatile discs (DVDs) May be used in the image reproducing apparatuses. In addition to the above examples, an electronic device capable of including a display device according to an embodiment of the present invention includes mobile phones, portable game machines, portable information terminals, electronic books, video cameras, digital still cameras, (E.g., head mounted displays), navigation systems, audio playback devices (e.g., car audio components and digital audio players), copiers, facsimiles, printers, multifunction printers, ATMs, vending machines, and the like. Specific examples of such electronic devices are shown in Figs. 27A to 27D.

27A shows a display device including a housing 5001, a display portion 5002, a support table 5003, and the like. A display device according to an embodiment of the present invention can be used in the display portion 5002. [ By using the display device according to one embodiment of the present invention in the display portion 5002, it is possible to provide a display device capable of obtaining image data with high recognition performance and having high-function applications. It should be noted that the display device includes all display devices for displaying information, such as display devices for personal computers, display devices for receiving TV broadcasts, and display devices for displaying advertisements .

27B shows a portable information terminal including a housing 5101, a display portion 5102, a switch 5103, operation keys 5104, an infrared port 5105, and the like. A display device according to an embodiment of the present invention can be used in the display portion 5102. [ By using the display device according to an embodiment of the present invention in the display portion 5102, it is possible to provide a portable information terminal capable of obtaining image data with high recognition performance and equipped with high functional applications.

27C shows a cash dispenser including a housing 5201, a display portion 5202, a coin slot 5203, a bill slot 5204, a card slot 5205, a passbook slot 5206, and the like. The display device according to the embodiment of the present invention can be used in the display portion 5202. [ By using the display device according to the embodiment of the present invention in the display portion 5202, image data can be obtained with high recognition performance and a more accurate automatic cash dispenser can be provided. The automatic teller machine using the display device according to the embodiment of the present invention can read biometric information such as fingerprints, faces, handprints, long passages, patterns of hand veins, irises and the like used for biometric measurement with high accuracy. Thus, a false non-match rate caused by a false sense that a person is identified as another person, and a false acceptance rate caused by misunderstanding the person to be identified as another person, can be suppressed.

27D shows a portable game device 500 including a housing 5301, a housing 5302, a display portion 5303, a display portion 5304, a microphone 5305, speakers 5306, operation keys 5307, a stylus 5308, / RTI > The display device according to an embodiment of the present invention can be used for the display portion 5303 or the display portion 5304. [ By using the display device according to the embodiment of the present invention in the display portion 5303 or the display portion 5304, it is possible to provide a portable game machine which can obtain an image with high recognition performance and can have high functional applications. Note that although the portable game machine shown in Fig. 27D includes two display portions 5303 and 5304, it should be noted that the number of display portions included in the portable game machine is not limited to two.

This embodiment can be suitably implemented in combination with any other embodiment and other examples.

The present application is based on Japanese Patent Application No. 2010-055878 filed in Japan on March 12, 2010, the entire contents of which are incorporated herein by reference.

100: display device 101: pixel array
102: display element control circuit 103: optical sensor control circuit
104: pixel 105: display element part
106: optical sensor unit 107: display element driving circuit
108: Display element driving circuit 109: Optical sensor reading circuit
110: optical sensor driving circuit 201: transistor
202: holding capacitor 203: liquid crystal element
204: photodiode 205: charge storage control transistor
206: reset transistor 207: amplifying transistor
208: selection transistor 209: selection signal line
210: signal charge storage part 211: output signal line
212: reference signal line 213: charge accumulation control signal line
214: reset signal line 215: gate signal line
216: source signal line 230: power supply line
231: Time 232: Time
233: Time 234: Time
235: Time 236: Time
237: Time 238: Time
300: pre-charge circuit 301: transistor
302: Holding capacitor 303: Precharge signal line
311: accumulation period 312: charge retention period
313: Period 314: Charge Retention Period
315: Period 401: Period
402: charge retention period 403: period
404: charge retention period 405: period
406: charge retention period 503: potential
509: Dislocation 510: Dislocation
511: dislocation 513: dislocation
514: Dislocation 802: Amplification transistor
803: charge storage control transistor 804: reset transistor
805: selection transistor 902: amplification transistor
903: charge storage control transistor 904: reset transistor
905: selection transistor 1001: substrate
1002: photodiode 1003a: transistor
1003b: transistor 1003c: transistor
1003d: transistor 1004: holding capacitor
1005: Liquid crystal element 1007: Pixel electrode
1008: liquid crystal 1009: counter electrode
1011: Orientation film 1012: Orientation film
1013: counter substrate 1014: color filter
1015: shielding film 1016: spacer
1017: polarizer 1018: polarizer
1021: Target 1025: Arrow
1030: wiring 1031: protective insulating film
1032: planarization insulating film 1033: insulating film
1035: Signal wiring 1036: Wiring
1041: p-type semiconductor layer 1042: i-type semiconductor layer
1043: n-type semiconductor layer 1141: p-type semiconductor layer
1142: i-type semiconductor layer 1143: n- type semiconductor layer
1601: photodiode 1602: amplifying transistor
1603: charge storage control transistor 1604: reset transistor
1605: selection transistor 1612: signal charge storage part
1613 charge accumulation control signal line 1614 reset signal line
1615: selection signal line 1620: output signal line
1630: power supply line 1631: reference signal line
1701: photodiode 1702: amplifying transistor
1703: charge storage control transistor 1704: reset transistor
1712: Signal charge storage part 1713: Charge storage control signal line
1714: reset signal line 1720: output signal line
1730: power supply line 1731: reference signal line
1801: Panel 1802: Diffusion plate
1803: prism sheet 1804: diffuser plate
1805: light guide plate 1806: reflector
1807: Light source of backlight 1809: Circuit board
1810: FPC 1811: FPC
1812: finger 2001: photodiode
2002: amplification transistor 2003: charge accumulation control transistor
2004; Reset transistor 2012: signal charge storage part
2013: charge accumulation control signal line 2014: reset signal line
2015; Shielding film 2020: output signal line
2025: arrow 2030: power supply line
2031: reference signal line 2112: potential
2113: dislocation 2114: dislocation
2120: Dislocation 2130: Time
2131: Time 2132: Time
2133: Time 2134: Time
2135: time 2201: photodiode
2202: Amplification transistor 2203: Charge storage control transistor
2205: selection transistor 2212: signal charge storage part
2213 charge storage control signal line 2215 selection signal line
2216: reset signal line 2220: output signal line
2230: power supply line 2312: potential
2313: Dislocation 2315: Dislocation
2316: Dislocation 2320: Dislocation
2330: Time 2331: Time
2332: Time 2333: Time
2334: Time 2335: Time
2336: Time 2337: Time
2601: photodiode 2602: amplifying transistor
2606: Capacitor 2612: Signal charge storage part
2615: selection signal line 2616: reset signal line
2620: Output signal line 2630: Power supply line
2712: Dislocation 2715: Dislocation
2716: Dislocation 2720: Dislocation
2730: Time 2731: Time
2732: Time 2733: Time
3001: Dislocation 3002: Dislocation
3003: Dislocation 3480: Dislocation
3501: Dislocation 3502: Dislocation
3503: Dislocation 3712: Dislocation
3715: Dislocation 3716: Dislocation
3720: Dislocation 3730: Time
3731: Time 3732: Time
3733: time 3801: photodiode
3802: Amplification transistor 3803: Charge storage control transistor
3804: reset transistor 3812: signal charge storage part
3813: charge accumulation control signal line 3814: reset signal line
3820: Output signal line 3830: Power supply line
3831: Reference signal line 3832: Reset power supply line
3912: Dislocation 3913: Dislocation
3914: Dislocation 3920: Dislocation
3930: Time 3931: Time
3932: Time 3933: Time
3934: Time 3935: Time
3980: Dislocation 4001: Dislocation
4401: Photodiode 4402: Amplification transistor
4405: selection transistor 4412: signal charge storage part
4415: selection signal line 4416: reset signal line
4420: Output signal line 4430: Power supply line
4480: Dislocation 4501: Dislocation
4502: Dislocation 4701: Dislocation
4705: Dislocation 4711: Dislocation
4712: Dislocation 4713: Dislocation
4714: Dislocation 4715: Dislocation
4720: Duration 4721: Time
4722: Time 4723: Time
4724: Time 4725: Time
4726: Time 4727: Time
4728: Time 4729: Time
4980: selection signal line 5001: housing
5002: Display portion 5003: Support
5101: Housing 5102:
5103: switch 5104: operation key
5105: Infrared port 5201: Housing
5202: display portion 5203: coin slot
5204: Banknote Slot 5205: Card Slot
5206: passbook slot 5301: housing
5302: Housing 5303: Display
5304: Display section 5305: Microphone
5306: Speaker 5307: Operation keys
5308: Stylus 9696: Display panel

Claims (20)

A method for driving a display device,
The display device includes a pixel array,
The pixel array includes:
A first pixel including a first display element part and a first photosensor part;
A second pixel including a second display element portion and a second photosensor portion,
The method comprising:
Simultaneously performing a charge accumulation operation in each of the first photosensor portion and the second photosensor portion while displaying a black image in the pixel array,
Wherein the second pixel is provided in a different row than the first pixel. A method for driving a display device,
The display device includes a plurality of optical sensor units arranged in a matrix, and the plurality of optical sensor units include:
As a first photosensor section,
A first photodiode,
A first transistor including a first gate, a first terminal, and a second terminal, the first terminal being electrically connected to the first photodiode;
A second transistor including a second gate electrically connected to the second terminal;
As the second photosensor section,
A second photodiode,
A third transistor including a third gate, a third terminal and a fourth terminal, the third terminal being electrically connected to the second photodiode,
A fourth transistor including a fourth gate electrically connected to the fourth terminal;
Backlight,
The method comprising:
Turning off the backlight;
Turning on the first transistor and the third transistor at the same time;
Turning on the first transistor and the third transistor simultaneously after turning on the first transistor and the third transistor;
And turning on the backlight after turning off the first transistor and the third transistor,
Wherein the first photosensor section is provided in the first row in the matrix type,
The second photosensor section is provided in the second row in the matrix type,
Wherein the first row is different from the second row. A method for driving a display device,
The display device includes a pixel array,
The pixel array includes:
A plurality of display element units;
Comprising a plurality of photosensor portions,
Wherein each of the plurality of photosensor units comprises:
A photodiode;
A first transistor including a first gate, a first terminal, and a second terminal, the first terminal being electrically connected to the photodiode;
A second transistor including a first gate, a second gate, a third terminal, and a fourth terminal, the second gate electrically connected to the second terminal,
The method comprising:
A first potential is applied to the first gate of each of the plurality of photosensor portions and a second potential is applied to the second terminal and the second gate of the plurality of photosensor portions by irradiating light to the photodiode while displaying a black image on the plurality of display element portions, And changing the second potential to a third potential at a node between the first node and the second node,
The light is irradiated from the display device,
Wherein the plurality of photosensor portions are arranged in a matrix. The method according to claim 1,
Outputting a first signal from the first photosensor section to the first display element section according to a first charge accumulated in the first photosensor section;
And outputting a second signal from the second photosensor section to the second display element section in accordance with a second charge accumulated in the second photosensor section,
And the second signal is output after the first signal is output. 5. The method of claim 4,
Wherein the step of performing the charge accumulation operation, outputting the first signal, and outputting the second signal are performed within one frame period. The method according to claim 1 or 3,
Wherein the display device includes a backlight,
Wherein the black image is displayed by turning off the backlight. The method according to claim 1 or 3,
Wherein the pixel array includes a liquid crystal and a backlight,
Wherein the black image is displayed by shielding light emitted from the backlight with the liquid crystal. The method according to claim 1,
Wherein the charge accumulation operation is performed by irradiating the first photosensor portion and the second photosensor portion with light. The method according to claim 1,
Wherein each of the first photosensor portion and the second photosensor portion comprises a photodiode. The method according to claim 1,
Further comprising performing a reset operation before performing the charge accumulation operation. 3. The method of claim 2,
Wherein each of the first transistor and the third transistor includes an oxide semiconductor. The method of claim 3,
Wherein the first transistor comprises an oxide semiconductor. 13. The method according to claim 11 or 12,
Wherein the oxide semiconductor comprises indium. delete delete delete delete delete delete delete

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