KR101603776B1 - Voltage regulator - Google Patents

Abstract

A voltage regulator with high electric power conversion efficiency is disclosed. A voltage regulator according to the present invention comprises: first and second switches connected in parallel between an input power source and an A node; a power charger/discharger part equipped with a diode and a super capacitor connected between the A node and an L node in series; a third switch connected in parallel to the charger/discharger between the A node and the L node; a fourth switch connected between a C node which is between the super capacitor and the diode, and a ground power source; an LDO connected between the L node and a load to apply constant voltage to the load; a control unit detecting the voltage level of the A node and the L node and controlling the first, third and fourth switches.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a voltage regulator having a high power conversion efficiency,

The present invention relates to a voltage regulator, and more particularly to a voltage regulator having a high power conversion efficiency.

Switching Mode Power Supply (SMPS) and Low-Dropout (LDO) are the most commonly used voltage regulators that provide stable supply of power to the load. While SMPS has an advantage of excellent power conversion efficiency, it is vulnerable to EMI (ElectroMagnetic Interference) and EMC (ElectroMagnetic Compatibility). And LDOs have good EMI / EMC characteristics, but they have poor power conversion efficiency. SCALDO (Supercapacitor Assisted Low Dropout), which combines the advantages of SMPS and LDO, has been developed.

1 shows the configuration of a conventional SCALDO.

SCALDO shown in FIG. 1 increases the power conversion efficiency by storing and reusing the power wasted by the voltage difference between the input voltage and the LDO provided in the supercapacitor. SCALDO uses four switches (SW1 to SW4) and a super capacitor (C) for reuse of electric power. Since the capacitance of the supercapacitor (C) is high in several F units, SW4 can be switched and driven to have an advantage of excellent EMI / EMC characteristics.

However, when the MOSFET is used as the switches SW1 to SW4 in the conventional SCALDO, when the first and third switches SW1 and SW3 are turned off and the second and fourth switches SW2 and SW4 are turned on, The power stored in the capacitor C is not transferred to the LDO and is discharged along the leakage path lp shown in FIG. 1 due to the MOSFET body diode effect of the third switch SW. As a result, current relays such as a solid state relay or a photovoltaic relay are used as the switches (SW1 to SW4), but since relays have a large turn-on resistance (Ron) and consume a certain amount of current for switching operation, Consumption occurs. This is a major cause of lowering the power conversion efficiency of SCALDO as a whole.

SCALDO is also configured to store and reuse unnecessary power consumed by the input voltage and output voltage difference in the super capacitor (C). That is, the input voltage V _in is divided by the voltage V _C of the supercapacitor _C and the LDO (V _L ) to become V _in = V _C + V _L. However, since the initial voltage of the supercapacitor C is V _C = 0 in the state where the first and third switches SW1 and SW3 are turned on at the beginning of operation and the second and fourth switches SW2 and SW4 are turned off , V _in = V _L and the input voltage V _in is directly transferred to the output stage LDO for a short time until the super capacitor C is charged. Therefore, LDO is likely to be damaged. The larger the voltage difference between the input voltage and the output voltage, the more serious the problem becomes.

Korean Patent Publication No. 10-2014-0089814 (published on July 16, 2014)

It is an object of the present invention to provide a voltage regulator having a high power conversion efficiency.

According to an aspect of the present invention, there is provided a voltage regulator including first and second switches connected in parallel between an input power source and an A node; A power boosting unit including a super capacitor and a diode connected in series between the A node and the L node; A third switch connected between the node A and the node L in parallel with the power supply; A fourth switch connected between a node C between the supercapacitor and the diode and a ground power source; An LDO connected between the L node and the load for applying a constant voltage to the load; And a control unit for controlling the first, third, and fourth switches by sensing voltage levels of the A node and the L node, .

The first and third switches are implemented as PMOS transistors, and the second and fourth switches are implemented as NMOS transistors.

The second switch has a gate which is higher than a threshold voltage ( _{VSW2_th} ) of the second switch and lower than a sum (V _{LDO_min} + V _{SW2_th} ) of a minimum input voltage (V _{LDO_min} ) for driving the LDO and a threshold voltage of the second switch And a first reference voltage (Vref1) having a value is applied.

Wherein the control unit applies a first control signal of a first level to the first and fourth switches at an initial stage of operation of the voltage regulator and applies a second control signal of a second level to the third switch, And the third and fourth switches are turned on to drive the regulator in the preliminary charging mode.

The control unit senses the voltage level of the node A in the pre-charge mode, and the voltage level of the node A is lower than the threshold voltage (V _{SW2_th} ) of the second switch at the first reference voltage (Vref1) to determine if it exceeds a predetermined second reference voltage (Vref2 <Vref1- _{SW2_th} V) and, when the voltage level of the node a is greater than the second reference voltage, turn the first and second control signals are switched to the charging mode, .

The controller senses the voltage level of the L node in the charging mode to determine whether the voltage level of the L node is lower than a predetermined third reference voltage (Vref3 = V _{LDO_min} ) to the minimum input voltage (V _{LDO_min} ) And when the voltage level of the L node is lower than the third reference voltage, the first and second control signals are inverted to switch to the discharge mode.

The control unit senses the voltage level of the L node in the discharge mode, and when the voltage level of the L node becomes lower than the third reference voltage, the control unit inverts the first and second control signals, .

Wherein the controller senses a voltage level of the node A in the charge mode and the discharge mode, and when the voltage level of the node A is lower than a second reference voltage, the first and fourth switches The control signal is applied and the second control signal of the second level is applied to the third switch to switch back to the preliminary charging mode.

The voltage regulator may further include a load capacitor connected between the L node and the ground power supply in parallel with the LDO.

Therefore, it is possible to obtain a high power conversion efficiency by reducing the power consumption for the switch driving of the present invention, to prevent the overvoltage from being applied to the internal LDO at the beginning of operation, to secure safety and reliability, .

1 shows the configuration of a conventional SCALDO.
2 shows a voltage regulator according to an embodiment of the present invention.
3 shows an operation algorithm of the control unit of the voltage regulator of FIG.
4 to 6 show an equivalent circuit according to the operation mode of the voltage regulator of FIG.
7 shows a voltage waveform at each node in the operation of the voltage regulator of FIG.

In order to fully understand the present invention, operational advantages of the present invention, and objects achieved by the practice of the present invention, reference should be made to the accompanying drawings and the accompanying drawings which illustrate preferred embodiments of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be described in detail with reference to the preferred embodiments of the present invention with reference to the accompanying drawings. However, the present invention can be implemented in various different forms, and is not limited to the embodiments described. In order to clearly describe the present invention, parts that are not related to the description are omitted, and the same reference numerals in the drawings denote the same members.

Throughout the specification, when an element is referred to as "including" an element, it does not exclude other elements unless specifically stated to the contrary. The terms "part", "unit", "module", "block", and the like described in the specification mean units for processing at least one function or operation, And a combination of software.

2 shows a voltage regulator according to an embodiment of the present invention.

Referring to FIG. 2, the voltage regulator of the present invention includes four switches SW1 to SW4, a supercapacitor C, a diode D, an LDO (LDO), and a control unit CON.

The first switch SW1 and the second switch SW2 of the four switches SW1 to SW4 are connected in parallel between the input power source and the node A (IN). The first switch SW1 is used as a charge switch for controlling whether or not the voltage regulator is charged while the operation of the voltage regulator is performed. The first switch SW1 is turned on / off in response to the first control signal Q1 applied from the control unit CON to transfer the input voltage Vin to the node A to charge the supercapacitor C . The first switch SW1 is preferably implemented as a PMOS transistor so that a voltage drop does not occur during the transfer of the input voltage Vin.

The second switch SW2 functions as a pre-charge switch for precharging the supercapacitor C in the pre-charge mode before the voltage regulator performs a normal operation. A first reference voltage Vref1 having a predetermined voltage level is always applied to the gate of the second switch SW2. The second switch SW2 is preferably implemented as an NMOS transistor for fast switching operation and ease of control and the first reference voltage Vref1 is higher than the threshold voltage V _{SW2_th} of the second switch SW2, (V _{LDO_min} + V _{SW2_th} ) of the minimum input voltage (V _{LDO_min} ) for driving and the threshold voltage of the second switch (V _{LDO_min} + V _{SW2_th} ). The second switch SW2 is implemented as an NMOS transistor so that the input voltage V _in of the large voltage level to the LDO LDO in the preliminary charging mode is supplied to the LDO 2 for a short time before the super capacitor C is charged. (LDO). That is, the LDO (LDO) is prevented from being damaged.

The conventional SCALDO shown in FIG. 1 is configured such that one switch SW1 transfers the input voltage Vin to the supercapacitor C, but as shown in FIG. 2, in the present invention, two The switches SW1 and SW2 are configured to be turned on and off differently according to the operation mode of the voltage regulator so as to transmit the input voltage Vin to the super capacitor C. [

The supercapacitor C and the diode D are connected in series between the A node (ndA) and the L node (ndL). The supercapacitor C receives the input voltage Vin through the node A and charges the capacitor A to the node A to discharge the charged voltage to the LDO through the diode D1. Electrode is connected, and the - electrode is connected to the diode (D).

The super capacitor C is charged from the charge voltage of 0 V to the second reference voltage Vref2 level in the preliminary charge mode and then charged and discharged alternately in the charge mode and the discharge mode.

Meanwhile, the diode D protects the input voltage Vin or the discharge voltage of the supercapacitor C, which is applied to the L node ndL, to be transferred to the LDO (LDO) from flowing back to the supercapacitor C .

The supercapacitor C and the diode D function as a power supply for charging the input voltage Vin and discharging it to the LDO.

On the other hand, the third switch SW3 is connected in parallel with the input charging portion between the A node (ndA) and the L node (ndL). The third switch SW3 is turned on / off in response to the second control signal Q2 applied from the control unit CON to change the path through which the input voltage Vin is delivered according to the operation mode of the voltage regulator, (C) is charged or discharged. The third switch SW3 is also preferably implemented as a PMOS transistor like the first switch SW1 so that no voltage drop occurs.

The fourth switch SW4 connected between the node C and the ground voltage Vss between the super capacitor C and the diode D is connected to the first control signal Q1 in the same manner as the first switch SW1 And changes the path through which the input voltage Vin is transmitted in accordance with the operation mode of the voltage regulator together with the third switch SW so that the equivalent circuit of the voltage regulator is deformed. The fourth switch SW4 connected to the ground voltage Vss is preferably implemented as an NMOS transistor as a pull-down transistor.

The LDO (LDO) connected between the L node (ndL) and the load (LOAD) converts the voltage transferred through the L node (ndL) into a stable voltage of a predetermined voltage level and outputs it to the load LOAD. The LDO (LDO) can be implemented using the conventional LDO as it is. Since the LDO (LDO) is a well-known technology, the detailed configuration of the LDO is not described in detail.

As shown in FIG. 2, the voltage regulator of the present invention includes a capacitor C _LDO connected between an L node ndL and a ground voltage Vss to prevent an unnecessary signal from being applied to the _{LDO LDO} Respectively.

Meanwhile, the control unit CON senses the voltage levels V _A and V _L of the node A and the node L and outputs the first and second signals Q1 and Q2 to the first, 4 switches SW1, SW3, and SW4 to control ON / OFF of the first, third, and fourth switches SW1, SW3, and SW4. The control unit CON applies the first control signal Q1 to the first and fourth switches SW1 and SW4 and the second control signal Q2 to the third switch SW3.

FIG. 3 shows an operation algorithm of the control unit of the voltage regulator of FIG. 2, FIGS. 4 to 6 show equivalent circuits according to the operation mode of the voltage regulator of FIG. 2, And the voltage waveforms in FIG.

The operation of the voltage regulator of the present invention will be described with reference to FIGS. 3 to 7. First, the control unit CON controls the voltage level of the first level (here, high level) in the preliminary charging mode Level) and the second control signal Q2 of the second level (here, low level) (S10).

When the first switch SW1 is implemented as a PMOS transistor and the fourth switch SW4 is implemented as an NMOS transistor, the first switch SW1 is turned off in response to the first control signal Q1 of the first level While the fourth switch SW4 is turned on. And the third switch SW3 implemented by the PMOS transistor is turned on in response to the second control signal Q2 of the second level.

The second switch SW2 to which the first reference voltage Vref1 is applied to the gate is turned on by the voltage difference between the input voltage Vin and the A node At. When the second switch SW2 is turned on, the voltage V _{A at} the node _A is 0 V since it is in a state before the super capacitor C is charged. Accordingly, the input voltage Vin is transferred to the node A (A) through the second switch SW2 instead of the first switch SW1 in the off state. However, since the second switch SW2 is an NNMOS transistor and the first reference voltage Vref1 for turning on the second switch SW2 is applied to the gate of the second switch SW2, A voltage level Vref1- _{Vsw2_th} obtained by subtracting the threshold value _{Vsw2_th} of the second switch SW2 from the first reference voltage Vref1 is applied. That is, as illustrated in the equivalent circuit of Figure 4, the voltage (V Vref1- _{SW2_th)} of the node A (ndA) is implemented as an equivalent input voltage, replacing the input voltage (Vin).

Since the third switch SW3 is turned on, the LDO (LDO) is directly connected to the A node in the equivalent circuit because the A node and the L node are not distinguished. Since the fourth switch SW4 is turned on, the supercapacitor C is connected between the node A and the ground voltage Vss. In other words, the supercapacitor C is connected in parallel with the LDO (LDO). Since the diode D is connected between the C node (ndC) and the L node (ndL), the diode D is connected in the reverse direction and is in the open state and is omitted in the equivalent circuit.

In the equivalent circuit, the equivalent input voltage Vref1- _{Vsw2_th} is expressed in a form in which the input voltage Vin is substituted, but the voltage level of the A node actually becomes higher than the voltage level of the supercapacitor C And increases with the increase in the number. The super capacitor (C) may be charged in the pre-charging mode (a period) equivalent to the input voltage (V Vref1- _{SW2_th).} In other words, the voltage level of the A node (in) can rise from the non-charged 0 V of the _{supercapacitor} C to the equivalent input voltage (Vref1 - V _{SW2 - th} ) level.

On the other hand, the control unit CON senses the voltage level of the node A (S20), and discriminates whether the voltage level of the node A (A) exceeds the predetermined second reference voltage Vref2 (S30). When it is determined that the voltage level of the node A is higher than the predetermined second reference voltage Vref2, the first and second control signals Q1 and Q2 are inverted to set the voltage regulator in the charging mode (S40). Wherein the second reference voltage (Vref2) is set to the charging voltage, i.e., voltage level lower than the maximum voltage of the equivalent input voltage (V Vref1- _{SW2_th)} of the node A (ndA) in the pre-charge mode of the super capacitor (C).

Therefore, the supercapacitor C is charged up to the second reference voltage Vref2 in the precharge mode (period a), and the voltage corresponding to the voltage level charged in the supercapacitor C is applied to the LDO (LDO) It is possible to prevent a large voltage from being applied and damaged by the LDO (LDO) at the beginning of the operation of the regulator.

The control unit CON inverts the first and second control signals Q1 and Q2 to switch the first control signal Q1 of the second level and the second control signal Q2 of the first level, To the first, third, and fourth switches SW1, SW3, and SW4.

Accordingly, the first switch SW1 is turned on and the third and fourth switches SW3 and SW4 are turned off. When the first switch SW1 is turned on, the input voltage Vin is immediately applied to the node A and the second switch SW2 is turned on as the voltage level of the node A becomes equal to the input voltage Vin. Is turned off.

The supercapacitor C and the diode D and the LDO LDO are turned off from the input voltage Vin as shown in the equivalent circuit of Fig. 5 because the third and fourth switches SW3 and SW4 are turned off. They are connected in series. Since the voltage level of the A node instantaneously rises to the input voltage Vin but the supercapacitor C and the LDO LDO are connected in series, the voltage of the L node (LDO) applied to the LDO (LDO) voltage (V _LDO) of ndL) is the sum of the threshold voltage (V _D) of the charge and a diode (D) charging the super capacitor (C) from an input voltage (Vin) subtracting the voltage (Vin - (Vc + V _D )). Since the supercapacitor C is charged by the second reference voltage Vref2 in the preliminary charging mode, the voltage V _LDO of the L node ndL at the beginning of the charging mode is Vin - (Vref2 + V _D ). Here, the second reference voltage Vref2 is the supercapacitor voltage Vc charged in the super capacitor C at the initial stage of the charge mode.

This is because the maximum value of the voltage applied to the supercapacitor C in the preliminary charging mode is set to the second reference voltage Vref2 and the input voltage Vin is applied in the charging mode, The voltage equal to or higher than the two reference voltages Vref2 is charged. Since the voltage at the L node (ndL) is Vin - (Vc + V _D ) and this value drops to the third reference voltage (Vref3 = V _{LDO_min} ) as the charging progresses, a capacitor (C) is Vc = Vin - the voltage (Vref3 + V _D) is charged.

As the supercapacitor C is charged and the supercapacitor voltage Vc becomes higher, the voltage level of the L node ndL applied to the LDO (LDO) becomes lower as shown in Fig.

The controller (CON) is by detecting a voltage level (V _LDO) of the L node (ndL) (S50), L node (ndL) voltage level (V _LDO) to a minimum input voltage (V for driving the LDO (LDO) of _{LDO_min} ) is lower than a predetermined third reference voltage (Vref3 = V _{LDO_min} ) (S60).

The control unit CON inverts the first and second control signals Q1 and Q2 again to determine whether the voltage level V _LDO of the L node ndL is lower than the third reference voltage Vref3, To the discharge mode (section c in Fig. 7).

In the discharge mode (period c), the control unit CON again applies the first control signal Q1 of the first level to the first and fourth switches SW1 and SW4, and the second control signal Q2 of the second level To the third switch SW3. Accordingly, the first switch SW1 is turned off, and the third and fourth switches SW3 and SW4 are turned on. In the discharge mode, the second switch SW2 is in a state where the voltage level of the node A is raised due to the charging of the supercapacitor C in the previous charging mode (V _A > Vref 3> Vref 1 - V _{SW 2} - _th ) 2 is not turned on because the sum of the source voltage (V _A ) and the threshold voltage (V _{SW2_th} ) of the switch (SW2) is larger than the gate voltage (Vref1).

Since the first switch SW1 is turned off and the third and fourth switches SW3 and SW4 are turned on, as shown in the equivalent circuit of Fig. 6, in the discharge mode (section c) Is omitted. The voltage Vc charged in the supercapacitor C is applied to the L node ndL via the third switch SW3 turned on at the maximum charge voltage Vc_max at the initial stage of the discharge mode and is supplied to the L node ndL The applied voltage (V _LDO = Vc_max) is not applied to the C node (ndC) by the diode (D) and is applied to the LDO (LDO). That is, the power stored in the super capacitor is discharged to the LDO (LDO). As the supercapacitor C discharges, the voltage level (V _LDO ) of the L node (ndL) is lowered.

The control unit CON again detects the voltage level V _LDO of the L node ndL which is going to be lowered (S50). Then, it is determined whether the voltage level (V _LDO ) of the L node is lower than the third reference voltage (Vref3 = V _{LDO_min} ) (S60). This is to determine whether or not the super capacitor C is overdischarged. If it is determined that the voltage level V _LDO of the L node is lower than the third reference voltage Vref3, the control unit CON again inverts the first and second control signals Q1 and Q2.

When the first and second control signals Q1 and Q2 are inverted, the first switch SW1 is turned on and the second to fourth switches SW2 to SW4 are turned off. Therefore, it is configured as shown in the equivalent circuit of FIG. 5 and operates again in the charging mode (section b). That is, the voltage regulator repeatedly discharges the super capacitor C by repeating the charging mode (section b) and the discharging mode (section c).

In the above description, the control unit CON detects the voltage level V _A of the node _A and switches to the charging mode (period b) only in the pre-charging mode (period a). However, The voltage level V _A of the node _A can be sensed and switched to the pre-charge mode (section a) even in the charging mode (section b) and the discharge mode (section c). This is because when the voltage level of the supercapacitor voltage Vc becomes lower than the second reference voltage Vref2 due to unexpected overdischarge of the super capacitor C, an instantaneous large voltage is applied to the LDO LDO, LDO) is prevented from being damaged.

As described above, the voltage regulator of the present invention can realize all of the first to fourth switches SW1 to SW4 as a MOSFET, so that the power consumption for driving the switch can be reduced and a high power conversion efficiency can be obtained.

The method according to the present invention can be implemented as a computer-readable code on a computer-readable recording medium. A computer-readable recording medium includes all kinds of recording apparatuses in which data that can be read by a computer system is stored. Examples of the recording medium include a ROM, a RAM, a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, and the like, and a carrier wave (for example, transmission via the Internet). The computer-readable recording medium may also be distributed over a networked computer system so that computer readable code can be stored and executed in a distributed manner.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art.

Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

Claims (9)

First and second switches connected in parallel between an input power supply and an A node;
A power boosting unit including a super capacitor and a diode connected in series between the A node and the L node;
A third switch connected between the node A and the node L in parallel with the power supply;
A fourth switch connected between a node C between the supercapacitor and the diode and a ground power source;
An LDO connected between the L node and the load for applying a constant voltage to the load; And
A control unit for sensing the voltage level of the A node and the L node and controlling the first, third and fourth switches; And a voltage regulator. The method of claim 1, wherein the first and third switches are implemented as PMOS transistors,
And the second and fourth switches are implemented as NMOS transistors. 3. The apparatus of claim 2, wherein the second switch
The in gate having a value below the minimum input voltage (V _{LDO_min)} to the sum (V _{LDO_min} + V _{SW2_th)} of the threshold voltage of the second switch is higher than a threshold voltage (V _{SW2_th)} for driving the LDO of the second switch 1 &lt; / RTI &gt; reference voltage (Vref1) is applied. 4. The apparatus of claim 3, wherein the control unit
The first control signal of the first level is applied to the first and fourth switches at the beginning of the operation of the voltage regulator and the second control signal of the second level is applied to the third switch to turn off the first switch And the third and fourth switches are turned on to drive the regulator in a preliminary charging mode. 5. The apparatus of claim 4, wherein the control unit
The voltage level of the node A is lower than the threshold voltage V _{SW2_th} of the second switch at the first reference voltage Vref1 by sensing the voltage level of the node A in the _pre- Wherein the first control signal is switched to the charge mode when the voltage level of the node A exceeds the second reference voltage by inverting the first and second control signals to determine whether the voltage level of the node A exceeds the reference voltage Vref2 < Vref1 - V _{SW2_th} , Voltage regulator. 6. The apparatus of claim 5, wherein the control unit
The voltage level of the L node is _{discriminated} in the charging mode to determine whether the voltage level of the L node is lower than a predetermined third reference voltage (Vref3 = V _{LDO_min} ) by the minimum input voltage (V _{LDO_min} ) And when the voltage level of the node becomes lower than the third reference voltage, inverts the first and second control signals to switch to the discharge mode. 7. The apparatus of claim 6, wherein the control unit
Wherein the controller detects the voltage level of the L node in the discharge mode and reverses the first and second control signals to switch to the charge mode when the voltage level of the L node becomes lower than the third reference voltage Voltage regulator. 8. The apparatus of claim 7, wherein the control unit
The first node receives the first control signal of the first level by the first and fourth switches when the voltage level of the node A is lower than the second reference voltage by sensing the voltage level of the node A in the charge mode and the discharge mode, And applies the second control signal of the second level to the third switch to switch back to the pre-charge mode. 9. The voltage regulator of claim 8, wherein the voltage regulator
And a load capacitor connected between the L node and the ground power supply in parallel with the LDO.

Images