JP4889398B2 - Constant voltage power circuit - Google Patents

Description

  The present invention relates to a constant voltage power supply circuit including a light load constant voltage circuit having a small supply power and a heavy load constant voltage circuit having a large supply power.

  In recent years, in consideration of environmental problems, power saving of electronic devices has been demanded. This tendency is particularly remarkable in battery-driven electronic devices. In order to save power, it is important to reduce the power consumed by the electronic device, and to improve the power efficiency of the power supply circuit itself to suppress wasteful power consumption.

One method of reducing power consumption in an electronic device is to reduce power consumption by setting a standby state in which circuit operation in the electronic device is stopped when the electronic device is not operating. However, even if the electronic device shifts to the standby state, a sufficient power saving effect cannot be expected if the power efficiency of the power supply circuit itself is poor.
In the constant voltage circuit constituting the power supply circuit, the constant voltage circuit itself consumes power separately from the power output to the electronic device. If the power consumption is large, the power efficiency of the power supply circuit deteriorates. Since the power consumed by the constant voltage circuit itself does not decrease even when the output current decreases, the power efficiency decreases as the output current decreases.

In general, a constant voltage circuit having a large maximum output current can output a large amount of power, but the power consumed by the circuit itself is large. If the output power is reduced, the power efficiency becomes extremely poor. Conversely, a constant voltage circuit with a small maximum output current has limited power that can be output, but the power consumed by the circuit itself is also small, and it is high by supplying power to electronic devices that have low power consumption such as in a standby state. Power efficiency can be obtained.
When using a power supply circuit that consists only of a constant voltage circuit with a large maximum output current, the power consumption of the constant voltage circuit itself is large even when the electronic device shifts to the standby state, and as a result, a sufficient power saving effect can be obtained. I can't. Therefore, when the electronic device shifts to a standby state that does not require a large amount of power, it is preferable to use only a constant voltage circuit that consumes less power.

  Therefore, a heavy load constant voltage circuit with a large maximum output current and a light load constant voltage circuit with a small maximum output current are both incorporated in the power supply circuit. When power is supplied and power is switched to the standby state, which operates with less power than normal operation, power is supplied from the light load constant voltage circuit to minimize power consumption in the standby state and save power consumption. It has been proposed to improve the power effect (see, for example, Patent Document 1).

Examples of the power supply circuit including the light load constant voltage circuit and the heavy load constant voltage circuit include power supply circuits having the following configurations (1) and (2).
(1) A control circuit for controlling the power consumption state is provided, and either one of the light load constant voltage circuit and the heavy load constant voltage circuit is operated based on the state of the control signal output from the control circuit. Power circuit.
(2) Provided with detection means for detecting the power consumption, and configured to operate either the light load constant voltage circuit or the heavy load constant voltage circuit based on the power consumption detected by the detection means Power circuit.
JP 2001-197731 A

  When the power supply circuit of (1) above is switched from the heavy load constant voltage circuit to the light load constant voltage circuit when the output current is larger than the maximum output current of the light load constant voltage circuit, the output voltage drops rapidly. As a result, there is a problem of causing a malfunction.

  In the power supply circuit of (2) above, even when the output current is momentarily reduced, the operation / stop of the light load constant voltage circuit and the heavy load constant voltage circuit is switched. There is a problem that it is likely to occur and an unexpected noise is generated to cause a malfunction.

  Therefore, the present invention switches the heavy load constant voltage circuit from the heavy load constant voltage circuit to the light load constant voltage circuit in the power supply circuit including the heavy load constant voltage circuit and the light load constant voltage circuit, An object of the present invention is to provide a power supply circuit that is not affected by an instantaneous change in output current.

  The first aspect of the constant voltage power supply circuit of the present invention includes a heavy load constant voltage circuit, a light load constant voltage circuit having a maximum output current smaller than that of the heavy load constant voltage circuit, a heavy load constant voltage circuit, and a light load. From a switching unit that activates either a heavy load constant voltage circuit or a light load constant voltage circuit when a control signal to activate any one of the load constant voltage circuits is input, and any one of the operated constant voltage circuits A comparison unit that compares the detected output current with a preset threshold current in order to detect the output current from the output unit. The circuit is equipped with a current detection circuit that outputs a signal according to the comparison result in the comparison circuit. The switching unit also receives the output signal of the current detection circuit in addition to the control signal, and the control signal is a constant voltage circuit for light loads. Is in a state to operate, One current output current from the detecting circuit is characterized in that to only activate the constant voltage circuit for a light load when it is input an output signal indicating that it is below the threshold current.

  The threshold current is preferably a current value close to the maximum output current value of the light load constant voltage circuit or smaller than the maximum output current value of the light load constant voltage circuit.

  When the output current falls below the threshold current, the change of the current signal from the current detection circuit is delayed for a fixed time and input to the switching unit. When the output current exceeds the threshold current, the current detection circuit It is preferable to further include a current signal delay circuit that inputs the current signal to the switching unit without delaying the change.

  In the constant voltage power supply circuit of the first aspect, when the control signal changes from a state where the heavy load constant voltage circuit is to be operated to a state where the light load constant voltage circuit is to be operated, the change of the control signal is changed for a certain time. When the state is changed so that the light load constant voltage circuit is activated and the heavy load constant voltage circuit is activated, the switching unit is delayed without delaying the change of the control signal. There may be further provided a control signal delay circuit to be inputted to.

  The current detection circuit may be a current limiting circuit for limiting the output current from the output unit within a certain current value, which has a function of detecting the output current from the output unit.

  A second aspect of the constant voltage power supply circuit of the present invention includes a heavy load constant voltage circuit, a light load constant voltage circuit having a maximum output current smaller than that of the heavy load constant voltage circuit, a heavy load constant voltage circuit, and a light load. From a switching unit that activates either a heavy load constant voltage circuit or a light load constant voltage circuit when a control signal to activate any one of the load constant voltage circuits is input, and any one of the operated constant voltage circuits An output unit that outputs a constant voltage according to the output of the control signal when the control signal changes from a state where the constant voltage circuit for heavy loads should be operated to a state where the constant voltage circuit for light loads should be operated The control signal delay circuit further includes a control signal delay circuit that delays the change of the control signal by a predetermined time and inputs the delayed control signal to the switching unit.

  The constant voltage power supply circuit of the first aspect includes a comparison circuit that compares the detected output current with a preset threshold current in order to detect the output current from the output unit, and the comparison result in the comparison circuit The switching unit receives the output signal of the current detection circuit in addition to the control signal, and the control signal is in a state to operate the light load constant voltage circuit, and Since the constant voltage circuit for light load is operated only when the output signal indicating that the output current is below the threshold current is input from the current detection circuit, the output current becomes below the threshold current. Until, the control signal does not switch to the light load constant voltage circuit even if the light load constant voltage circuit should be activated, and the output voltage suddenly switches to the light load constant voltage circuit with a large output current. Drop to It is eliminated, thereby reducing the noise of the output voltage.

  If the threshold current is set to a current value close to the maximum output current value of the light load constant voltage circuit or smaller than the maximum output current value of the light load constant voltage circuit, the output from the output section Since the light load constant voltage circuit does not operate in a state where the current is larger than that of the light load constant voltage circuit, it is possible to eliminate a sudden drop in the output voltage.

  When the output current falls below the threshold current, the change in the current signal from the current detection circuit is delayed by a fixed time and input to the switching unit, and the current detection circuit when the output current exceeds the threshold current If there is further provided a current signal delay circuit that is input to the switching unit without delaying the change of the current signal from, a certain time elapses after the output current detected by the current detection circuit falls below the threshold current Until then, the light load constant voltage circuit will not operate, so even if the output current fluctuates up and down across the threshold current, it will not switch to the light load constant voltage circuit repeatedly, and noise will be generated in the output voltage. Can be prevented.

  When the control signal changes from a state where the heavy load constant voltage circuit is to be operated to a state where the light load constant voltage circuit is to be operated, the change in the control signal is delayed for a certain time and input to the switching unit. Provided with a control signal delay circuit for inputting to the switching unit without delaying the change of the control signal when the load constant voltage circuit is changed from the state to be operated to the state to be activated. In this case, the light load constant voltage circuit will not operate until a certain time has elapsed after the control signal changes to the state in which the light load constant voltage circuit should be operated. Thus, the constant voltage circuit for light load is not operated, and the output voltage can be prevented from rapidly decreasing.

The constant voltage circuit is often provided with a current limiting circuit that controls the output current while constantly monitoring the output current so that the current output from the output unit does not exceed the maximum output current value. Such a current limiting circuit has a function of detecting the output current in order to monitor the output current.
Therefore, if the current detection circuit used in the constant voltage power supply circuit according to the first aspect includes a current limiting circuit for limiting the output current from the output unit within a certain current value, the circuit is It can be simplified and the increase in cost can be suppressed.

  The second aspect of the constant voltage power supply circuit of the present invention is that the control signal changes when the control signal changes from a state where the heavy load constant voltage circuit is to be operated to a state where the light load constant voltage circuit is to be operated. Since the control signal delay circuit that delays the signal for a certain period of time and inputs it to the switching unit is provided for the light load until a certain time elapses after the control signal changes to the control signal for operating the constant voltage circuit for the light load Even if the output current fluctuates up and down across the threshold value without switching to the constant voltage circuit, switching to the light load constant voltage circuit is no longer repeated, and noise in the output voltage can be prevented.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram schematically showing an embodiment of a constant voltage power supply circuit according to the present invention.

  The power supply circuit according to this embodiment includes a heavy load constant voltage circuit 4 that operates during normal operation and outputs a voltage, and a light load constant voltage circuit that operates during a standby state and supplies a smaller voltage than the heavy load constant voltage circuit 4. The circuit includes a voltage circuit 6, a current detection circuit 2 that detects a current corresponding to the output voltage from the heavy load constant voltage circuit 4, an inverter circuit (INV) 8, and an AND circuit 10.

The heavy load constant voltage circuit 4 is a high-efficiency constant voltage circuit with a large maximum output current and a high efficiency at heavy loads, and the light load constant voltage circuit 6 is a high-efficiency constant voltage circuit with a small maximum output current and a light load. is there.
The current detection circuit 2 detects a current corresponding to the voltage output from the output terminal _Vout , and the output signal becomes a high level when the detected current value falls below the threshold current, It goes low when the detected current value is higher than the threshold current.
In this embodiment and the following embodiments, the maximum output current value of the light load constant voltage circuit 6 is set as the threshold current.

  The output signal of the current detection circuit 2 is input to one terminal of the AND circuit 10. A control signal ECO is input to the other terminal of the AND circuit 10. The control signal ECO becomes low level when the heavy load constant voltage circuit 4 is operated, and becomes high level when the light load constant voltage circuit 6 is operated.

  The AND circuit 10 outputs a high level signal only when both the output signal from the current detection circuit 2 input to the two terminals and the control signal ECO are at a high level, and either one of the input signals is When it is low level, it outputs a low level signal.

  The output signal of the AND circuit 10 is inverted on the one hand by the inverter circuit 8 and input to the chip enable terminal CE1 of the heavy load constant voltage circuit 4, and on the other hand to the chip enable terminal CE2 of the light load constant voltage circuit 6. ing. That is, when a high level signal is output from the AND circuit 10, a low level signal is input to the chip enable terminal CE1 of the heavy load constant voltage circuit 4, and to the chip enable terminal CE2 of the light load constant voltage circuit 6. A high level signal is input. Conversely, when a low level signal is output from the AND circuit 10, a high level signal is input to the chip enable terminal CE1 of the heavy load constant voltage circuit 4, and the chip enable terminal CE2 of the light load constant voltage circuit 6 is output. A low-level signal is input to.

  Both the heavy load constant voltage circuit 4 and the light load constant voltage circuit 6 operate when a high level signal is input, and stop when a low level signal is input. That is, when the control signal ECO is at a high level and the current value detected by the current detection circuit 2 is equal to or less than the threshold current, the light load constant voltage circuit 6 operates, and the heavy load constant voltage Circuit 4 stops. Therefore, if the current value detected by the current detection circuit 2 is higher than the threshold current even if the control signal ECO is at the high level, the output signal from the AND circuit 10 is at the low level, and the light load constant is set. The voltage circuit 6 does not operate.

  Next, a configuration example of the constant voltage power supply circuit of FIG. 1 will be described in detail. FIG. 2 is a circuit diagram showing in detail a configuration example of the constant voltage power supply circuit of FIG.

The heavy load constant voltage circuit 4 includes an operational amplifier circuit 11, an output transistor M1 composed of a PMOS transistor, and series resistors R1 and R2 that generate a feedback voltage corresponding to the output voltage from the output terminal _Vout .
A feedback voltage is input to the non-inverting input terminal (+ terminal) of the operational amplifier circuit 11, and a reference voltage _Vref is input to the inverting input terminal (−terminal).

The source of the output transistor M1 is connected to the power input terminal V _in, the drain is connected to the output terminal V _out, the gate is connected to the output terminal of the operational amplifier circuit 11.
The operational amplifier circuit 11 includes a chip enable terminal CE1, and the output terminal of the AND circuit 10 is connected to the chip enable terminal CE1 via the inverter circuit 8. The operational amplifier circuit 11 operates when a high level signal is input to the chip enable terminal CE1, and stops when a low level signal is input, so that the current consumption becomes substantially zero.

The light load constant voltage circuit 6 includes an operational amplifier circuit 14, an output transistor M2 composed of a PMOS transistor, and series resistors R3 and R4 that generate a feedback voltage corresponding to the output voltage from the output terminal _Vout .
A feedback voltage is input to the non-inverting input terminal of the operational amplifier circuit 14, and a reference voltage _Vref is input to the inverting input terminal.

The source of the output transistor M2 is connected to the power input terminal V _in, the drain is connected to the output terminal V _out, the gate is connected to the output terminal of the operational amplifier circuit 14.
The operational amplifier circuit 14 includes a chip enable terminal CE2, and the output terminal of the AND circuit 10 is connected to the chip enable terminal CE2. The operational amplifier circuit 14 operates when a high-level signal is input to the chip enable terminal CE2, and stops when a low-level signal is input, so that the current consumption becomes substantially zero.

The current detection circuit 2 includes a comparator 12, a PMOS transistor M3, and a resistor R5.
The source of the PMOS transistor M3 is connected to the power supply input terminal Vin, and the drain is grounded via the resistor R5. The gate of the PMOS transistor M3 is connected to the gate of the output transistor M1 of the heavy load constant voltage circuit 4, and constitutes a current mirror circuit with the output transistor M1.

  The inverting input terminal of the comparator 12 is connected to the drain of the PMOS transistor M3 and the resistor R5, and the comparison voltage Vs is applied to the non-inverting input terminal. The output terminal of the comparator 12 is connected to one terminal of the AND circuit 10.

  Since the output transistor M1 and the PMOS transistor M3 constitute a current mirror circuit, the drain current of the PMOS transistor M3 of the current detection circuit 2 is output from the heavy load constant voltage circuit 4 while the heavy load constant voltage circuit 4 is in operation. It is proportional to the drain current of the transistor M1. Since the drain current of the output transistor M1 is an output current, the drain current of the PMOS transistor M3 is proportional to the output current.

The drain current of the PMOS transistor M3 is supplied to the resistor R5 and converted into a voltage, and the voltage is applied to the inverting input terminal of the comparator 12.
The comparator 12 compares the voltage proportional to the output current input to the inverting input terminal with the comparison voltage Vs. When the voltage proportional to the output current is equal to or lower than the comparison voltage Vs, the output signal becomes high level and the comparison voltage Vs. When the output signal is higher than that, the output signal becomes low level.
The comparison voltage Vs is used as a threshold voltage and is set to the maximum output current value of the light load constant voltage circuit 6.

The operation of the constant voltage power supply circuit of FIG. 2 will be described.
(1) When the control signal ECO is at a low level The output signal of the AND circuit 10 is at a low level regardless of the output signal of the comparator 12 of the current detection circuit 2. Therefore, the high level signal inverted by the inverter circuit 8 is input to the chip enable terminal CE1 of the operational amplifier circuit 11 of the heavy load circuit 4, and the operational amplifier circuit 11 operates. Since the low level signal is input to the chip enable terminal CE2 of the operational amplifier circuit 14 of the light load circuit 6, the operational amplifier circuit 14 is stopped.
As a result, when the control signal ECO is at a low level, the heavy load constant voltage circuit 4 operates and the light load constant voltage circuit 6 stops.

(2) When the control signal ECO changes from low level to high level As described above, when the voltage applied to the inverting input terminal is higher than the comparison voltage Vs, the signal output from the comparator 12 to the AND circuit 10 Becomes low level. That is, in a state where the drain current of the PMOS transistor M3 is larger than the threshold current, the signal input to one terminal of the AND circuit 10 is at a low level, so that the output signal from the AND circuit 10 is at a low level. The heavy load constant voltage circuit 4 is in an activated state, and the light load constant voltage circuit 6 is in a stopped state.

  When the voltage applied to the inverting input terminal of the comparator 12 becomes lower than the comparison voltage Vs, the signal output from the comparator 12 to the AND circuit 10 becomes a high level. As a result, both signals input to both terminals of the AND circuit 10 are at a high level, so that the output signal of the AND circuit 10 is at a high level, the heavy load constant voltage circuit 4 is stopped, and the light load constant voltage is stopped. Circuit 6 is activated.

In the constant voltage power supply circuit of this embodiment, even when the control signal ECO changes from low level to high level, the output current is larger than the maximum output current value of the light load constant voltage circuit 6 that is the threshold voltage. Because the constant voltage circuit 6 for light load does not operate at the same time, it is possible to prevent the output voltage V _out from suddenly decreasing due to switching from the constant voltage circuit 4 for heavy load to the constant voltage circuit 6 for light load. Can do.
On the other hand, in the state where the control signal ECO is at the low level, even if the output current instantaneously drops below the threshold current, the light load constant voltage circuit 6 is not switched. The fluctuation hardly affects the output voltage, and the noise of the output voltage can be reduced.

3 and 4 are diagrams showing another embodiment of the constant voltage power supply circuit, FIG. 3 is a block diagram schematically showing the constant voltage power supply circuit, and FIG. 4 is a circuit diagram showing FIG. 3 in detail.
The constant voltage power supply circuit of this embodiment uses a current limiting circuit 16 instead of the current detection circuit 2 of the constant voltage power supply circuit of FIGS. 1 and 2, and the other configuration is that of FIGS. Therefore, the description of the configuration other than the current limiting circuit 16 is omitted.

The current limiting circuit 16 outputs a current limiting signal IL to the heavy load constant voltage circuit 4 so that the output current of the constant voltage power supply circuit does not exceed the maximum output current of the heavy load constant voltage circuit 4. It is a circuit that restricts. The current limiting circuit 16 has a current detection function similar to that of the current detection circuit 2 shown in FIG.
Generally, a constant voltage circuit is always provided with a current limiting circuit. In this embodiment, a circuit to be newly added can be reduced by using a normally provided current limiting circuit also as a current detection circuit.

The current limiting circuit 16 will be described in detail with reference to FIG.
The current limiting circuit 16 includes a comparator 18, PMOS transistors M4 and M5, NMOS transistors M6 and M7, and a resistor R6.
The source of the PMOS transistor M4 is connected to the power input terminal V _in, the gate is connected to the gate of the output transistor M1 of the heavy load for a constant voltage circuit 4, a current mirror circuit with the PMOS transistor M4 and the output transistor M1 is doing. The drain of the PMOS transistor M4 is connected to the drain of the NMOS transistor M6.

The source of the NMOS transistor M6 is grounded, and the gate is connected to the drain. The gate and drain of the NMOS transistor M6 are connected to the gate of the NMOS transistor M7.
The source of the NMOS transistor M7 is grounded together with the source of the NMOS transistor M6, and the NMOS transistor M7 and the NMOS transistor M6 constitute a current mirror circuit. The drain of the NMOS transistor M6 is connected to the input terminal V _in via a resistor R6.

The source of the PMOS transistor M5 is connected to the power supply input terminal Vin, the gate is connected to the drain of the NMOS transistor M6 and the resistor R6, and the drain is connected to the gate of the output transistor M1 of the heavy load constant voltage circuit 4.
The comparison voltage Vs with reference to the input voltage Vin is applied to the inverting input terminal of the comparator 18, and the non-inverting input terminal is connected to the drain of the NMOS transistor M6 and the resistor R6. The output terminal of the comparator 18 is connected to one input terminal of the AND circuit 10.

  In this constant voltage power supply circuit, since the output transistor M1 and the PMOS transistor M4 of the heavy load constant voltage circuit 4 constitute a current mirror circuit, the drain current of the PMOS transistor M4 is proportional to the output current. The direction of the current of the drain current of the PMOS transistor M4 is inverted by a current mirror circuit composed of NMOS transistors M6 and M7, which is supplied to the resistor R6 and converted into a voltage. The comparator 18 outputs a low level signal when the voltage applied to the non-inverting input terminal is higher than the comparison voltage Vs applied to the inverting input terminal, and the voltage applied to the non-inverting input terminal. When it is lower than the comparison voltage Vs applied to the inverting input terminal, a high level signal is output.

  When the voltage drop of the resistor R6 exceeds the threshold voltage of the PMOS transistor M5, the PMOS transistor M5 is activated, and the drain-side potential of the PMOS transistor M5 rises to suppress the gate voltage drop of the output transistor M1. It becomes. As a result, an increase in the output current flowing through the output transistor M1 is suppressed, and the output current is limited.

  FIG. 5 is a block diagram schematically showing still another embodiment of the constant voltage power supply circuit of the present invention. The constant voltage power supply circuit of this embodiment is obtained by adding a current signal delay circuit 20 to the constant voltage power supply circuit of FIG. 1, and the other structure is the same as that of FIG. The description of the configuration other than is omitted.

  When the output signal of the current detection circuit 2 changes from the low level to the high level, the current signal delay circuit 20 delays the low level signal from the current detection circuit 2 input to the AND circuit 10 for a predetermined time and changes to the high level. Change to level. Conversely, when the output signal of the current detection circuit 2 changes from high level to low level, the high level signal from the current detection circuit 2 input to the AND circuit is changed to low level without delay. As a result, even if the control signal ECO is at a high level, the output signal of the AND circuit 10 changes from a low level to a high level until a predetermined time elapses after the output signal of the current detection circuit 2 becomes a high level. No longer.

An example of the current signal delay circuit 20 will be described with reference to FIG.
The current signal delay circuit 20 includes a resistor R7, a capacitor C1, a diode D1, and a buffer amplifier 22. The buffer amplifier 22 has a hysteresis input terminal.
The cathode of the diode D1 is connected to the output terminal of the comparator 12 of the current detection circuit 2, and the anode is connected to one terminal of the capacitor C1 and the hysteresis input terminal of the buffer amplifier 22. The resistor R7 is connected in parallel with the diode D1. The other terminal of the capacitor C1 is grounded. The output terminal of the buffer amplifier 22 is connected to one input terminal of the AND circuit 10.

When the output signal of the comparator 12 of the current detection circuit 2 changes from the low level to the high level, the output signal is supplied to the capacitor C1 through the resistor R7 to charge the capacitor C1, and then passes through the buffer amplifier 22 and the AND circuit. 10 is input. Therefore, the signal input to the AND circuit 10 does not change to high level for a certain period of time until the capacitor C1 is charged, and the input signal to the AND circuit 10 changes to high level after a delay.
Conversely, when the output signal of the comparator 12 of the current detection circuit 2 changes from the high level to the low level, the capacitor C1 is discharged through the diode D1, so that the voltage of the capacitor C1 decreases in a short time, and almost The input signal to the AND circuit 10 changes to a low level without delay.

  With the above configuration, the constant voltage power supply circuit according to this embodiment has detected that the control signal ECO has changed from the low level to the high level, and the current detection circuit 2 has detected that the output current has decreased below the threshold current. After a certain period of time, the light load constant voltage circuit 6 is switched.

When switching from the heavy load constant voltage circuit 4 to the light load constant voltage circuit 6, the output current value fluctuates particularly when the decrease in the output current output to the output terminal _Vout is moderate. When the output current fluctuates up and down across the threshold, jitter occurs in which the output signal of the comparator 12 of the current detection circuit 2 repeatedly changes between high level and low level. When the output signal of the current detection circuit 2 is input to the AND circuit 10 as it is, switching between the heavy load constant voltage circuit 4 and the light load constant voltage circuit 6 is repeatedly performed due to the occurrence of jitter, and noise is generated in the output voltage. To do.
In the constant voltage power supply circuit of this embodiment, when the output signal from the current detection circuit 2 changes from a low level to a high level, the current signal delay circuit 20 that delays the change for a predetermined time and inputs it to the AND circuit 10 is provided. Since it is provided, the influence of jitter can be reduced. Then, by setting the delay time of the current signal delay circuit 20 to a time when the output signal of the current detection circuit 2 is stabilized, the switching from the heavy load constant voltage circuit 4 to the light load constant voltage circuit 6 can be reduced. It can be performed stably without being affected.

  In this embodiment, a CR charge / discharge circuit comprising a capacitor C1 and a resistor R7 is used as the current signal delay circuit 20, but the present invention is not limited to this, and for example, a clock signal is divided by a counter. A known delay circuit such as a circuit using a constant current circuit and a capacitor can be used.

  FIG. 7 is a block diagram showing still another embodiment of the constant voltage power supply circuit of the present invention. The constant voltage power supply circuit of this embodiment is obtained by adding a control signal delay circuit 24 to the constant voltage power supply circuit of FIG. 1, and the other structure is the same as that of FIG. The description of the configuration other than is omitted.

When the control signal ECO changes from the low level to the high level, the control signal delay circuit 24 delays the low level signal input to the AND circuit 10 for a predetermined time and changes it to the high level. Conversely, when the control signal ECO changes from high level to low level, the high level signal input to the AND circuit 10 is changed to low level without delay.
In this way, if the signal input to the AND circuit 10 is changed to the high level with a certain time margin after the control signal ECO changes from the low level to the high level, the current detection of the current detection circuit 2 is detected. Even when the accuracy is low, switching to the light load constant voltage circuit 6 can be performed after the output current is sufficiently reduced.

An example of the control signal delay circuit 24 will be described with reference to FIG.
The control signal delay circuit 24 has the same configuration as the current signal delay circuit 20 of FIG. That is, the control signal delay circuit 24 includes a resistor R8, a diode D2, a capacitor C2, and a buffer amplifier 26. The buffer amplifier 26 has a hysteresis input terminal.

  The cathode of the diode D2 is connected to the output terminal of a control circuit (not shown) that outputs the control signal ECO, and the anode is connected to one end of the capacitor C2 and the hysteresis input terminal of the buffer amplifier 26. The resistor R8 is connected in parallel with the diode D2. The other end of the capacitor C2 is grounded. The output terminal of the buffer amplifier 26 is connected to the AND circuit 10.

When the control signal ECO changes from the low level to the high level, the control signal is supplied to the capacitor C2 through the resistor R8 to charge the capacitor C2, and then input to the AND circuit 10 through the buffer amplifier 26. Accordingly, the signal input to the AND circuit 10 does not change to a high level for a certain period of time until the capacitor C2 is charged, and the signal input to the AND circuit 10 changes to a high level after being delayed for a predetermined time.
On the contrary, when the control signal ECO changes from the high level to the low level, the capacitor C2 is discharged through the diode D2, so that the voltage of the capacitor C2 decreases in a short time and the signal input to the AND circuit 10 Changes to low level with little delay.

  The current signal delay circuit 20 shown in FIGS. 5 and 6 and the control signal delay circuit 24 shown in FIGS. 7 and 8 are provided in the same constant voltage power supply circuit as shown in FIGS. 9 and 10, for example. Also good. FIG. 9 is a block diagram showing an embodiment in which the current signal delay circuit 20 and the control signal delay circuit 24 are provided in the constant voltage power supply circuit of FIG. 1, and FIG. 10 is a circuit diagram showing a configuration example of FIG.

  As shown in FIGS. 9 and 10, the current signal delay circuit 20 delays the change of the output signal of the current detection circuit 2 from the low level to the high level, and the control signal ECO changes from the low level to the high level. By providing both the control signal delay circuit 24 for delaying the change, both of the low level signals input to the AND circuit 10 at the time of switching from the heavy load constant voltage circuit 4 to the light load constant voltage circuit 6 can be obtained. Since both of them are delayed and change to high level, the light load constant voltage immediately after detecting that the output current is lower than the threshold current by the current detection signal 2 and immediately after the control signal ECO changes to high level. The circuit 6 will not operate. Thereby, switching from the heavy load constant voltage circuit 4 to the light load constant voltage circuit 6 can be performed more safely.

5 to 10, the constant voltage power supply circuit including the current detection circuit 2 is provided with the current signal delay circuit 20 or the control signal delay circuit 24. However, as shown in FIGS. The same effect can be obtained even if the current signal delay circuit 20 or the control signal delay circuit 24 is provided in a constant voltage power supply circuit including the current limiting circuit 16 instead of the current detection circuit 2.
An embodiment in which the current signal delay circuit 20 is provided in the constant voltage power supply circuit having the current limiting circuit 16 in FIGS. 3 and 4 is shown in FIGS. 11 and 12, and the embodiment in which the control signal delay circuit 24 is provided is shown. 13 and 14, an embodiment in which both the current signal delay circuit 20 and the control signal delay circuit 24 are provided is shown in FIGS. 15 and 16.

An example of the configuration of the constant voltage power supply circuit provided with the current signal delay circuit 20 for delaying the output signal of the current limiting circuit 16 will be described with reference to FIG.
The cathode of the diode D1 of the current signal delay circuit 20 is connected to the output terminal of the comparator 18 of the current limiting circuit 16, and the anode is connected to the hysteresis input terminal of the buffer amplifier 22 and one end of the capacitor C1. The resistor R7 is connected in parallel with the diode D1. The other end of the capacitor C1 is grounded. The output terminal of the buffer amplifier 22 is connected to the AND circuit 10.

With the above configuration, when the output signal of the comparator 18 of the current limiting circuit 16 changes from the low level to the high level, the output signal is supplied to the capacitor C1 through the resistor R7 to charge the capacitor C1, and then the buffer amplifier. 22 and input to the AND circuit 10. Therefore, the signal input to the AND circuit 10 does not change to a high level for a certain period of time until the capacitor C1 is charged, but changes to a high level with a delay of a certain time.
Conversely, when the output signal of the comparator 18 of the current limiting circuit 16 changes from the high level to the low level, the capacitor C1 is discharged through the diode D1, so that the voltage of the capacitor C1 drops in a short time, and almost The signal input to the AND circuit 10 without a delay changes from the high level to the low level.

An embodiment in which the control signal delay circuit 24 for delaying the control signal ECO is provided in the constant voltage power supply circuit including the current limiting circuit 16 will be described with reference to FIG.
The cathode of the diode D2 of the control signal delay circuit 24 is connected to the output terminal of a control circuit (not shown) that outputs the control signal ECO, and the anode is connected to one end of the capacitor C2 and the hysteresis input terminal of the buffer amplifier 26. . The resistor R8 is connected in parallel with the diode D2. The other end of the capacitor C2 is grounded. The output terminal of the buffer amplifier 26 is connected to the AND circuit 10.

When the control signal ECO changes from the low level to the high level, the control signal is supplied to the capacitor C2 through the resistor R8 to charge the capacitor C2, and then input to the AND circuit 10 through the buffer amplifier 26. Accordingly, the signal input to the AND circuit 10 does not change to a high level for a certain period of time until the capacitor C2 is charged, and the signal input to the AND circuit 10 changes to a high level after being delayed for a predetermined time.
On the contrary, when the control signal ECO changes from the high level to the low level, the capacitor C2 is discharged through the diode D2, so that the voltage of the capacitor C2 decreases in a short time and the signal input to the AND circuit 10 Changes to low level with little delay.

  FIGS. 15 and 16 show an embodiment in which a current signal delay circuit 20 and a control signal delay circuit 24 are provided in a constant voltage power supply circuit provided with a current limiting circuit 16, and the circuit configurations thereof are shown in FIGS. The explanation is omitted because it is the same.

  FIGS. 17 and 18 are diagrams showing an embodiment in which a control signal delay circuit 24 is provided in a constant voltage power supply circuit that does not include a current detection circuit or a current limiting circuit, and FIG. 17 schematically shows the configuration of the embodiment. FIG. 18 is a circuit diagram showing an example of the circuit configuration in detail.

  In the constant voltage power supply circuit of this embodiment, the control signal ECO is input to the heavy load constant voltage circuit 4 and the light load constant voltage circuit 6 via the control signal delay circuit 24. When the control signal ECO is at a high level, a high level signal is input to the light load constant voltage circuit 6 to operate the light load constant voltage circuit 6, and an inverter circuit 8 is connected to the heavy load constant voltage circuit 4. A low-level signal is input through the heavy load constant voltage circuit 4 to stop. Conversely, when the control signal ECO is at a low level, a low level signal is input to the light load constant voltage circuit 6 to stop the light load constant voltage circuit 6, and the heavy load constant voltage circuit 4 includes an inverter. When a high level signal is input via the circuit 8, the heavy load constant voltage circuit 4 operates.

  When the control signal ECO changes from the low level to the high level, the control signal delay circuit 24 delays the change and inputs it to the constant voltage circuits 4 and 6, and the control signal ECO changes from the high level to the low level. In this case, the change is input to both constant voltage circuits 4 and 6 without delay. Therefore, the constant voltage power supply circuit is switched from the heavy load constant voltage circuit 4 to the light load constant voltage circuit 6 after a lapse of a fixed time after the control signal ECO changes from the low level to the high level.

  If a high level signal is output from the control signal ECO at the same time as the transition from the high-speed operation state to the standby state, it takes some time for the output current from the power supply circuit to fall to the standby state current. Therefore, the delay time of the control signal delay circuit 24 is set to a time required until the output current decreases to the standby state current after the control signal ECO is switched from the low level to the high level, or a time slightly longer than that. Is preferred. Then, the control signal delay circuit 24 can delay the change of the control signal ECO from the low level to the high level until the output current is reduced to the standby state current, and the output current from the power supply circuit is reduced. In the meantime, the switching to the light load constant voltage circuit 6 can be prevented, the output voltage can be prevented from abruptly decreasing, and the occurrence of output voltage switching noise can also be prevented.

In the embodiment of the present specification, the constant voltage circuit 4 for heavy load and the constant voltage circuit 6 for light load are shown using series regulators. The constant voltage circuit may be composed of a switching regulator.
In the detailed configuration example of the heavy load constant voltage circuit 4 and the light load constant voltage circuit 6, separate output transistors M1 and M2 are provided in the constant voltage circuits 4 and 6, respectively. However, the present invention is not limited to this, and a common output transistor may be used for the heavy load constant voltage circuit 4 and the light load constant voltage circuit 6, and the output transistors may be controlled by the operational amplifier circuits 11 and 14. .

It is a block diagram which shows roughly one Example of a constant voltage power supply circuit. FIG. 2 is a circuit diagram illustrating in detail the constant voltage power supply circuit of FIG. 1. It is a block diagram which shows schematically the further another Example of a constant voltage power supply circuit. FIG. 4 is a circuit diagram showing in detail the constant voltage power supply circuit of FIG. 3. It is a block diagram which shows schematically the further another Example of a constant voltage power supply circuit. It is a circuit diagram which shows the constant voltage power supply circuit of FIG. 5 in detail. It is a block diagram which shows schematically the further another Example of a constant voltage power supply circuit. It is a circuit diagram which shows the constant voltage power supply circuit of FIG. 7 in detail. It is a block diagram which shows schematically the further another Example of a constant voltage power supply circuit. FIG. 10 is a circuit diagram illustrating the constant voltage power supply circuit of FIG. 9 in detail. It is a block diagram which shows schematically the further another Example of a constant voltage power supply circuit. It is a circuit diagram which shows the constant voltage power supply circuit of FIG. 11 in detail. It is a block diagram which shows schematically the further another Example of a constant voltage power supply circuit. It is a circuit diagram which shows the constant voltage power supply circuit of FIG. 13 in detail. It is a block diagram which shows schematically the further another Example of a constant voltage power supply circuit. It is a circuit diagram which shows the constant voltage power supply circuit of FIG. 15 in detail. It is a block diagram which shows schematically the further another Example of a constant voltage power supply circuit. It is a circuit diagram which shows the constant voltage power supply circuit of FIG. 17 in detail.

Explanation of symbols

2 Current detection circuit 4 Heavy load constant voltage circuit 6 Light load constant voltage circuit 8 Inverter circuit 10 AND circuit 11, 14 Operation amplification circuit 12, 18 Comparator 16 Current limit circuit 20 Current signal delay circuit 22, 26 Buffer amplifier 24 Control Signal delay circuit C1, C2 Capacitor D1, D2 Diode M1-M7 Transistor R1-R8 Resistance

Claims (3)

Operates either the constant voltage circuit for heavy loads, the constant voltage circuit for light loads whose maximum output current is smaller than that of the constant voltage circuit for heavy loads, or the constant voltage circuit for heavy loads or the constant voltage circuit for light loads A switching unit that operates one of the heavy load constant voltage circuit and the light load constant voltage circuit when a control signal to be operated is input, and outputs a constant voltage by an output from one of the operated constant voltage circuits In a constant voltage power supply circuit comprising an output unit,
In order to detect the output current from the output unit, a current that includes a comparison circuit that compares the detected output current with a preset threshold current and outputs a signal according to the comparison result in the comparison circuit With a detection circuit,
In addition to the control signal, the switching unit also receives an output signal of the current detection circuit, and the control signal is in a state where the constant voltage circuit for light load should be operated, and the output current from the current detection circuit The light load constant voltage circuit is operated only when an output signal indicating that is less than the threshold current is input ,
When a change in the output signal from the current detection circuit when the output current becomes equal to or less than a threshold current is delayed by a predetermined time and input to the switching unit, and the output current exceeds the threshold current Current signal delay circuit to be input to the switching unit without delaying the change in the output signal from the current detection circuit,
When the control signal changes from a state in which the heavy load constant voltage circuit is to be operated to a state in which the light load constant voltage circuit is to be operated, the change of the control signal is delayed for a certain time to the switching unit. When the control signal is changed from a state in which the light load constant voltage circuit is to be operated to a state in which the heavy load constant voltage circuit is to be operated, the control signal is sent to the switching unit without delaying the control signal. A constant voltage power supply circuit , further comprising a control signal delay circuit to be input .   2. The constant voltage according to claim 1, wherein the threshold current is a maximum output current value of the light load constant voltage circuit or a current value smaller than the maximum output current value of the light load constant voltage circuit. Power supply circuit. 3. The constant voltage power supply circuit according to claim 1, wherein the current detection circuit includes a current limiting circuit for limiting an output current from the output unit within a predetermined current value.

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