KR101510862B1 - Single-channel asynchronous bridge system for interconnecting blocks of different domains in System-on-Chip - Google Patents

Abstract

The present invention relates to a single channel asynchronous bridge system for interconnecting blocks of different domains in system on chip (SoC) which has multiple domains. In detail, the present invention relates to a single channel asynchronous bridge system which links the blocks to a single payload channel in the asynchronous bridge regardless of FIFO depth to make block connection simple and to reduce chip size and time for making chip design; improves full system performance through FIFO depth setting by the bus performance transmitting payload data between blocks; minimizes the data time limitation by transmitting transmitter domain clerk to a receiver to make the design easy; and prevents multibit CDC problems by using a single bit control signal between a transmitter and the receiver.

Description

[0001] The present invention relates to a single-channel asynchronous bridge system for interconnecting blocks of different domains in a system-on-a-chip,

The present invention relates generally to a single-channel asynchronous bridge technique for efficiently connecting blocks belonging to different domains in a system-on-a-chip (SoC) having a plurality of domains.

More particularly, the present invention simplifies the block connection by connecting blocks with a single payload channel regardless of the FIFO depth in the asynchronous bridge, thereby reducing the chip size and the time required for chip design, It is possible to set the FIFO depth according to the performance of the bus for transmitting the data, thereby improving the overall system performance and transmitting the clock of the transmitter domain to the receiver, thereby minimizing the timing restriction of the payload data, Channel asynchronous bridge technology capable of preventing multi-bit CDC problems by using a single-bit control signal between the receivers.

In recent years, as the chip size of a system-on-chip (SoC) increases and various functions are accepted, functional blocks are divided into different clock, power, and voltage domains within one chip. Because the clock, power, and voltage conditions are different among the blocks existing in different domains within the chip, they are commonly connected through an asynchronous bridge.

As the number of blocks in an entire chip increases, the asynchronous bridge connection between blocks affects chip size and design time. SoC design process independently performs RTL design work, STA (Static Timing Analysis) work, and layout design work for each block. As the number of blocks of whole chip increases, chip size and design time influence . As the number of connections between blocks increases, the number of verification items increases in the RTL design, and the timing constraints between the blocks and the check points to be examined are increased in the STA, which increases the design time. Also, routing between blocks in the layout design becomes complicated, resulting in an increase in the total chip size.

Also, in the conventional asynchronous bridge, an internal FIFO is generally used as a memory for storing the data of the bus in the middle. The depth of the internal FIFO affects overall system performance.

1 shows a multi-channel asynchronous bridge system used for block connection of different domains in the prior art. The asynchronous bridge is composed of a transmitter 110 and a receiver 120, and a FIFO 112 is located in the transmitter 110. At this time, the depth of the FIFO 112 shown in FIG.

The transmitter 110 includes a transmission controller 111, a FIFO 112, and a transmission synchronizer 113. Transmitter 110 is provided with payload data (payload_src) from a source using a valid-ready handshaking protocol. The payload data is stored in the FIFO 112 of the transmitter 110 and transmitted to the receiver 120 through the same four payload channels (payload_ch0 to payload_ch3) as the FIFO depth.

The receiver 120 includes a receiving controller 121, a multiplexer 122, and a receiving synchronizer 123. The receiver 120 receives the payload data on a plurality of payload channels and selects one payload data through the multiplexer 122. And provides the payload data (payload_dst) to the destination using a validated-handy handshaking protocol.

The transmitter 110 stores the payload data in the FIFO 112 and transmits the write pointer (write_pointer) of the FIFO 112 to the receiver 120 if the FIFO 112 is not FULL. The receiver 120 transfers payload data (payload_dst) to the destination and sends a read pointer (read_pointer) to the transmitter 110 when the FIFO 112 is not EMPTY. The transmitter 110 and the receiver 120 compare the write pointer and the read pointer to determine FULL and EMPTY, respectively.

Since the transmitter 110 and the receiver 120 have different clock domains, the write pointer and the read pointer are stored via the synchronizers 113 and 123. Generally, the transmit controller 111 and the receive controller 121 transmit the gray code Pointer (Gray code pointer) built in to mitigate the effect of multi-bit CDC (Multiple-bit Clock Domain Crossing).

In such a conventional multi-channel asynchronous bridge system, the number of connection channels between blocks is affected by the depth of the FIFO 112 provided in the transmitter 110, that is, the FIFO depth. As the FIFO depth of the asynchronous bridge increases, the payload channel increases and the connection channel between the blocks increases. While there is an advantage that the performance improves as the connection channel increases, there are various disadvantages in the chip design.

That is, as the routing of the entire chip becomes complicated, not only the chip size increases but also the time required for RTL design, STA operation, and layout design is increased. In addition, due to the connection restriction between the blocks, the depth of the FIFO 112 may not be set sufficiently to satisfy the bus performance, which results in a problem that the performance of the entire system can not be sufficiently increased.

In addition, the payload data transmitted at the transmitter 110 passes through the receiver 120 before reaching the destination, where the latency of the payload data is limited by the clock frequency of the receiver domain. This timing limitation becomes more difficult as the clock frequency of the receiver domain becomes faster and the physical distance between the transmitter 110 and the receiver 120 becomes longer. In addition, write and read pointers mitigate multi-bit CDC problems using gray code pointers, but multi-bit CDC problems can be serious if the distance between blocks is large. Accordingly, in the prior art, there is a further need for a timing limit to uniformly adjust the skew between the pointer bits, so that the chip designing process becomes very cumbersome.

Therefore, a system-on-chip block connection technology capable of solving various problems as described above is urgently required in the related industry.

1. Korean patent application No. 10-2012-0003660 entitled "System-on-a-chip, microcontroller, electronic device including the same, and communication method of system-

2. Korean Patent Application No. 10-2007-0121656 entitled "SoC System for Multimedia System"

3. Korean Patent Application No. 10-2009-0117760 entitled "Asynchronous Integrated Upsizing Circuit in Data Processing System"

4. Korean Patent Application No. 10-2006-7001734 entitled "Microprocessor Subsystem"

5. Korean Patent Application No. 10-2004-7016993 entitled " Systolic Array-Type Structure Implementation Processing Apparatus and Processing Method "

An object of the present invention is to provide a single-channel asynchronous bridge technique for efficiently connecting blocks belonging to different domains in a system-on-a-chip (SoC) having a plurality of domains in general.

In particular, it is an object of the present invention to simplify the block connection by connecting blocks with a single payload channel regardless of the FIFO depth in the asynchronous bridge, thereby reducing chip size and time required for chip design, It is possible to set the FIFO depth according to the performance of the bus for transmitting the data, thereby improving the overall system performance and transmitting the clock of the transmitter domain to the receiver, thereby minimizing the timing restriction of the payload data, Channel asynchronous bridge technique that can prevent multi-bit CDC problems by using a single-bit control signal between the receivers.

In order to achieve the above object, the present invention is a single-channel asynchronous bridge system having a transmitter and a receiver for connecting a plurality of blocks belonging to different domains in a system-on-chip. At this time, the transmitter 210 includes a register slice 212 for temporarily storing the payload data and the source valid signal provided from the source, separating the timing, and transmitting the payload data to the receiver through a single payload channel; A first counter 213 receiving a strobe signal from a receiver and generating a first pointer that follows a read pointer of a FIFO built in a receiver; A strobe synchronizer 214 receiving a first pointer and resetting the first pointer to a clock domain of the transmitter; And generates a transmission valid signal so as to correspond to the source valid signal and provides the transmission valid signal to the receiver so as to determine whether the FIFO built in the receiver is FULL by comparing the count value by the transmission valid signal and the count value by the first pointer, And a FIFO transmission controller 211 for controlling whether or not the register slice is to transmit payload data to the receiver according to the determination result of FULL. The receiver 220 also includes a FIFO 222 for receiving and storing payload data from a transmitter over a single payload channel; A third counter 223 for generating a write pointer to correspond to the transmit valid signal and providing the write pointer as a write address of the FIFO; A valid synchronizer 224 that receives a write pointer and resets it to the clock domain of the receiver; A read pointer is generated so as to correspond to the destination valid signal and the destination read signal and is provided as the read address of the FIFO. The count value by the transfer valid signal and the count value by the destination valid signal and the destination read signal are And a FIFO reception controller 221 for determining whether or not the FIFO is EMPTY, generating a strobe signal corresponding to the determination result of the EMPTY and a destination ready signal, and transmitting the generated strobe signal to the transmitter.

In the present invention, the FIFO transmission controller 211 includes: a first AND gate 215 for performing a logical product of the source valid signal and the result of the FULL determination to generate a transmission valid signal; A second counter (217) for generating a second pointer following the first pointer generated by the first counter; A first comparator (218) generating a pop signal that remains valid while the values of the first pointer and the second pointer are different; A built-in counter counting up by a source valid signal and counting down by a pop signal to determine whether or not the FIFO built in the receiver is full based on the value of the built-in counter, And a FIFO pool generator 216 for providing transmission to the ready port of the slice 212 and performing transmission control on the payload data.

In the present invention, the FIFO reception controller 221 includes: a second AND gate 227 for performing a logical product operation of a destination valid signal and a destination ready signal to generate a first enable signal; A fourth counter 225 for generating a read pointer corresponding to a period in which the first enable signal is HIGH and providing the read pointer as a read address of the FIFO; A second comparator (229) for generating a destination valid signal that remains valid while the values of the write pointer and the read pointer are different; A third AND gate 228 for performing a logical multiplication of the destination valid signal and the destination ready signal to generate a second enable signal; And a clock gate 226 for generating a strobe signal corresponding to a period in which the first enable signal is HIGH and transmitting the generated strobe signal to a transmitter.

At this time, the transmitter 210 transmits the clock signal of the transmitter domain to the receiver 220, the receiver 220 receives the clock signal of the transmitter domain, inverts the counted clock of the third counter and the operation clock of the FIFO, The transmission valid signal and the strobe signal exchanged between the transmitter 210 and the receiver 220 are preferably composed of a single bit. It is preferable that the first to fourth counters 213, 217, 223 and 225 are gray code counters and the FIFO 222 is a depth configuration type FIFO. In addition, a plurality of transmitters 210 and a plurality of receivers 220 included in a plurality of blocks belonging to different domains consist of a reset of synchronized logic by interlocking a reset signal.

According to the present invention, a system-on-chip (SoC) having a plurality of domains has an advantage that blocks belonging to different domains can be efficiently connected using an asynchronous bridge of a single channel scheme.

In particular, according to the present invention, a block connection is simplified by connecting a block with a single payload channel regardless of the FIFO depth in an asynchronous bridge, thereby reducing chip size and time required for chip design.

In addition, according to the present invention, the FIFO depth can be set according to the performance of a bus for transmitting payload data between blocks, thereby improving the performance of the entire system-on-a-chip.

Also, according to the present invention, it is possible to minimize the timing limitation of the payload data by transmitting the clock of the transmitter domain to the receiver, thereby facilitating design, and by using a single-bit control signal between the transmitter and the receiver, There is an advantage to be able to do.

1 shows an asynchronous multi-channel bridge system used for block connection of different domains in the prior art, Fig.
2 shows a single channel asynchronous bridge system for block connection of different domains according to the present invention, Fig.
3 shows an internal structure of a transmitter according to the present invention,
4 shows an internal structure of a receiver according to the present invention,
5 is a diagram illustrating a data connection between blocks using the AXI protocol according to the present invention;
FIG. 6 is a diagram illustrating a clock and reset connection between blocks using the AXI protocol according to the present invention. FIG.

The present invention provides a single channel asynchronous bridge technique for efficiently connecting blocks belonging to different domains in an SoC. The asynchronous bridge according to the present invention simplifies the connection between the blocks as a whole by connecting the blocks with a single channel (i.e., one payload channel) regardless of the FIFO depth. This reduces the total chip size because the RTL design reduces the connection and verification time between blocks, reduces the timing constraints between blocks in the STA process, reduces overall chip design time, and simplifies routing between blocks in the layout design.

Also, the present invention can increase the FIFO depth according to the bus performance without being limited by the connection between the blocks, thereby improving the overall system performance as compared with the prior art. In general, in an asynchronous bridge, the internal FIFO stores the bus data in the middle, and the FIFO depth affects overall system performance. Conventionally, since the number of payload channels is the same as that of the FIFO depth, if the FIFO depth is increased, the number of payload channels is increased and the connection between the blocks is complicated, thereby causing various problems. This causes the FIFO depth to be insufficient for the bus performance in the prior art. Since the asynchronous bridge of the present invention connects the blocks using a single payload channel irrespective of the FIFO depth, the FIFO depth sufficient for the bus performance can be ensured, thereby improving the overall system performance.

Also, in the present invention, the problem of timing limitation due to the latency of the payload data is alleviated by transmitting the clock of the transmitter domain to the receiver. If the two different domains are in one block, the transmitter and the receiver are placed in one block, so the payload data and the latency of the control signals between the transmitter and the receiver are negligibly small. However, if the two different domains are divided into two blocks, the transmitter and the receiver are placed in different blocks, and the latency of the payload data and control signals between the transmitter and the receiver becomes large.

The payload data transmitted at the transmitter must arrive at the receiver before being used in the destination, and timing constraints related to the clock frequency of the receiver domain must be considered in the system design. That is, the latency of the payload data transmitted from the transmitter to the receiver is limited by the clock frequency of the receiver domain. This timing constraint becomes more difficult to satisfy as the clock frequency of the receiver domain becomes faster and the physical distance between blocks becomes longer.

In the present invention, a clock of a transmitter domain is transmitted to a receiver to synchronize payload data with a clock of a transmitter domain. The clock and payload data satisfy the setup time by keeping the latency the same and the receiver satisfies the hold time by using the inversion clock for the clock of the transmitter domain. With this configuration, there is an advantage that the latency of the payload data transmitted from the transmitter to the receiver is free from the timing limitation problem due to the clock frequency of the receiver domain.

Also, in the present invention, the transmitter and the receiver are configured to transmit and receive a single-bit valid signal and a strobe signal so that a multi-bit CDC problem does not occur. In the prior art, the FULL and EMPTY states of the FIFO are determined by transmitting and receiving gray code pointers between the transmitter and the receiver. If the two different domains are in one block, the multi-bit CDC is not a problem since the latency of the gray code pointer is negligibly small. However, if the two different domains are divided into two blocks, the latency of the Gray code pointer becomes large due to the distance between the blocks, which may cause a multi-bit CDC problem. In the present invention, instead of transmitting a multi-bit Gray code pointer as in the prior art, the transmitter and the receiver exchange a single-bit valid signal and a strobe signal so as to avoid a multi-bit CDC problem.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

2 is a diagram illustrating a single channel asynchronous bridge system for block connection of different domains in the present invention. The asynchronous bridge according to the present invention comprises a transmitter 210 and a receiver 220, which are different from the prior art in that the FIFO module is located in the receiver 220.

First, the transmitter 210 receives payload data (payload_src) from a source using a valid-handy handshaking protocol and stores the data in a register slice 212. The register slice 212 temporarily stores the payload data to separate the timing. In the present invention, the stored payload data is transmitted to the receiver 220 via a single payload channel (tx_payload). For reference, register slice technology is used to register AXI interconnects in the Advanced Extensible Interface (AXI) protocol and isolate timing.

Meanwhile, although the number of payload channels is set to a plurality according to the FIFO depth in the prior art shown in FIG. 1, in the present invention, the payload channel is a single channel regardless of the FIFO depth. Therefore, in the present invention, the block connection is not complicated even if the FIFO depth is increased as much as necessary in consideration of the bus performance.

The receiver 220 receives the payload data from the transmitter 210, stores the payload data in the FIFO 222, and transmits the payload data to the destination using payload-ready handshaking protocol (payload_dst).

The transmitter 210 checks the FIFO 222 in the receiver 220 and transfers the payload data stored in the register slice 212 to the FIFO 222 of the receiver 220 when the FULL is not FULL. At this time, the transmitter 210 indicates that the payload data is valid through the valid signal tx_valid.

The receiver 220 transmits the payload data to the destination when the FIFO 222 is not EMPTY and sends the strobe signal rx_strobe to the transmitter 210 to inform that the transmission of the payload data is completed.

The first Gray code counter 213 of the transmitter 210 generates a read pointer ReadPtr through the strobe signal rx_strobe and the third Gray code counter 223 of the receiver 220 generates a read pointer And generates a write pointer (WritePtr) through a signal (tx_valid). The transmitter 210 and the receiver 220 determine FULL or EMPTY for the FIFO 222 in the receiver 220 using the generated read pointer and write pointer (ReadPtr, WritePtr).

The FIFO 222 and the third Gray code counter 223 of the receiver 220 are synchronized to the clock tx_clk transmitted from the transmitter 210. [ Since the clock tx_clk, the payload data tx_payload and the valid signal tx_valid transmitted from the transmitter 210 to the receiver 220 are physically similar in length to the signal lines, the latency is maintained at substantially the same level, Therefore, the setup time is satisfied despite the latency of the payload data generated in the transmission path. The FIFO 222 and the third Gray code counter 223 of the receiver 220 synchronize with the clock (i.e., the inverted clock) inverted from the clock transmitted from the transmitter 210 to satisfy the hold time.

On the other hand, in the embodiment shown in the present specification, a gray code counter is used as the counting means. The gray code counter is a kind of counter, and codes are allocated so that there is no case where only one bit changes in counting up-down, thereby preventing a static hazard (that is, temporary noise of a spike field) at the time of decoding. It is preferable to apply the gray code counter in consideration of the stability of the system, but the scope of the right of the present invention is not limited thereto.

3 is a diagram illustrating an internal structure of a transmitter 210 for use in a single channel asynchronous bridge system according to the present invention. 3, a transmitter 210 according to the present invention includes a register slice 212, a FIFO full generator 216, first and second gray code counters 213 and 217, a strobe synchronizer (214).

First, the register slice 212 temporarily stores the payload data (payload_src) and the valid signal (valid_src) provided from the source to separate the timing.

The FIFO pull generator 216 uses a push signal and a pop signal to determine whether the FIFO 222 of the receiver 220 is FULL. The push signal becomes HIGH and the internal counter 216a increases when the valid signal tx_valid transmitted to the receiver 220 is valid to HIGH. The strobe signal rx_strobe provided from the receiver 220 increases the value of the first Gray code counter 213. [ The comparator 218 compares the values of the first and second gray code counters 213 and 217 and sets the pop signal to HIGH in different cases. The internal counter 216a of the FIFO pull generator 216 decreases as the pop signal is set to HIGH.

The FIFO pull generator 216 sets the Full signal output to HIGH if the FIFO 222 of the receiver 220 is FULL and the inverted LOW signal is input to the ReadyDst port of the register slice 212, Lt; / RTI > The inverted LOW signal is also input to the AND gate 215 and the valid signal tx_valid transmitted to the receiver 220 is set to LOW so that the fact that the transmission of the payload data has been stopped is terminated at the receiver 220).

Conceptually, the FIFO pull generator 216 compares the counted number of the strobe signal rx_strobe received from the receiver 220 with the valid signal tx_valid transmitted to the receiver 220, 222) is FULL. The internal counter 216a counts up while the transmitter 210 transmits the payload data to the receiver 220 and the receiver 220 delivers the payload data to the destination so that the read pointer of the FIFO 222 is changed The internal counter 216a counts down. This allows the internal counter 216a to monitor how much data remains in the FIFO 222 to determine whether the FIFO 222 is in the FULL state.

The first and second gray code counters 213 and 217 follow the read pointer of the FIFO 222 existing in the receiver 220. The first Gray code counter 213 generates a signal (ReadPtr) that follows the read pointer of the receiver 220 corresponding to the strobe signal rx_strobe transmitted from the receiver 220. [ While the value of the second gray code counter 217 is different from the first gray code counter 213, the second gray code counter 217 counts up by the operating clock since the result of the comparator 218 is HIGH, Up continues until the values of the first and second gray code counters 213 and 217 become equal.

Thus, the first Gray code counter 213 generates a signal (ReadPtr) that follows the read pointer of the FIFO 222, and the second Gray code counter 217 generates a signal from the FIFO 222 to the destination If the read pointer changes as it is provided, it stores the past value to see how much it has changed. The more the read pointer is changed in the FIFO 222 of the receiver 220, the longer the comparator 218 outputs HIGH.

The read pointer (ReadPtr), which is the output of the first gray code counter 213, passes through the strobe synchronizer 214 because the clock domain of the first gray code counter 213 differs from that of the second gray code counter 217. Since the strobe signal rx_strobe is generated according to the clock domain of the receiver 220 side, the read pointer (ReadPtr) in the first gray code counter 213 is also primarily dependent on the clock domain of the receiver 220 side. Since the flip-flop operates according to the clock domain of the transmitter 210 side, the strobe synchronizer 214 is reset to the clock domain of the transmitter 210 when the read pointer ReadPtr passes through the strobe synchronizer 214. Thus, the strobe synchronizer 214 functions to reset the clock domain of the strobe signal to match the operation clock of the transmitter 210.

Also, in order to alleviate the timing limitation problem due to the latency of the payload data as described above, the clock of the transmitter domain, that is, the operating clock of the transmitter 210 is provided to the receiver 220 side (tx_clk).

4 is a diagram illustrating an internal structure of a receiver 220 for use in a single channel asynchronous bridge system according to the present invention. 4, a receiver 220 according to the present invention includes a FIFO 222, third and fourth Gray code counters 223 and 225, a balanced synchronizer 224, and a clock gate 226 .

First, the FIFO 222 can be made up of a configurable-depth FIFO (FIFO) capable of configuring the length of the FIFO array by the programmable processor, that is, the FIFO depth. The FIFO 222 primarily stores the payload data (tx_payload) received from the transmitter 210.

The third and fourth Gray code counters 223 and 225 generate a write address and a read address of the FIFO 222 and determine whether the FIFO 222 is EMPTY. The third Gray code counter 223 is counted up by the transmission clock tx_clk transmitted from the transmitter 210 when the valid signal tx_valid transmitted from the transmitter 210 is HIGH. The third gray code counter 223 generates a write pointer WritePtr of the FIFO 222 since the payload data is input to the FIFO 222 in accordance with the transmission clock tx_clk when the valid signal tx_valid is HIGH will be. The fourth gray code counter 225 counts up when the valid signal (valid_dst) to the destination and the ready signal (ready_dst) are HIGH. Under this condition, the fourth gray code counter 225 generates the read pointer (ReadPtr) of the FIFO 222 because the payload data is provided from the FIFO 222 to the destination.

At this time, the comparator 229 compares the two values of the third and fourth Gray code counters 223 and 225, that is, the read pointer (ReadPtr) of the FIFO 222 with the write pointer (WritePtr). If the read pointer (ReadPtr) and the write pointer (WritePtr) are the same, this means that the FIFO 222 is in the EMPTY state. Therefore, when the pointers (ReadPtr, WritePtr) are different, that is, when the FIFO 222 is not in the EMPTY state and contains payload data, the valid signal to the destination (valid_dst) is set to HIGH, Remind me to the destination.

When the valid signal valid_dst transmitted to the destination is HIGH and the ready signal ready_dst received from the destination is HIGH, it means that the payload data is transferred from the FIFO 222 to the destination. In this case, the clock gate 226 sends a strobe signal rx_strobe to the transmitter 210 to signal that the payload data is sent to the destination.

Since the clock domain of the third gray code counter 223 differs from that of the fourth gray code counter 225, the write pointer WritePtr, which is the output of the third gray code counter 223, is connected to the balanced synchronizer 224 The clock domain is reset. Since the valid signal tx_valid is generated according to the clock domain of the transmitter 210, the write pointer (WritePtr) in the third gray code counter 223 is also primarily dependent on the clock domain of the transmitter 210 side. The validated synchronizer 224 is reset to the clock domain of the receiver 220 side when the write pointer WritePtr passes through the balanced synchronizer 224 because the flip-flop operates according to the clock domain of the receiver 220 side . In this way, the validated synchronizer 224 functions to reset the clock domain of the valid signal to match the operation clock of the receiver 220.

FIG. 5 is a diagram illustrating a data connection between blocks using the AXI protocol according to an embodiment of the present invention. FIG. 6 is a diagram illustrating a clock and reset connection between blocks using the AXI protocol according to the present invention. The Advanced Microcontroller Bus Architecture (AMBA) specification defines technical specifications for buses connecting IPs within a SoC. The AMBA 3.0 specification, which designs the bus structure for high-speed operation, is generally called the AXI protocol.

In FIG. 5 and FIG. 6, block A and block B belong to different domains and differ in at least one of clock, power, and voltage. At this time, the transmitter 210 and the receiver 220 are responsible for connecting the block A and the block B and have the same payload channel as the AXI protocol.

5, the payload data of the read address channel AR, the write address channel AW and the write data channel W and the payload data of the read data channel R and the write response channel B, The transmitter 210 and the receiver 220 are arranged to correspond to the directionality of the payload data.

Referring to FIG. 6, ACLK and ARESET of block A are transmitted to block B, and BCLK and BRESET of block B are transmitted to block A. The clock is transmitted to the receiver 220 and is synchronized to the FIFO 222 and the third Gray code counter 223 and the reset is sent to the transmitter 210 and the receiver 220 to be used for resetting the synchronized logic.

As described above, the embodiments of the present invention have been disclosed in the present specification and drawings, and although specific terms have been used, they have been used only in a general sense to easily describe the technical contents of the present invention and to facilitate understanding of the invention. And is not intended to limit the scope of the invention. It will be apparent to those skilled in the art that other modifications based on the technical idea of the present invention are possible in addition to the embodiments disclosed herein.

210: Transmitter
221: FIFO transmission controller
212: register slice
213, 217, 223, 225: gray code counter
214: Strobe synchronizer
215, 227, 228: AND gate
216: FIFO Pool Generator
216a: Internal counter
218, 229: comparator
220: receiver
221: FIFO reception controller
222: FIFO
224: Balanced Synchronizer
226: clock gate

Claims (7)

A single-channel asynchronous bridge system having a transmitter and a receiver for connecting a plurality of blocks belonging to different domains in a system-on-chip,
The transmitter (210)
A register slice (212) for temporarily storing payload data and a source valid signal provided from a source to separate timing and transmit the payload data to the receiver over a single payload channel;
A first counter 213 receiving a strobe signal from the receiver and generating a first pointer that tracks a read pointer of a FIFO built in the receiver;
A strobe synchronizer 214 receiving the first pointer and resetting the first pointer to the clock domain of the transmitter;
And generating a transmission valid signal corresponding to the source valid signal to provide the transmission valid signal to the receiver and comparing the count value by the transmission valid signal with the count value by the first pointer, And a FIFO transmission controller (211) for controlling whether or not the register slice transmits the payload data to the receiver according to a result of the determination of the FULL state,
The receiver (220)
A FIFO (222) for receiving and storing payload data from the transmitter over the single payload channel;
A third counter (223) for generating a write pointer corresponding to the transmission valid signal and providing the write pointer as a write address of the FIFO;
A valid synchronizer 224 for receiving the write pointer and resetting the write pointer to the clock domain of the receiver;
A read pointer is generated to correspond to the destination valid signal and the destination read signal, and is provided as a read address of the FIFO, and the count value by the transfer valid signal and the read value by the destination valid signal and the destination read signal And a FIFO receiving controller 221 for comparing the counted value to determine whether or not the FIFO is EMPTY, generating a strobe signal corresponding to the determination result of the EMPTY and the destination ready signal, and transmitting the generated strobe signal to the transmitter Channel asynchronous bridge system for a block connection of different domains.
The method according to claim 1,
The FIFO transmission controller 211,
A first AND gate (215) for ANDing the source valid signal and the result of the FULL determination to generate the transmission valid signal;
A second counter (217) for generating a second pointer following the first pointer generated by the first counter;
A first comparator (218) for generating a pop signal that remains valid while the values of the first pointer and the second pointer are different;
A built-in counter counting up by the source valid signal and counting down by the pop signal to determine whether the FIFO built in the receiver is FULL based on the value of the built-in counter, A FIFO pool generator 216 for providing a corresponding signal to the ready port of the register slice 212 to perform transmission control on the payload data;
Channel asynchronous bridge system for a block connection of different domains.
The method of claim 2,
The FIFO reception controller 221,
A second AND gate (227) for ANDing the destination valid signal and the destination ready signal to generate a first enable signal;
A fourth counter (225) for generating the read pointer corresponding to a period in which the first enable signal is HIGH and providing the read pointer as a read address of the FIFO;
A second comparator (229) for generating the destination valid signal that remains valid while the value of the write pointer and the value of the read pointer are different;
A third AND gate 228 for performing a logical multiplication of the destination valid signal and the destination ready signal to generate a second enable signal;
A clock gate (226) for generating the strobe signal corresponding to a period in which the first enable signal is HIGH and transmitting the generated strobe signal to the transmitter;
Channel asynchronous bridge system for a block connection of different domains.
The method of claim 3,
The transmitter 210 transmits a clock signal of the transmitter domain to the receiver 220,
Wherein the receiver (220) receives the clock signal of the transmitter domain and inverts the input clock to the counting clock of the third counter and the operating clock of the FIFO.
The method of claim 4,
Channel asynchronous bridge system for a block connection of different domains, wherein the transmission valid signal and the strobe signal exchanged between the transmitter (210) and the receiver (220) are composed of a single bit.
The method of claim 5,
Wherein a plurality of transmitters (210) and a plurality of receivers (220) included in a plurality of blocks belonging to different domains constitute reset of synchronized logic by interlocking a reset signal. Asynchronous bridge system.
The method of claim 6,
Wherein the first to fourth counters (213, 217, 223, and 225) are configured with gray code counters and the FIFO (222) is configured with a depth configurable FIFO. Asynchronous bridge system.

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