CN116701297A - Synchronous bridge circuit, bus device and system on chip - Google Patents
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Abstract
The present disclosure relates to an asynchronous bridge circuit, a bus device, and a system on a chip. The asynchronous bridge circuit includes: a first asynchronous sub-module for placement in a first cure domain, and configured to operate based on a first clock frequency in the first cure domain; and a second asynchronous sub-module connected in asynchronous communication with the first asynchronous sub-module, the second asynchronous sub-module for placement in a second curing domain, and the second asynchronous sub-module configured to operate based on a second clock frequency in the second curing domain that is different from the first clock frequency.
Description
Technical Field
The present disclosure relates to the technical field of electronic circuits, and in particular, to an asynchronous bridge circuit, a bus device, and a system on a chip.
Background
For the reasons of simplifying Chip design and reducing running power consumption, a System On Chip (SOC) may be divided into a plurality of curing domains, different curing domains may be separately designed and may belong to different power domains or clock domains, respectively, so as to realize independent power-up and power-down control or clock control in the curing domains. However, when data communication is performed between different solidified domains, different clock frequencies in the solidified domains will cause timing problems.
Disclosure of Invention
It is an object of the present disclosure to propose an asynchronous bridge circuit, a bus device and a system on chip to solve the problem of data communication between solidified domains with different clock frequencies.
According to a first aspect of the present disclosure, there is provided an asynchronous bridge circuit comprising:
a first asynchronous sub-module for placement in a first cure domain, and configured to operate based on a first clock frequency in the first cure domain; the method comprises the steps of,
a second asynchronous sub-module connected in asynchronous communication with the first asynchronous sub-module, the second asynchronous sub-module for placement in a second curing domain, and the second asynchronous sub-module configured to operate based on a second clock frequency in the second curing domain that is different from the first clock frequency.
In some embodiments, one of the first and second synchronization sub-modules includes a caching component configured to cache pending data based on a clock frequency in a solidification domain in which the caching component resides; the method comprises the steps of,
the other of the first and second synchronous sub-modules includes a reading component configured to read the data to be transmitted based on a clock frequency in a cure domain in which the reading component is located;
The size of the cache space of the cache component is larger than the size of the space occupied by data read each time.
In some embodiments, the asynchronous bridge circuit comprises a first-in-first-out FIFO synchronous bridge, wherein the FIFO synchronous bridge comprises a write sub-module and a read sub-module, one of the write sub-module and the read sub-module being the first synchronous sub-module and the other of the write sub-module and the read sub-module being the second synchronous sub-module.
In some embodiments, the write submodule includes a write synchronizer, a write controller, and a FIFO memory, wherein:
the write synchronizer is communicatively connected with the read sub-module and is configured to receive a read pointer from the read sub-module and synchronize the read pointer with a clock frequency in a cure domain in which the write sub-module is located;
the write controller is communicatively connected with the write synchronizer and is configured to generate corresponding write control signals according to the synchronized read pointer, write pointer, and write request signals; and, a step of, in the first embodiment,
the FIFO memory is communicatively connected to the write controller, and the FIFO memory is configured to receive and store data to be transferred in response to the write control signal indicating write data.
In some embodiments, the write controller is further configured to convert the write pointer in binary form to a write pointer in gray form.
In some embodiments, the write controller is configured to generate the respective write control signals from the synchronized read pointer, write pointer, and write request signals, including:
the write controller is configured to generate a first storage state indication signal according to the synchronized read pointer and write pointer; and, a step of, in the first embodiment,
the write controller is configured to generate the write control signal according to the first storage state indication signal and the write request signal;
wherein the write control signal indicates writing data in case the first storage state indication signal indicates that the FIFO memory is in a non-full state and the write request signal indicates that a write request exists, otherwise the write control signal indicates not writing data.
In some embodiments, the read submodule includes a read synchronizer, a read controller, and a selector, wherein:
the read synchronizer is communicatively connected with the write submodule and is configured to receive a write pointer from the write submodule and synchronize the write pointer with a clock frequency in a cure domain in which the read submodule is located;
The read controller is communicatively connected with the read synchronizer and is configured to generate corresponding read control signals in accordance with the synchronized write pointer, read pointer and read request signals; and, a step of, in the first embodiment,
the selector is communicatively coupled to the read controller and FIFO memory in the write sub-module, and the selector is configured to select and receive pending data in the FIFO memory in response to the read control signal indicating read data.
In some embodiments, the read controller is further configured to convert the read pointer in binary code form to a read pointer in gray code form.
In some embodiments, the read controller is configured to generate respective read control signals from the synchronized write pointer, read pointer, and read request signals, including:
the read controller is configured to generate a second storage state indication signal according to the synchronized write pointer and read pointer; and, a step of, in the first embodiment,
the read controller is configured to generate the read control signal according to the second storage state indication signal and the read request signal;
Wherein the read control signal indicates to read data if the second storage state indication signal indicates that the FIFO memory is in a non-empty state and the read request signal indicates that a read request exists, otherwise the read control signal indicates not to read data.
In some embodiments, the read synchronizer is communicatively connected with a write controller in the write sub-module, and the read synchronizer is configured to receive a write pointer from the write controller; and, a step of, in the first embodiment,
the read controller is communicatively connected with a write synchronizer in the write sub-module, and the read controller is configured to transmit a read pointer to the write synchronizer.
In some embodiments, each of the write synchronizer and the read synchronizer includes two or more synchronization registers connected in series with each other.
In some embodiments, a transmission time for transmitting the pending data from the write submodule to the read submodule is less than or equal to a synchronization time of any one of the write synchronizer and the read synchronizer.
According to a second aspect of the present disclosure, there is provided a bus apparatus comprising:
One or more bridge channels, wherein at least one of the one or more bridge channels comprises an asynchronous bridge circuit as described above.
In some embodiments, the bus device further comprises:
a first bus connected at a first end of the one or more bridge channels, and configured to be disposed in the first cure domain; the method comprises the steps of,
a second bus connected at a second end of the one or more bridge channels different from the first end, and configured to be disposed in the second cure domain;
wherein the first bus and the second bus are the same type of bus or different types of buses.
In some embodiments, either of the first bus and the second bus comprises an AXI bus or an AHB bus.
According to a third aspect of the present disclosure, there is provided a system on a chip, comprising:
a plurality of cure domains, wherein at least two of the plurality of cure domains are each configured to operate based on a different clock frequency; the method comprises the steps of,
an asynchronous bridge circuit or bus arrangement as described above.
Other features of the present disclosure and its advantages will become apparent from the following detailed description of exemplary embodiments of the disclosure, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description, serve to explain the principles of the disclosure.
The disclosure may be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:
FIG. 1 shows a schematic diagram of an asynchronous bridge circuit in a system-on-chip;
FIG. 2 shows a schematic diagram of a clock path in the system-on-chip of FIG. 1;
FIG. 3 illustrates a schematic diagram of an asynchronous bridge circuit across a curing domain in a system-on-chip according to an exemplary embodiment of the present disclosure;
FIG. 4 illustrates a schematic diagram of an asynchronous bridge circuit in a specific embodiment in accordance with the present disclosure;
FIG. 5 illustrates a schematic diagram of a bus arrangement according to an exemplary embodiment of the present disclosure;
fig. 6 shows a schematic diagram of the structure of an AXI2AXI bus arrangement in a specific embodiment according to the present disclosure.
Note that in the embodiments described below, the same reference numerals are used in common between different drawings to denote the same parts or parts having the same functions, and a repetitive description thereof may be omitted. In this specification, like reference numerals and letters are used to designate like items, and thus once an item is defined in one drawing, no further discussion thereof is necessary in subsequent drawings.
For ease of understanding, the positions, dimensions, ranges, etc. of the respective structures shown in the drawings and the like may not represent actual positions, dimensions, ranges, etc. Accordingly, the disclosed invention is not limited to the disclosed positions, dimensions, ranges, etc. as illustrated in the drawings. Moreover, the figures are not necessarily to scale, some features may be exaggerated to show details of particular components.
Detailed Description
Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present disclosure unless it is specifically stated otherwise.
The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the disclosure, its application, or uses. That is, the various techniques, methods, and apparatus herein are shown by way of example to illustrate different embodiments in the present disclosure and are not intended to be limiting. Those skilled in the art will appreciate that they are merely illustrative of exemplary ways in which the invention may be practiced, and not exhaustive.
Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail, but should be considered part of the specification where appropriate.
Generally, a system on a chip may be divided into a plurality of curing domains, each of which may be individually designed to simplify the design difficulty and improve the design efficiency. Wherein, different solidification domains can be respectively in different power domains or clock domains, thus realizing independent power-on and power-off control or clock control, thereby helping to reduce the power consumption of the whole system-on-chip. However, since buses in different solidified domains may use different clock frequencies, this may lead to problems in data transfer between such two solidified domains, especially in high-speed data transfer.
In order to solve the above-described problems, in a system on chip, when data transmission between the first and second curing domains 110' and 120' is required, the first bus 111' of the first curing domain 110' passes through the domain boundaries of the first and second curing domains 110' and 120', enters the second curing domain 120', and is transferred to the second bus 121' of the second curing domain 120' through the asynchronous bridge circuit 300' provided in the second curing domain 120', in a manner as shown in fig. 1. In the specific example shown in fig. 1, the first bus 111 'corresponds to a Master Port (MP) for transmitting data, and the second bus 121' corresponds to a Slave Port (SP) for receiving data. However, it will be appreciated that in other cases the master and slave ends may be interchanged. Wherein the first solidified domain 110 'is in the first clock domain 210', a portion of the second solidified domain 120 'comprising the first bus 111' and a portion of the asynchronous bridge circuit 300 'is also in the first clock domain 210', and the other portion of the second solidified domain 120 'is in the second clock domain 220'.
However, in the case of data transmission across the cure domain in the manner shown in fig. 1, the following problems may exist:
first, as shown in fig. 2, a first On-Chip Clock (OCC) 112' may be provided in the first solidified domain 110', and the first solidified domain 110' in the first Clock domain 210' may perform Clock tree synthesis based On the first On-Chip Clock 112 '. However, since a portion of the second cure domain 120 'is also in the first clock domain 210', this back end requires clock tree synthesis (Clock Tree Synthesis, CTS) in both the first cure domain 110 'and the second cure domain 120' with respect to the first on-chip clock 112', i.e., at least a portion of the clocks in the second cure domain 120' are dependent on the first on-chip clock 112 'in the first cure domain 110'. Thus, once the clock tree synthesis is performed again for either one of the first cure domain 110 'and the second cure domain 120', if the corresponding clock tree length or clock skew (skew) changes, a corresponding adjustment is required for the clock tree in the other cure domain, which results in an increase in chip design difficulty and a decrease in design efficiency.
Second, due to differences in temperature, supply voltage, etc. between the first cure domain 110 'and the second cure domain 120', there may be differences in the degradation coefficients of the clocks in the two cure domains, and in order to meet the requirements of holding time (i.e., delay time cannot be less than holding time) in the static timing analysis (Static Timing Analysis, STA), it may be necessary to add corresponding delay units in the cure domains. However, as the delay unit increases, there is a possibility that the requirement of the setup time (i.e., the delay cannot be greater than the setup time) in the static timing analysis cannot be satisfied. Specifically, as shown in fig. 2, when the clock tree length of the first on-chip clock 112' exceeds a certain threshold, the Data delay (Data delay), the first clock tree delay (Clk delay 1), and the second clock tree delay (Clk delay 2) may not meet the requirements of the setup time and the hold time at the same time.
The conflicts in timing as described above will result in a reduction in the chip back-end verification (signoff) frequency, directly affecting the performance parameters of the chip.
In order to solve the above-mentioned problem, the present disclosure proposes an asynchronous bridge circuit, which splits the asynchronous bridge circuit into two asynchronous submodules according to a clock domain and sets the two asynchronous submodules in two curing domains respectively, so as to avoid clock tree synthesis across the curing domains, thereby easily realizing timing sequence convergence.
In an exemplary embodiment of the present disclosure, as shown in fig. 3, the asynchronous bridge circuit may include a first synchronous sub-module 310 and a second synchronous sub-module 320. Wherein the first asynchronous sub-module 310 is for placement in the first cure domain 110, and the first asynchronous sub-module 310 may be configured to operate based on a first clock frequency (i.e., the first on-chip clock 112) in the first cure domain 110; the second synchronization sub-module 320 is for placement in the second cure domain 120, and the second synchronization sub-module 320 may be configured to operate based on a second clock frequency (i.e., the second on-chip clock 122) in the second cure domain 120 that is different from the first clock frequency. In other words, the asynchronous bridge circuit is split into two synchronous sub-modules according to the clock domain, wherein the first synchronous sub-module 310 is provided in the first clock domain 210 and the second synchronous sub-module 320 is provided in the second clock domain 220. By splitting the asynchronous bridge circuit into two different asynchronous sub-modules according to the clock domain and arranging them in the corresponding curing domain or clock domain, respectively, the asynchronous sub-modules in each curing domain can be operated according to the clock frequency in that curing domain. It follows that clock tree synthesis of one cure domain based on an on-chip clock in the other cure domain as shown in fig. 1 is no longer required. On the one hand, the clock trees in the two curing domains can be independent of each other, no dependency exists, and when the clock tree in one curing domain is recombined, the clock tree in the other curing domain is not influenced, so that the design difficulty is reduced, and the design efficiency is improved. On the other hand, since the setup time path and the hold time path between the two curing domains are not involved any more, so long as the data transmission delay between the two curing domains is less than or equal to a certain maximum delay, the timing closure can be easily realized, the occurrence of the conflict between the setup time and the hold time is avoided, and the control of the data transmission delay can be simply realized through comprehensive constraint and layout planning (floorplan) in the system on a chip.
Further, between the second synchronous sub-module 320 and the first synchronous sub-module 310, it may be connected in an asynchronous communication manner, so as to implement asynchronous transmission of the data to be transmitted. In some embodiments, one of the first and second synchronization sub-modules 310, 320 may include a cache component and the other may include a read component. Wherein the caching component may be configured to receive and cache the data to be transferred based on a clock frequency in a curing domain in which the caching component is located, and the reading component may be configured to read the required data to be transferred from the caching component based on the clock frequency in the curing domain in which the reading component is located. It can be appreciated that the size of the buffer space of the buffer component may be larger than the size of the space occupied by the data read each time, so as to realize asynchronous transmission of the data by utilizing the buffer characteristic of the buffer component. The cache component and the read component can be provided in a variety of ways, without limitation. In addition, in other embodiments, asynchronous communication between the first synchronous sub-module 310 and the second synchronous sub-module 320 may be implemented in other possible manners, which are not limited herein.
In a particular embodiment, asynchronous communication between the first synchronous sub-module 310 and the second synchronous sub-module 320 may be implemented on a first-in-first-out (FIFO) basis. As shown in fig. 4, the asynchronous bridge circuit may comprise a FIFO synchronous bridge. The FIFO synchronous bridge may include a writing sub-module 410 (or FIFO writing Domain, FIFO Push Domain) and a reading sub-module 420 (or FIFO reading Domain, FIFO Pop Domain), one of the writing sub-module 410 and the reading sub-module 420 may serve as the first synchronous sub-module 310, and the other of the writing sub-module 410 and the reading sub-module 420 may serve as the second synchronous sub-module 320, according to the direction of data transmission.
Further, as shown in fig. 4, in some embodiments, the write submodule 410 may include a write synchronizer 411, a write controller 412, and a FIFO memory 413. The caching component as described above may comprise at least a FIFO memory 413 in the writing sub-module 410.
The write synchronizer 411 may be communicatively connected with the read sub-module 420, for example, may be communicatively connected with a read controller 422 in the read sub-module 420, and the write synchronizer 411 may be configured to receive the read pointer from the read sub-module 420 (or the read controller 422) and synchronize the read pointer with a clock frequency in a cure domain in which the write sub-module 412 is located for subsequent comparison of the read pointer and the write pointer.
In some embodiments, to simplify the synchronization process, the read pointer received by the write synchronizer 411 may be in the form of a gray code, which may be generated by the read controller 422 in the read sub-module 420 converting the read pointer in binary code. It will be appreciated, however, that the binary encoded version of the read pointer may be converted to other encoded versions as long as it is convenient to be synchronized by the write synchronizer 411, and is not limited in this regard. In some embodiments, the write synchronizer 411 may include two synchronization registers connected in series with each other to synchronize the read pointer in gray code into the clock domain in which the write submodule 410 resides, avoiding metastable states that may occur when synchronizing using only a single synchronization register. However, in other embodiments, the write synchronizer 411 may include more synchronization registers as needed to provide sufficient transmission delay, etc. (as will be described in more detail below), without limitation.
The write controller 412 may be communicatively coupled to the write synchronizer 411, and the write controller 412 may be configured to generate corresponding write control signals based on the synchronized read pointer, write pointer, and write request signals. In some embodiments, the write controller 412 may also be configured to convert the write pointer in binary form into a write pointer in gray code form (push ptr_g), which may be transferred into the read sub-module 420 for synchronization on the one hand, and to compare the write pointer with the read pointer on the other hand. Of course, in some embodiments, write controller 412 may also compare the write pointer to the read pointer in binary encoded form, without limitation.
In some embodiments, the various signals may have a high level and a low level to indicate different states, respectively. For example, the write controller 412 may be configured to generate a first storage state indication signal (ready_m) based on the synchronized read pointer and write pointer. In a specific example, when the write pointer is one fifo_depth (i.e., the DEPTH of the FIFO memory 413) larger than the read pointer, it may be determined that the storage state of the FIFO memory 413 currently written in the sub-module 410 is a full state, at which time the first storage state indication signal may be set to a low level; otherwise, it may be determined that the storage state of the FIFO memory 413 currently written in the submodule 410 is a non-full state, at which time the first storage state indication signal may be set to a high level. Accordingly, in the case where the first storage state indicating signal is at a low level, data cannot be continuously written into the FIFO memory 413; and in the case where the first storage state indicating signal is at a high level, data may be written into the FIFO memory 413. Further, the write controller 412 may be further configured to generate the write control signal (we_addr) according to the first storage state indication signal (ready_m) and the write request signal (valid_m). In a specific example, in the case where there is a write request currently, the write request signal may be set to a high level; otherwise, the write request signal may be set to a low level. Further, in a case where the first storage state indication signal indicates that the FIFO memory 413 is in a non-full state (i.e., ready_m is at a high level) and the write request signal indicates that there is a write request (i.e., valid_m is at a high level), the write control signal (we_addr) may indicate write data, at which time the FIFO memory 413 may receive and store pending data (source payload) shown in fig. 4; otherwise, the write control signal indicates that no data is written, at which point the FIFO memory 413 does not receive and store the data to be transferred. It will be appreciated that in other specific examples, the storage state of the FIFO memory 413 may be determined in other ways, or various signals and levels thereof may be set to indicate the corresponding states, without limitation.
The FIFO memory 413 may be communicatively connected to the write controller 412, and the FIFO memory 413 may be configured to receive and store the data to be transferred in response to the write control signal indicating the write data. The size of the memory space of the FIFO memory 413 may be obtained according to its bit width and depth, and the data written into the FIFO memory 413 each time is located in the uppermost empty memory cell thereof according to the principle of first-in first-out.
As shown in fig. 4, the read sub-module 420 may include a read synchronizer 421, a read controller 422, and a selector 423. The reading assembly as described above may include at least a selector 423 in the reading sub-module 420.
The read synchronizer 421 may be communicatively connected with the write submodule 410, for example, may be communicatively connected with the write controller 412 in the write submodule 410, and the read synchronizer 421 may be configured to receive the write pointer from the write submodule 410 (or the write controller 412) and synchronize the write pointer with the clock frequency in the cure domain in which the read submodule 420 is located in order to subsequently compare the write pointer with the read pointer.
In some embodiments, to simplify the synchronization process, the write pointer received by the read synchronizer 421 may be in the form of a gray code, which may be generated by the write controller 412 in the write sub-module 410 converting the write pointer in binary code. It will be appreciated, however, that the binary encoded form of the write pointer may be converted to other encoded forms as long as it is convenient to be synchronized by the read synchronizer 421, and is not limited in this regard. In some embodiments, the read synchronizer 421 may include two synchronization registers connected in series with each other to synchronize the write pointer in gray code into the clock domain in which the read sub-module 420 resides, avoiding metastables that may occur when synchronizing using only a single synchronization register. However, in other embodiments, the read synchronizer 421 may include more synchronization registers as needed to provide sufficient transmission delay, etc. (as will be described in more detail below), without limitation.
The read controller 422 may be communicatively connected with the read synchronizer 421, and the read controller 422 may be configured to generate corresponding read control signals based on the synchronized write pointer, read pointer, and read request signals. In some embodiments, the read controller 422 may also be configured to convert the binary code form of the read pointer into a gray code form of the read pointer, which may be transmitted into the write sub-module 410 for synchronization on the one hand, and to compare the read pointer and the write pointer on the other hand. Of course, in some embodiments, read controller 422 may also compare the read pointer and the write pointer in binary encoded form, without limitation.
As described above, the various signals may have high and low levels to indicate different states, respectively. For example, the read controller 422 may be configured to generate a second storage state indication signal (valid_s) according to the synchronized write pointer and read pointer. In a specific example, when the read pointer and the write pointer are the same, it may be determined that the storage state of the FIFO memory 413 in the current writing sub-module 410 is an empty state, at which time the second storage state indication signal may be set to a low level; otherwise, it may be determined that the storage state of the FIFO memory 413 currently written in the submodule 410 is a non-empty state, at which time the second storage state indication signal may be set to a high level. Accordingly, in the case where the second storage state indicating signal is at a low level, data cannot be read from the FIFO memory 413; and in the case where the second storage state indicating signal is at a high level, data can be read from the FIFO memory 413. Further, the read controller 422 may be further configured to generate the read control signal (rd_addr) according to the second storage state indication signal (valid_s) and the read request signal (ready_s). In a specific example, in the case where there is a read request currently, the read request signal may be set to a high level; otherwise, the read request signal may be set to a low level. Further, in the case where the second storage state indication signal indicates that the FIFO memory 413 is in a non-empty state (i.e., valid_s is at a high level) and the read request signal indicates that there is a read request (i.e., ready_s is at a high level), the read control signal (rd_addr) may indicate to read data, at which time the corresponding data to be transmitted (the output data (sink payload) shown in fig. 4 or fifo_mem shown in fig. 6) may be read from the FIFO memory 413 through the selector 423; otherwise, the read control signal indicates that the data is not to be read. It will be appreciated that in other specific examples, the storage state of the FIFO memory 413 may be determined in other ways, or various signals and levels thereof may be set to indicate the corresponding states, without limitation.
The selector 423 may be communicatively connected with the read controller 422 and the FIFO memory 413 in the write sub-module 410, and the selector 423 may be configured to select and receive the data to be transferred in the FIFO memory 413 in response to the read control signal indicating the read data. In some embodiments, the selector 423 may include a Multiplexer (MUX). Accordingly, a read control signal may be transmitted to the control terminal of the multiplexer to effect selection of the data stored in the FIFO memory 413. However, it will be appreciated that in other embodiments, other selection circuits may be used to select the corresponding data to be transmitted, which is not limited herein. Furthermore, according to the first-in first-out principle, the data read each time may be the data in the FIFO memory 413 located in the lowest layer of full memory cells thereof, and the data read each time occupies only a part of the memory space of the FIFO memory 413, thereby implementing asynchronous transmission of the data.
Based on the asynchronous bridge circuit shown in fig. 4, in order to ensure correct timing in the system on chip, the transmission time of the data to be transmitted from the write sub-module 410 to the read sub-module 420 is only required to be less than or equal to the synchronization time of either one of the write synchronizer 412 and the read synchronizer 422. That is, as long as the time required for the selector 423 to read out the corresponding data to be transferred from the FIFO memory 413 is less than or equal to the synchronization time of either one of the write synchronizer 412 and the read synchronizer 422, which can be simply achieved by comprehensive constraint and layout planning in the system on chip.
According to another aspect of the present disclosure, a bus arrangement is also presented. As shown in fig. 5, in an exemplary embodiment, the bus apparatus may include one or more bridge channels 530, wherein at least one bridge channel 530 of the one or more bridge channels 530 may include an asynchronous bridge circuit as described above. That is, the bridge channel 530 may be split into two parts according to the clock domain, wherein the first and second asynchronous sub-modules operate in the respective solidified domains based on the respective clock frequencies, respectively, without affecting each other, thereby facilitating a simple implementation of timing closure in the asynchronously operating solidified blocks.
In some embodiments, the bus may be included in a bus device. For example, as shown in fig. 5, the bus apparatus may further include a first bus 510 and a second bus 520, the first bus 510 being connected at a first end of the one or more bridge channels 530, and the first bus 510 being for placement in a first cured domain, the second bus 520 being connected at a second end of the one or more bridge channels 530, different from the first end, and the second bus 520 being for placement in a second cured domain. In some embodiments, first bus 510 and second bus 520 may be the same type of bus. In other embodiments, first bus 510 and second bus 520 may be different types of buses, not limiting herein. The number of bridge channels 530 in the bus apparatus may be determined according to the specific types of the first bus 510 and the second bus 520 to be bridged.
In a specific example, as shown in fig. 6, an asynchronous bridge circuit 300 may be used to bridge between an AXI (advanced extensible interface) bus and the AXI bus, both AXI buses may be used in different solidification domains or power domains, respectively, and have different clock frequencies, i.e., the asynchronous bridge circuit 300 may act as a power domain asynchronous bridge (Power Domain Bridge, PDB). In the specific example shown in fig. 6, the bus arrangement may comprise five bridge channels in total, each bridge Channel being operable to bridge one Channel in one AXI bus and a corresponding Channel in another AXI bus, including a read address Channel (AR Channel), a read data Channel (R Channel), a write address Channel (AW Channel), a write data Channel (W Channel) and a write response Channel (B Channel). Wherein each bridge channel may comprise an asynchronous bridge circuit as described above. As shown in fig. 6, in the read address Channel (AR Channel), the write sub-module of the asynchronous bridge circuit may be set at the master (axi2axi_pdb_mp), and the read sub-module may be set at the slave (axi2axi_pdb_sp); in the read data Channel (R Channel), the writing sub-module of the asynchronous bridge circuit may be set at the slave end (axi2axi_pdb_sp), and the reading sub-module may be set at the master end (axi2axi_pdb_mp); in the write address Channel (AW Channel), the write sub-module of the asynchronous bridge circuit may be provided at the master end (axi2axi_pdb_mp), and the read sub-module may be provided at the slave end (axi2axi_pdb_sp); in the write data Channel (W Channel), the write sub-module of the asynchronous bridge circuit may be provided at the master end (axi2axi_pdb_mp), and the read sub-module may be provided at the slave end (axi2axi_pdb_sp); and in the write response Channel (B Channel), the write sub-module of the asynchronous bridge circuit may be provided at the slave (axi2axi_pdb_sp), and the read sub-module may be provided at the master (axi2axi_pdb_mp). Here, the master may be in one cure domain or clock domain and the slave in another cure domain or clock domain. It will be appreciated that in other embodiments, the bus apparatus may be used to bridge other types of buses, including an AHB bus, etc., such as, but not limited to, a bridge between an AXI bus and an AHB bus, or a bridge between two AHB buses.
According to yet another aspect of the present disclosure, a system on a chip is also presented. In an exemplary embodiment, as shown in FIG. 3, the system-on-chip may include a plurality of curing domains (e.g., a first curing domain 110 and a second curing domain 120) and an asynchronous bridge circuit or bus device as described above. Wherein at least two of the plurality of cure domains are each configured to operate based on a different clock frequency.
In some embodiments, as the depth of the FIFO memory in the asynchronous bridge circuit increases, in order to maintain the correctness of the voltage in the system on chip, a level shift cell (level shift cell) for shifting the voltage, an isolation cell (isolation cell) for isolating the voltage, and the like may be correspondingly increased, which is not limited herein.
The technical scheme of the disclosure provides a bus connection mode between different solidification domains, and by splitting the asynchronous bridge circuit into different sub-modules according to clock domains and respectively arranging the sub-modules in corresponding solidification domains, the time sequence problem caused by data transmission between solidification domains of different clocks can be avoided while the bus connection bandwidth is ensured. Because each sub-module only needs to operate according to the clock signals in the curing domain where the sub-module is located, different sub-modules are connected in an asynchronous communication mode, the rear end only needs to integrate the clock tree in each curing domain based on the corresponding clock signals, decoupling is carried out among different curing domains, and the dependency relationship on the clock tree does not exist, so that the design difficulty can be effectively reduced, and the design efficiency can be improved. Moreover, since there is no setup time and hold time path between any different cure domains, timing closure can be easily achieved. The timing paths between the clock domains only need to meet a certain maximum delay to ensure the correctness of the timing, and the maximum delay can be simply realized based on the comprehensive constraint and layout planning of the system on chip.
In all examples shown and discussed herein, any specific values should be construed as merely illustrative, and not a limitation. Thus, other examples of the exemplary embodiments may have different values.
The words "front," "back," "top," "bottom," "over," "under," and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the disclosure described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.
As used herein, the word "exemplary" means "serving as an example, instance, or illustration," and not as a "model" to be replicated accurately. Any implementation described herein by way of example is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, this disclosure is not limited by any expressed or implied theory presented in the preceding technical field, background, brief summary or the detailed description.
As used herein, the term "substantially" is intended to encompass any minor variation due to design or manufacturing imperfections, tolerances of the device or element, environmental effects and/or other factors. The word "substantially" also allows for differences from perfect or ideal situations due to parasitics, noise, and other practical considerations that may be present in a practical implementation.
The foregoing description may indicate elements or nodes or features that are "connected" or "coupled" together. As used herein, unless expressly stated otherwise, "connected" means that one element/node/feature is directly connected (or in direct communication) electrically, mechanically, logically, or otherwise with another element/node/feature. Similarly, unless expressly stated otherwise, "coupled" means that one element/node/feature may be directly or indirectly joined to another element/node/feature in a mechanical, electrical, logical, or other manner to permit interactions, even though not directly connected. That is, "coupled" is intended to encompass both direct and indirect coupling of elements or other features, including connections utilizing one or more intermediate elements.
It will be further understood that the terms "comprises" and/or "comprising," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, and/or components, and/or groups thereof.
Those skilled in the art will recognize that the boundaries between the above described operations are merely illustrative. The operations may be combined into a single operation, the single operation may be distributed among additional operations, and the operations may be performed at least partially overlapping in time. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be altered in other various embodiments. However, other modifications, variations, and alternatives are also possible. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
Although some specific embodiments of the present disclosure have been described in detail by way of example, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present disclosure. The embodiments disclosed herein may be combined in any desired manner without departing from the spirit and scope of the present disclosure. Those skilled in the art will also appreciate that various modifications might be made to the embodiments without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.
Claims (16)
1. An asynchronous bridge circuit, the asynchronous bridge circuit comprising:
a first asynchronous sub-module for placement in a first cure domain, and configured to operate based on a first clock frequency in the first cure domain; and
a second asynchronous sub-module connected in asynchronous communication with the first asynchronous sub-module, the second asynchronous sub-module for placement in a second curing domain, and the second asynchronous sub-module configured to operate based on a second clock frequency in the second curing domain that is different from the first clock frequency.
2. The asynchronous bridge circuit of claim 1, wherein one of the first and second synchronous sub-modules comprises a caching component configured to cache pending data based on a clock frequency in a solidified domain in which the caching component resides; and
the other of the first and second synchronous sub-modules includes a reading component configured to read the data to be transmitted based on a clock frequency in a cure domain in which the reading component is located;
The size of the cache space of the cache component is larger than the size of the space occupied by data read each time.
3. The asynchronous bridge circuit of claim 1, comprising a first-in-first-out FIFO synchronous bridge, wherein the FIFO synchronous bridge comprises a write sub-module and a read sub-module, one of the write sub-module and the read sub-module being the first synchronous sub-module and the other of the write sub-module and the read sub-module being the second synchronous sub-module.
4. The asynchronous bridge circuit of claim 3 wherein the write submodule includes a write synchronizer, a write controller, and a FIFO memory, wherein:
the write synchronizer is communicatively connected with the read sub-module and is configured to receive a read pointer from the read sub-module and synchronize the read pointer with a clock frequency in a cure domain in which the write sub-module is located;
the write controller is communicatively connected with the write synchronizer and is configured to generate corresponding write control signals according to the synchronized read pointer, write pointer, and write request signals; and
The FIFO memory is communicatively connected to the write controller, and the FIFO memory is configured to receive and store data to be transferred in response to the write control signal indicating write data.
5. The asynchronous bridge circuit of claim 4 wherein the write controller is further configured to convert a write pointer in binary code form to a write pointer in gray code form.
6. The asynchronous bridge circuit of claim 4 wherein the write controller being configured to generate the corresponding write control signals based on the synchronized read pointer, write pointer, and write request signals comprises:
the write controller is configured to generate a first storage state indication signal according to the synchronized read pointer and write pointer; and
the write controller is configured to generate the write control signal according to the first storage state indication signal and the write request signal;
wherein the write control signal indicates writing data in case the first storage state indication signal indicates that the FIFO memory is in a non-full state and the write request signal indicates that a write request exists, otherwise the write control signal indicates not writing data.
7. The asynchronous bridge circuit of claim 3 wherein the read sub-module comprises a read synchronizer, a read controller, and a selector, wherein:
the read synchronizer is communicatively connected with the write submodule and is configured to receive a write pointer from the write submodule and synchronize the write pointer with a clock frequency in a cure domain in which the read submodule is located;
the read controller is communicatively connected with the read synchronizer and is configured to generate corresponding read control signals in accordance with the synchronized write pointer, read pointer and read request signals; and
the selector is communicatively coupled to the read controller and FIFO memory in the write sub-module, and the selector is configured to select and receive pending data in the FIFO memory in response to the read control signal indicating read data.
8. The asynchronous bridge circuit of claim 7 wherein the read controller is further configured to convert a read pointer in binary code form to a read pointer in gray code form.
9. The asynchronous bridge circuit of claim 7 wherein the read controller being configured to generate respective read control signals based on the synchronized write pointer, read pointer, and read request signals comprises:
The read controller is configured to generate a second storage state indication signal according to the synchronized write pointer and read pointer; and
the read controller is configured to generate the read control signal according to the second storage state indication signal and the read request signal;
wherein the read control signal indicates to read data if the second storage state indication signal indicates that the FIFO memory is in a non-empty state and the read request signal indicates that a read request exists, otherwise the read control signal indicates not to read data.
10. The asynchronous bridge circuit of claim 7 wherein the read synchronizer is communicatively connected with a write controller in the write sub-module and the read synchronizer is configured to receive a write pointer from the write controller; and
the read controller is communicatively connected with a write synchronizer in the write sub-module, and the read controller is configured to transmit a read pointer to the write synchronizer.
11. The asynchronous bridge circuit of claim 10 wherein each of the write synchronizer and the read synchronizer comprises two or more synchronous registers connected in series with each other.
12. The asynchronous bridge circuit of claim 10 wherein a transmission time for transmitting pending data from the write submodule to the read submodule is less than or equal to a synchronization time of either of the write synchronizer and the read synchronizer.
13. A bus apparatus, the bus apparatus comprising:
one or more bridge channels, wherein at least one of the one or more bridge channels comprises an asynchronous bridge circuit according to any one of claims 1 to 12.
14. The bus apparatus of claim 13, wherein the bus apparatus further comprises:
a first bus connected at a first end of the one or more bridge channels, and configured to be disposed in the first cure domain; and
a second bus connected at a second end of the one or more bridge channels different from the first end, and configured to be disposed in the second cure domain;
wherein the first bus and the second bus are the same type of bus or different types of buses.
15. The bus apparatus of claim 14, wherein either of the first bus and the second bus comprises an AXI bus or an AHB bus.
16. A system-on-chip, the system-on-chip comprising:
a plurality of cure domains, wherein at least two of the plurality of cure domains are each configured to operate based on a different clock frequency; and
an asynchronous bridge circuit according to any of claims 1 to 12 or a bus arrangement according to any of claims 13 to 15.
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