KR101392155B1 - Display substrate and method of manufacturing mother substrate for display substrate - Google Patents

Abstract

A method of manufacturing a display substrate and a mother substrate for a display substrate which can improve the reliability of a product and a manufacturing process, the display substrate comprising metal wirings formed in a display region of the base substrate, And a first electrostatic dispersion wiring extending from the test pad portion to one end of the base substrate. The first electrostatic dispersion wiring extends from the test pad portion to one end of the base substrate. Thus, damage to the mother substrate for the display substrate due to static electricity can be prevented, reliability of the manufacturing process can be improved, and reliability of the product can be improved.

Visual inspection, shorting bar, trimming, static electricity, organic layer

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a mother board for a display substrate and a mother board for a display substrate,

1 is a plan view of a display substrate according to an embodiment of the present invention.

2 is a cross-sectional view taken along line I-I 'of FIG.

3 is a plan view of a display substrate according to an embodiment of the present invention.

4 is an enlarged plan view of a portion A in Fig.

5 is a cross-sectional view taken along the line II-II 'of FIG. 4 and a cross-sectional view of the inspection switching device.

6A to 9 are process charts for explaining a manufacturing method of a mother substrate for a display substrate according to the present invention.

Description of the Related Art

100: display substrate 110: base substrate

The present invention relates to a method of manufacturing a mother board for a display substrate and a display substrate, and more particularly, to a method of manufacturing a mother board for a display substrate and a display substrate in which reliability of a product and a manufacturing process is improved.

In general, in a process of manufacturing a liquid crystal display device, a visual inspection (hereinafter referred to as VI) or a visual inspection (hereinafter referred to as " visual inspection ") for inspecting a state in which pixel voltages are applied to pixel electrodes of an array substrate before mounting a driving integrated circuit on a liquid crystal display panel And proceeds with a gross test (hereinafter referred to as GT). The VI or GT can check the defective state of the liquid crystal display panel in advance, thereby reducing the cost and improving the yield.

In the case of VI, if the state in which the pixel voltage is applied in the VI result is good, the inspection signal wiring is cut off from the gate wiring and the source wiring. As a method for cutting the inspection signal wiring from the source wiring and the gate wiring, the inspection signal wiring is cut together with the substrate by diamond cutting or laser cutting is performed by laser trimming (hereinafter referred to as L / T) The signal wiring was separated from the source wiring and the gate wiring. However, in the case of using a laser, there is a problem that a process must be added, contamination particles are generated in the cutting process, and wiring may be corroded through the cut surface. In order to solve this problem, L / T skip process), and the VI is carried out using the inspection switching unit and the inspection pad unit for applying the inspection signal to the inspection switching unit.

On the other hand, there is a problem that reliability of a product and a manufacturing process is lowered due to a short circuit of a wiring or a switching element due to static electricity generated from the outside or flowing from the outside during a process of manufacturing a liquid crystal display device. Particularly, static electricity easily occurs in the short-point or inspection pad portion. Various structures are proposed to prevent the electrostatic failure of the display substrate. However, forming a separate structure for preventing the generation of static electricity raises the manufacturing cost and complicates the manufacturing process.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made keeping in mind the above problems occurring in the prior art, and it is an object of the present invention to provide a display substrate for preventing electrostatic failure of a product including a switching unit for inspection.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a mother board for a display substrate that prevents the generation of static electricity.

According to another aspect of the present invention, there is provided a display substrate including metal wirings formed in a display region of a base substrate, a switching region formed in a peripheral region of the display region, And a first electrostatic dispersion wiring electrically connected to the switching unit for inspection and extending from the inspection pad unit to one end of the base substrate to which the inspection signal is applied.

A method of manufacturing a mother substrate for a display substrate according to an embodiment of the present invention for realizing the above object comprises the steps of: forming a metal wiring formed in a display region of each array region of a base mother substrate including a plurality of array regions; Forming an array layer including an inspection signal line electrically connected to the metal lines and a switching unit connected to the inspection signal line, the method comprising the steps of: forming an array layer on the base mosquito plate Forming a transparent electrode layer on the substrate, patterning the transparent electrode layer, forming a shorting bar between the adjacent array areas by patterning the transparent electrode layer, inspecting pad electrodes formed at one end of the inspection signal wiring, And forming a transparent electrode pattern including the electrostatic dispersion wiring.

According to the method for manufacturing a mother board for a display substrate and a display substrate, external electric charges flowing through the test pad unit can be dispersed immediately by shorting the first electrostatic dispersion wiring. Accordingly, it is possible to prevent the generation of static electricity and prevent the damage of the mother substrate for the display substrate due to the static electricity, thereby improving the reliability of the product and the manufacturing process.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings.

1 is a plan view of a display substrate according to an embodiment of the present invention.

2 is a cross-sectional view taken along line I-I 'of FIG.

1 and 2, a base substrate 110 of a display substrate 100 according to an embodiment of the present invention includes a display region DA including a pixel region P, A first peripheral area PA1 and a second peripheral area PA2.

A gate line GL, a data line DL, a pixel switching element PTFT and a pixel electrode PE are formed in the display area DA. The gate lines GL extend in a first direction of the base substrate 110 and are arranged in parallel in a second direction perpendicular to the first direction. The data lines DL extend in the second direction and a plurality of the data lines DL are arranged in parallel in the first direction. The gate lines GL and the data lines DL intersect each other to define pixel regions P of the display region DA.

The pixel switching element PTFT includes a gate electrode GE connected to the gate line GL and a source electrode SE connected to the data line DL and a drain electrode spaced apart from the source electrode SE DE). A gate insulating layer 130 is formed on the gate electrode GE and a semiconductor layer 142 and an ohmic contact layer 144 are formed between the gate electrode GE and the source electrode SE and the drain electrode DE. ) Are sequentially stacked. A passivation layer 160 including a contact hole exposing one end of the drain electrode DE is formed on the source electrode SE and the drain electrode DE. The pixel electrode PE is electrically connected to the pixel switching element PTFT. The pixel electrode PE is formed on the passivation layer 160 and is contacted with one end of the drain electrode DE through the contact hole. The pixel electrode PE may be formed of a transparent and conductive material. The pixel electrode PE may be formed of, for example, indium tin oxide (ITO) or indium zinc oxide (IZO).

The first peripheral region PA1 is formed with a gate pad portion GP formed at one end of the gate line GL and a first pad portion GP1 for switching between the first inspection switching portion VIT1 and the first inspection signal line 154a, The signal wiring 124a, the first test pad portion VIP1 and the first drive pad portion DIP1 are formed.

In the second peripheral area PA2, a data pad portion DP formed at one end of the data line DL, a second inspection switching portion VIT2, a second inspection signal line 154b, The driving signal wiring 124b, the second inspection pad portion VIP2 and the second driving pad portion DIP2 are formed.

Specifically, the first inspection switching unit VIT1 includes a plurality of first inspection switching elements VI-TFT1. Each first switching element for inspection (VI-TFT1) is connected to the first inspection signal wiring 154a and the first driving signal wiring 124a. The first test pad portion VIP1 is formed at one end of the first test signal line 154a and the first drive pad portion DIP1 is formed at one end of the first drive signal line 124a do.

The first switching element for inspection VI-TFT1 receives a gate inspection signal from the first inspection signal wiring 154a and receives a driving signal from the first driving signal wiring 124a. The first switching element for inspection (VI-TFT1) may transmit the gate inspection signal to the gate wiring (GL) of the display area (DA). For example, the first test signal line 154a is formed of the same source metal layer as the data line DL, and the first test signal line 124a is, for example, the same as the gate line GL Gate metal layer.

The first test pad unit VIP1 includes a first test electrode 152a connected to the first test signal line 154a and a first test pad electrode 172a electrically connected to the first test electrode 152a, . The first test electrode 152a is formed of the same source metal layer as the first test signal line 154a and the first test pad electrode 172a is formed of the same transparent electrode layer as the pixel electrode PE .

The first driving pad unit DIP1 includes a first driving electrode 122a connected to the first driving signal line 124a and a first driving pad electrode 174a electrically connected to the first driving electrode 122a. . The first driving electrode 122a is formed of the same gate metal layer as the first driving signal wiring 124a and the first driving pad electrode 174a is formed in the same transparent electrode layer as the first test pad electrode 172a. As shown in FIG.

The second inspection switching part VIT2 includes a plurality of second inspection switching elements VI-TFT2, and each second inspection switching element VI-TFT2 includes the second inspection signal wiring 154b. And the second driving signal line 124b. The second switching element for inspection VI-TFT2 may transmit a data inspection signal to the data line DL of the display area DA.

The second inspection pad portion VIP2 is formed at one end of the second inspection signal wiring 154b. The second inspection pad unit VIP2 includes a second inspection electrode 152b connected to the second inspection signal wiring 154b and a second inspection pad electrode 172b electrically connected to the second inspection electrode 152b. . The second inspection signal wiring 154b may be formed of, for example, the source metal layer.

The second driving pad portion DIP2 is formed at one end of the second driving signal line 124b. The second driving pad DIP2 includes a second driving electrode 122b connected to the second driving signal line 124b and a second driving pad electrode 174b electrically connected to the second driving electrode 122b. . The second driving signal line 124b may be formed of the gate metal layer, for example.

In a visual inspection (hereinafter referred to as VI) process for checking the state of a voltage applied to the pixel electrode PE of the display area DA, the first and second test pad units VIP1, VIP2 apply the gate check signal and the data check signal. The applied gate inspection signal and the data inspection signal are transferred to the display area DA through the first inspection switching element VI-TFT1 and the second inspection switching element VI-TFT2. Thus, it is possible to check whether the wirings of the display area DA and the switching elements are defective through the gate inspection signal and the data inspection signal transmitted to the display area DA. After the completion of the VI process, when a turn-off voltage is transmitted to the first and second driving signal lines 124a and 124b through the first and second driving pad portions DIP1 and DIP2, The inspection switching parts VIT1 and VIT2 are kept electrically disconnected. Even when the display device including the display substrate 100 is driven, the inspection switching elements of the first and second inspection switching units VIT1 and VIT2 are always kept in the OFF state, It becomes blocked.

The first and second peripheral areas PA1 and PA2 include first electrostatic dispersion interconnections 176a and 178a connected to the first and second test pad units VIP1 and VIP2, Second electrostatic dispersion interconnections 176b and 178b connected to the pad portions DIP1 and DIP2 are formed.

The first electrostatic dispersion wirings 176a and 178a extend from the first inspection pad unit VIP1 to one end of the base substrate 110 and extend from the second inspection pad unit VIP2 to the base substrate 110). The first electrostatic dispersion wiring 176a is connected to the first test pad electrode 172a and the first electrostatic dispersion wiring 178a different from the first electrostatic dispersion wiring 186a is connected to the second test pad electrode 172a, Lt; / RTI > The first electrostatic dispersion interconnects 176a and 178a are formed of the same transparent electrode layer as the first and second test pad electrodes 172a and 172b. The first electrostatic dispersion wirings 176a and 178a are disposed apart from each other.

The second electrostatic dispersion interconnections 176b and 178b extend from the first driving pad portion DIP1 and the second driving pad portion DIP2 to one end of the base substrate 110, respectively. The second electrostatic dispersion wiring 176b is connected to the first driving pad electrode 174a and the second electrostatic dispersion wiring 178b different from the second electrostatic dispersion wiring 176b is connected to the second driving pad electrode 174b, Lt; RTI ID = 0.0 > 174b. The second electrostatic dispersion wirings 176b and 178b are formed of the same transparent electrode layer as the first and second driving pad electrodes 174a and 174b. The second electrostatic dispersion wirings 176b and 178b are disposed apart from each other and the second electrostatic dispersion wirings 176b and 178b are disposed apart from the first electrostatic dispersion wirings 176a and 178a .

The first electrostatic dispersion wirings 176a and 178a and the second electrostatic dispersion wirings 176b and 178b may be connected to a shorting bar (not shown) formed on the mother substrate for the display substrate 100, Respectively. The first electrostatic dispersion wirings 176a and 178a and the second electrostatic dispersion wirings 176b and 178b may be configured to apply charges to the inside of the mother substrate for the display substrate through all of the mother substrate for the display substrate . The first electrostatic dispersion wirings 176a and 178a and the second electrostatic dispersion wirings 176b and 178b may be separated from the shorting bar in the step of cutting the mother substrate for the display substrate into the display substrate 100, And remains on the display substrate 100. The cutting line of the mother substrate for the display substrate and the one end of the base substrate 110 of the display substrate 100 coincide with each other. Accordingly, the first electrostatic dispersion wirings 176a and 178a and the second electrostatic dispersion wirings 176b and 178b may remain on the base substrate 110 in a form extending to one end of the base substrate 110 .

The display panel 100 including the first and second test pad portions VIP1 and VIP2 and the first and second driving pad portions DIP1 and DIP2 may be used as an example of the present invention, However, it may include a plurality of pad portions of 4 or more formed in a large area according to the purpose of VI of the VI process, and may form electrostatic dispersion interconnections connected to the respective pad portions.

3 is a plan view of a display substrate according to an embodiment of the present invention.

3, the base substrate 110 of the display substrate 102 according to the embodiment of the present invention includes a display area DA for displaying an image, A first peripheral area PA1 including a mounting area DIA and an FPC connection area FPCA, and a second peripheral area PA2.

A gate line GL, a data line DL, a pixel switching element PTFT and a pixel electrode PE are formed in the display area DA. The gate line GL and the data line DL cross each other to define a pixel region P.

(Not shown) electrically connected to a driving chip (not shown), a switching unit for inspection (not shown) for a VI process, a test unit connected to the inspection switching unit Signal wiring (not shown) and driving signal wiring (not shown) are formed. FPC pads (not shown) for electrically connecting metal terminals of a flexible printed circuit board (not shown) are formed in the FPC connection area FPCA. The first peripheral area PA1 includes first electrostatic dispersion wirings 176a and 178a extending from the driving chip mounting area DIA to one end of the base substrate 110, 178a and 178a, and the second electrostatic dispersion wirings 176b and 178b extending to one end of the base substrate 110 are formed.

A voltage application part SPA and a third electrostatic dispersion wiring 179 are formed in the second peripheral area PA2. The voltage application unit SPA includes a voltage electrode SPE and a voltage pad electrode SPTE formed on the voltage electrode SPE and electrically connected to the voltage electrode SPE. The third electrostatic dispersion wiring 179 extends from the voltage application part SPA to one end of the base substrate 110. One end of the base substrate 110 is electrically connected to one end of the base substrate 110 that is perpendicular to one end of the base substrate 110 coinciding with the ends of the first and second electrostatic dispersion interconnections 176a, 178a, 176b, It may correspond to a side.

The first peripheral area PA1 extends from the voltage application part SPA to the first peripheral area PA1 along the outer side of the display area DA between the first peripheral area PA1 and the second peripheral area PA2. A common voltage wiring (VCL) is formed. The common voltage wiring (VCL) may be electrically connected to the FPC pads. The common voltage wiring VCL is designed to extend along the outside of the peripheral area DA to transmit a common voltage signal to the display area DA. According to the design of the common voltage wiring VCL, the common voltage wiring VCL overlaps the first and second electrostatic dispersion wirings 176a, 178a, 176b, and 178b.

The first electrostatic dispersion wirings 176a and 178a and the second electrostatic dispersion wirings 176b and 178b may be formed in a shorting bar (not shown) formed on a mother substrate for a display substrate, Respectively. Thereafter, the first electrostatic dispersion wirings 176a and 178a and the second electrostatic dispersion wirings 176b and 178b remain on the display substrate 102 by the cutting process of the mother substrate for the display substrate. Although not shown, fourth electrostatic dispersion interconnects (not shown) connected to the FPC pads may be formed in the FPC connection region FPCA. The fourth electrostatic dispersion wirings are formed in connection with the first to third electrostatic dispersion wirings 176a, 178a, 176b, 178b, 179 and the shorting bar of the mother substrate for the display substrate, And may be separated from the shorting bar and remain on the display substrate 102.

4 is an enlarged plan view of a portion A in Fig.

5 is a cross-sectional view taken along the line II-II 'of FIG. 4 and a cross-sectional view of the inspection switching device.

3 to 5, a first inspection switching unit VIT1, a second inspection switching unit VIT2, first and second inspection signal lines 154a and 154b are formed in the driving chip mounting area DIA, The first and second driving signal lines 124a and 124b and the first inspection pad unit VIP1 and the second inspection pad unit VIP2 and the first driving pad unit DIP1 and the second driving pad unit DIP2) are formed. The first electrostatic dispersion interconnections 176a and 178a are connected to the first test pad unit VIP1 and the second test pad unit VIP2 respectively and the second electrostatic dispersion interconnections 176a and 178b are connected to the first test pad unit VIP1 and the second test pad unit VIP2, Are connected to the first driving pad portion DIP1 and the second driving pad portion DIP2, respectively.

The first and second switching units VIT1 and VIT2 are electrically turned off after the step VI and include the first and second switching units VIT1 and VIT2 in an off state And the driving chip is mounted on the driving chip mounting area (DIA).

Specifically, the first inspection switching unit VIT1 includes the first inspection signal wiring 154a and the first inspection switching element VI-TFT1 connected to the first driving signal wiring 124a, The second switching unit for inspection VIT2 includes a second inspection switching element VI-TFT2 connected to the second inspection signal wiring 154b and the second driving signal wiring 124b. The first switching element for inspection VI-TFT1 includes a gate electrode VG, a source electrode VS formed on the gate electrode VG, and a drain electrode VG.

The first test pad unit VIP1 is formed at one end of the first test signal line 154a. The first test pad unit VIP1 includes a first test electrode 152a connected to the first test signal line 154a and a first test pad electrode 172a electrically connected to the first test electrode 152a, . The first test pad electrode 172a is connected to the first electrostatic dispersion wiring 176a. The second inspection pad portion VIP2 is formed at one end of the second inspection signal wiring 154b. The second inspection pad unit VIP2 includes a second inspection electrode 152b connected to the second inspection signal wiring 154b and a second inspection pad electrode 172b electrically connected to the second inspection electrode 152b. . The second test pad electrode 172b is connected to the first electrostatic dispersion wiring 178a which is different from the first electrostatic dispersion wiring 176a. The first electrostatic dispersion interconnects 176a and 178a are partially overlapped with the common voltage interconnection VCL on the common voltage interconnection VCL.

The first driving pad portion DIP1 is formed at one end of the first driving signal line 124a. The first driving pad unit DIP1 includes a first driving electrode 122a connected to the first driving signal line 124a and a first source metal pattern 156a formed on the first driving electrode 122a. And a first driving pad electrode 174a which is in contact with the source metal pattern 156a and is electrically connected to the first driving electrode 122a. The first driving pad electrode 174a is connected to the second electrostatic dispersion wiring 176b. The second driving pad portion DIP2 is formed at one end of the second driving signal line 124b. The second driving pad DIP2 includes a second driving electrode (not shown) connected to the second driving signal line 124b, a second source metal pattern 156b formed on the second driving electrode, And a second driving pad electrode 174b electrically connected to the second driving electrode in contact with the second source metal pattern 156b. The second driving pad electrode 174b is connected to the second electrostatic dispersion wiring 178b different from the second electrostatic dispersion wiring 176b. The second electrostatic dispersion interconnects 176b and 178b are formed on the common voltage interconnection VCL partially overlapped with the common voltage interconnection VCL.

The display substrate 102 includes a gate insulating layer 130 formed on the gate electrode VG, a semiconductor layer 142 sequentially formed on the gate insulating layer 130 corresponding to the gate electrode VG, A passivation layer 160 formed on the ohmic contact layer 144, the source electrode VS and the drain electrode VG and an organic layer OL formed on the passivation layer 160.

The organic layer OL is formed on the display area DA and the first and second peripheral areas PA1 and PA2 and covers the first and second inspection switching parts VIT1 and VIT2. The organic layer OL includes hole patterns that expose the first source metal pattern 156a and the first test electrode 152a. The source metal pattern 156a and the first driving pad electrode 174a are electrically connected through the hole patterns of the organic layer OL and the first testing electrode 152a is electrically connected to the first testing pad electrode 172a.

The first and second electrostatic dispersion interconnects 176a, 178a, 176b and 178b are formed on the organic layer OL formed on the first peripheral region PA1. The first thickness of the organic layer OL formed on the first peripheral area PA1 may be equal to the second thickness of the organic layer OL formed on the display area DA. Alternatively, the first thickness of the organic layer OL may be less than the second thickness.

The first and second electrostatic dispersion wirings 176a, 178a, 176b and 178b are connected to a shorting bar (not shown) of the mother substrate for a display substrate, And remains on the display substrate 102 separately. The first and second electrostatic dispersion interconnections 176a, 178a, 176b and 178b are connected to the shorting bar and are connected to the test board portions VIP1 and VIP2 and the driving pad portions DIP1 and DIP2, Charges introduced into the board can be dispersed throughout the mother board for the display board to prevent damage to the mother board for display board due to static electricity. In addition, the third electrostatic dispersion wiring 179 is connected to the shorting bar to prevent damage to the display mother board due to static electricity.

The common voltage wiring VCL and the first and second electrostatic dispersion wirings 176a, 178a, 176b, and 176b are formed by forming the organic layer OL in the first peripheral area PA1 of the display substrate 102, 178b are relatively widened. Accordingly, when the common voltage wiring VCL is designed to overlap with the first and second electrostatic dispersion interconnects 176a, 178a, 176b, and 178b, the organic layer OL is formed, Coupling between the common voltage signal transmitted to the common voltage wiring line VCL and the gate inspection signal and data inspection signals applied from the inspection pad units VIP1 and VIP2 and the driving pad units DIP1 and DIP2 Can be minimized.

In addition, by forming the organic layer OL on the passivation layer OL, each of the source electrode and the drain electrode of the switching elements for inspection can be covered with the passivation layer 160 and the organic layer OL. Accordingly, it is possible to prevent the static electricity from being generated by the charges introduced from the outside, and to prevent the damage of the inspection switching elements due to the static electricity.

6A to 9B are process charts for explaining a method of manufacturing a mother substrate for a display substrate according to the present invention.

6A and 6B, the base mother substrate 210 of the mother substrate 200 for a display substrate includes a plurality of array regions AA in which an array layer is formed and a plurality of array regions AA between adjacent array regions AA Includes an outer area SA.

Each array area AA includes a display area DA for displaying an image and a peripheral area PA surrounding the display area DA. The array layer includes a gate wiring (not shown) formed in the display area DA, a data wiring crossing the gate wiring and defining a pixel region, inspection signal wirings formed in the peripheral area PA, Wires, and a voltage electrode (SPE).

Each of the array areas AA of the base mother substrate 210 is formed as one display substrate 100 through a cutting process of cutting the base mother substrate 210 into each array area AA. A cutting line extending in one direction of the base mother substrate 210 is defined as a first cutting line CL1 and a cutting line extending in a direction perpendicular to the one direction is defined as a second cutting line CL2 The first and second cutting lines CL1 and CL2 correspond to virtual lines capable of cutting the display mother board 200 during the cutting process.

Hereinafter, FIGS. 6A to 9 illustrate the case where the pixel switching element (PTFT), the first inspection electrode connected to the first inspection signal wiring among the inspection signal wiring lines, the first inspection electrode connected to the first driving signal wiring among the driving signal wiring lines 1 drive electrode as an example.

Referring to FIG. 6B, a gate metal layer (not shown) is formed on the base mother substrate 210, and the gate metal layer is patterned to form a gate pattern. The patterned gate metal layer includes a gate electrode GE of the pixel switching element PTFT and the first test electrode 122a connected to the first test signal line.

A gate insulating layer 130 is formed on the base mosquito plate 210 including the gate pattern. The gate insulating layer 130 may be formed of, for example, silicon nitride (SiNx).

A semiconductor layer 142 and an ohmic contact layer 144 are sequentially stacked on the base mosquito plate 210 on which the gate insulating layer 130 is formed and the semiconductor layer 142 and the ohmic contact layer 144 are sequentially stacked. Is patterned. The patterned semiconductor layer 142 and the ohmic contact layer 144 are formed on the gate insulating layer 130 on the gate electrode GE so as to overlap with the gate electrode GE.

Next, a source metal layer (not shown) is formed on the base mosquito plate 210, and the source metal layer is patterned to form a source pattern. The source pattern includes a source electrode SE of the pixel switching element PTFT, a drain electrode DE spaced apart from the source electrode SE, a first driving electrode 152a connected to the first driving signal line ). The source electrode SE and the drain electrode DE are formed on the patterned semiconductor layer 142 and the ohmic contact layer 144 and overlap with the gate electrode GE.

A passivation layer 160 is formed on the base mosquito plate 210 on which the source pattern is formed. The passivation layer 160 may be formed of, for example, silicon nitride (SiNx). An organic layer OL is formed on the base mosquito plate 210 on which the passivation layer 160 is formed.

7A and 7B, the organic layer OL and the passivation layer 160 on the drain electrode DE and the first signal electrode 152a are removed, and the organic layer OL and the passivation layer 160 on the first driving electrode 122a are removed. The organic layer OL, the passivation layer 160, and the gate insulating layer 130 are removed. Thus, one end of the drain electrode DE is exposed, and hole patterns are formed in which the first signal electrode 152a and the first driving electrode 122a are exposed.

7C, the organic layer OL includes a first thickness portion formed in the display region DA with a first thickness a and a second thickness portion formed in the peripheral region PA with a second thickness b. And may include a first thickness portion formed. The first thickness a of the first thickness portion may be greater than the second thickness b of the second thickness portion. For example, the first thickness portion may be formed by intercepting the light irradiated to the initial organic layer, which is initially applied, and the second thickness portion may be formed by partially blocking light emitted to the initial organic layer. The first thickness a may be the same as the thickness of the organic layer initially applied, and the second thickness b may be less than the thickness of the organic layer applied initially.

A transparent electrode layer (not shown) is formed on the base mosquito plate 210 including the organic layer OL having the hole patterns formed thereon. The transparent electrode layer may be formed of a transparent and conductive material. The transparent electrode layer may be formed of, for example, Indium Zinc Oxide (IZO) or Indium Tin Oxide (ITO).

7A and 8B, a pixel electrode (PE) electrically connected to the pixel switching element (PTFT) by patterning the transparent electrode layer and a pixel electrode PE formed on the outer area SA, A first signal pad electrode 172a contacting the first signal electrode 152a and a first driving pad electrode 174a contacting the first driving electrode 122a, The first electrostatic dispersion wiring 176a and the second electrostatic dispersion wiring 176b are formed. The first electrostatic dispersion wiring 176a and the second electrostatic dispersion wiring 176b may be formed in connection with the shorting bar STB in the process of forming the shorting bar STB without any additional process, And the burden on the process complexity can be minimized.

The first electrostatic dispersion wiring 176a is connected to the first signal pad electrode 172a and the first electrostatic dispersion wiring 176a connects the first signal pad electrode 172a to the shorting bar STB Connect. The second electrostatic dispersion wiring 176b is connected to the first driving pad electrode 174a and the second electrostatic dispersion wiring 176b is connected to the first driving pad electrode 176a and the shorting bar STB Connect. The first and second electrostatic dispersion wirings 176a and 176b are connected to the shorting bar STB arranged in parallel with the second cutting line CL2, for example.

In addition, the transparent electrode layer is patterned to form a voltage pad electrode (SPTE) electrically connected to the voltage electrode (SPE) and a third electrostatic dispersion wiring (179). The third electrostatic dispersion wiring 179 is connected to the voltage pad electrode SPTE and connects the voltage pad electrode SPTE to the shorting bar STB. The third electrostatic dispersion wiring 179 is connected to the shorting bar STB which is disposed in parallel with the first cutting line CL1 or overlapped with the first cutting line CL1, for example.

Referring to FIG. 8A, a common voltage line VCL electrically connected to the voltage electrode SPE is disposed in the peripheral area PA. The common voltage wiring VCL may be formed, for example, by patterning the gate metal layer. The organic layer OL is formed on the common voltage wiring VCL and the first electrostatic dispersion wiring 176a and the second electrostatic dispersion wiring 176b are formed on the organic layer OL.

6A and FIG. 5, in order to form the first driving pad portion DIP1 shown in FIG. 5, the gate insulating layer 130 is formed on the first driving electrode 122a, The gate insulating layer 130 is etched to form holes for exposing the first driving electrode 122a. The source metal layer is formed on the base mosquito plate 210 including the gate insulating layer 130 having the holes and the source metal layer is patterned to form a first source metal pattern 156a. The first driving electrode 122a and the first source metal pattern 156a are in contact with each other through the holes of the gate insulating layer 130 and the first source metal pattern 156a, The passivation layer 160 and the organic layer OL are sequentially stacked on the mother substrate 210. [ The organic layer OL and the passivation layer 160 on the first source metal pattern 156a are etched to expose the first source metal pattern 156a. The first driving pad electrode 174a and the first driving pad electrode 174a, which are in contact with the first source metal pattern 156a, are patterned by patterning the transparent electrode layer formed on the organic layer OL, The second electrostatic dispersion wiring 176b, and the shorting bar STB are formed.

Although not shown in the drawings, the manufacturing process of the mother substrate 200 for the display substrate further includes a step of forming an alignment film on the base mother substrate 210 on which the transparent electrode layer is formed. In order to form the alignment layer, for example, a polymer layer made of polyimide (PI) or the like is formed, and then the polymer layer is rubbed using a rubbing cloth to form can do. Alternatively, the alignment layer may be formed by printing on the base mosquito plate 200 without using a rubbing process using a printing machine having an alignment pattern.

In the rubbing process, the rubbing cloth 200 and the rubbing cloth 200 are electrically charged due to friction between the display substrate mother substrate 200 and the rubbing cloth. In addition, in the printing process, the display mother plate 200 and the printer are charged due to the friction between the display mother plate 200 and the printing press. Charges charged in the rubbing cloth or the printing machine are discharged to the mother substrate 200 for the display substrate and the charges are discharged to the first test pad electrode 172a and the first drive pad electrode 174a to the inside of the mother substrate 200 for the display substrate. Further, the charges are introduced into the mother substrate 200 through the voltage pad electrode SPTE. The first electrostatic dispersion wirings 176a, the second electrostatic dispersion wirings 176b and the third electrostatic dispersion wirings 179 transfer the electric charges flowing into the inside of the display mother board 200 to the shorting bar STB to the entire mother substrate 200 for the display substrate. Accordingly, it is possible to prevent static charges from being generated due to concentration of charges introduced from the outside at a specific portion of the display mother board 200.

Subsequently, the mother substrate 200 for the display substrate on which the alignment film is formed is bonded to a mother substrate (not shown) for a color filter substrate including color filters. The coupled mother substrate 200 for the display substrate and the mother substrate for the color filter substrate are cut in units of display cells.

Referring to FIG. 9, the display cell includes a display substrate 100 separated from the display mother substrate 200. The first electrostatic dispersion wiring 176a, the second electrostatic dispersion wiring 176b and the third electrostatic dispersion wiring 179 formed in the peripheral area PA are left on the display substrate 100. [

According to such a manufacturing method of a mother board for a display substrate and a display substrate, it is possible to connect the shorting bar to the test pad electrode of the test pad by forming the first electrostatic dispersion wiring in the peripheral area of the display area. The electric charges can be prevented from being generated by dispersing the charges flowing through the inspection pad portion over a large area through the shorting bar. In addition, by forming the organic layer in the peripheral region, it is possible to protect the inspection switching unit from static electricity and to minimize the interference between the inspection signals applied to the inspection pad unit and the common voltage signal transmitted through the common voltage wiring. Thus, damage to the mother substrate for the display substrate due to static electricity can be prevented, and reliability of the product and the manufacturing process can be improved.

It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined in the appended claims. It will be possible.

Claims (29)

Metal wires formed in a display region of the base substrate; A test switching unit formed in a peripheral region of the display region and transmitting an inspection signal to the metal wirings; A test pad unit electrically connected to the inspection switching unit to receive the inspection signal and including a test electrode and a test pad electrode electrically connected to the test electrode; A first electrostatic dispersion wiring extending from the test pad portion to one end of the base substrate; And And an inspection signal line connected to the switching unit for inspection and transmitting the inspection signal to the inspection switching unit and connected to the inspection electrode and extending from the inspection pad unit. delete delete 2. The semiconductor device according to claim 1, wherein the first electrostatic- Wherein the test pad electrode is formed of the same metal layer as the test pad electrode and is connected to the test pad electrode. The apparatus according to claim 1, further comprising: a driving signal wiring electrically connected to the switching unit for inspection to transmit a driving signal to the inspection switching unit; A driving pad portion formed at one end of the driving signal wiring and applying the driving signal; And Further comprising a second electrostatic dispersion wiring extending from the drive pad portion to one end of the base substrate. 6. The apparatus of claim 5, wherein the drive pad portion A driving electrode connected to the driving signal line, and a driving pad electrode electrically connected to the driving electrode. 7. The semiconductor device according to claim 6, wherein the second electrostatic- Wherein the driving pad electrode is formed of the same metal layer as the driving pad electrode and is connected to the driving pad electrode. 8. The semiconductor device according to claim 7, wherein the second electrostatic- Wherein the first electrostatic dispersion wiring is formed of the same metal layer as the first electrostatic dispersion wiring and is spaced apart from the first electrostatic dispersion wiring. The display substrate according to claim 1, further comprising an organic layer formed on the display region and the peripheral region to cover the metal lines and the switching unit for inspection. 10. The display substrate according to claim 9, wherein the first electrostatic dispersion wiring is formed on the organic layer in the peripheral region. 11. The display substrate according to claim 10, further comprising a common voltage line formed below the organic layer in the peripheral region and transmitting a common voltage signal to the display region. 12. The semiconductor device according to claim 11, further comprising: a voltage pad portion formed at one end of the common voltage wiring; And And a third electrostatic dispersion wiring connected to the voltage pad portion and formed on the organic layer and extending to an end portion of the base substrate. 13. The semiconductor device according to claim 12, wherein the voltage pad portion A voltage electrode electrically connected to the common voltage wiring; and a voltage pad electrode formed as a transparent electrode layer on the voltage electrode and connected to the third electrostatic dispersion wiring. A metal wiring formed in a display region of each array region of a base mother board including a plurality of array regions; a test signal wiring formed in a peripheral region of the display region and electrically connected to the metal wirings; Forming an array layer including a switching portion for inspection connected thereto; Forming a transparent electrode layer on the base mother substrate on which the array layer is formed; And A shorting bar formed between adjacent array regions by patterning the transparent electrode layer, a test pad electrode formed at one end of the test signal wiring, and a first electrostatic dispersion wiring connecting the test pad electrode and the shorting bar And forming an electrode pattern, The step of forming the array layer A driving signal line arranged in the peripheral region for transmitting a driving signal to the switching unit for inspection and a common voltage line arranged in the peripheral region for transmitting a common voltage signal to the display region, Method of manufacturing a mother board. delete 15. The method of claim 14, wherein forming the transparent electrode pattern comprises: A driving pad electrode formed at one end of the driving signal wiring, a second electrostatic dispersion wiring connected to the driving pad electrode and the shorting bar, a voltage pad electrode formed at one end of the common voltage wiring, And forming a third electrostatic dispersed interconnection. The method for manufacturing a mother substrate for a display substrate according to claim 1, 17. The method of claim 16, further comprising forming an organic layer formed in the display region between the array layer and the transparent electrode layer to cover the metal wirings and formed in the peripheral region to cover the inspection switching portion Wherein the base substrate is a glass substrate. 18. The organic electroluminescence display according to claim 17, wherein the first thickness of the organic layer formed in the display region is Wherein the second thickness of the organic layer formed in the peripheral region is thicker than the second thickness of the organic layer formed in the peripheral region. 15. The method of claim 14, wherein forming the array layer Forming a gate metal layer on the base mother substrate; Patterning the gate metal layer to form a gate pattern including the driving signal wiring, the driving electrode connected to the driving signal wiring, the common voltage wiring, and the voltage electrode connected to the common voltage wiring; Forming a source metal layer on the base mosquito plate comprising the gate pattern; And And patterning the source metal layer to form a source pattern including the inspection signal wiring and the inspection electrode connected to the inspection signal wiring. 20. The method of claim 19, wherein the metal wires of the array layer A gate wiring formed of the gate metal layer, and a data wiring formed of the source metal layer and intersecting the gate wiring. An inspection electrode formed in the peripheral region of the base substrate including a display region and a peripheral region surrounding the display region; A test pad electrode electrically connected to the test electrode and overlapping the test electrode; An inspection signal wiring connected to the inspection electrode; And an electrostatic dispersion wiring electrically connected to the inspection electrode in the peripheral region of the base substrate, Wherein the electrostatic dispersion wiring extends from the test electrode to one end of the base substrate and includes a layer different from the test electrode. The display substrate according to claim 21, wherein the inspection signal wiring and the electrostatic dispersion wiring extend in different directions. delete 22. The display substrate of claim 21, wherein the test pad electrode comprises a transparent material. 22. The display substrate of claim 21, wherein the electrostatic dispersion wiring is connected to the inspection pad electrode. 25. The display substrate of claim 24, wherein the test pad electrode comprises the same layer as the electrostatic dispersion interconnect. 22. The display substrate according to claim 21, further comprising an organic layer formed in the display region and the peripheral region to cover the inspection signal wiring. 22. The display substrate according to claim 21, wherein the inspection signal wiring is connected to the inspection switching unit and transmits the inspection signal to the inspection switching unit and extends from the inspection electrode. The display substrate according to claim 21, wherein the electrostatic dispersion wiring includes a transparent material.

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