KR101191191B1 - Digital broadcasting system and processing method - Google Patents

Abstract

The present invention relates to a digital broadcasting system, and in particular, the present invention groups a plurality of enhanced data packets having information, and multiplexes the group into a plurality of areas in transmitting the group by multiplexing the group with main data. The data type and processing method to be inserted are classified according to the characteristics of the layered area. In particular, according to the present invention, the E-VSB preprocessing process is applied differently according to the type of data inserted into the layered region and the type of enhanced data inputted in the group, thereby improving reception performance in an environment in which channel variation or noise is weak. have.

Enhanced Data, Tiers, and Known Data

Description

Digital broadcasting system and processing method

1 is a block diagram showing an embodiment of a digital broadcast transmission system according to the present invention;

FIG. 2 is a detailed block diagram illustrating an embodiment of the trellis encoder of FIG. 1. FIG.

3A and 3B are diagrams showing an example of data configuration before and after the data interleaver in the digital broadcast transmission system according to the present invention.

4 illustrates configuration examples of an enhanced data group according to the present invention.

5A and 5B are block diagrams illustrating embodiments of the E-VSB preprocessor of FIG. 1.

6A and 6B are block diagrams illustrating embodiments of the E-VSB block processing unit of the present invention.

7A and 7B are block diagrams illustrating other embodiments of the E-VSB block processing unit of the present invention.

8 is a block diagram showing an embodiment of a digital broadcast receiving system according to the present invention;

DESCRIPTION OF THE REFERENCE NUMERALS

101: E-VSB preprocessor 102: E-VSB packet formatter

103: packet multiplexer 104: data randomizer

105: scheduler

110: E-VSB post-processing unit

111: RS encoder / unstructured RS parity position holder insert

112: data interleaver 113: E-VSB block processing unit

501: block encoder 502: block interleaver

503: byte extension

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital communication system, and more particularly, to a digital broadcasting system and a processing method for modulating and transmitting and receiving a modulation in a VSB (Vestigial Side Band) scheme.

The 8T-VSB transmission system, adopted as a digital broadcasting standard in North America and Korea, is a system developed for transmission of MPEG video / audio data. However, with the rapid development of digital signal processing technology and the widespread use of the Internet, digital home appliances, computers, and the Internet are being integrated into one big framework. Therefore, in order to meet various needs of users, it is necessary to develop a system capable of transmitting various additional data in addition to video / audio data through a digital broadcasting channel.

Some users of supplementary data broadcasting are expected to use supplementary data broadcasting by using PC card or portable device with simple indoor antenna. In the room, signal strength is greatly reduced due to wall blocking and influence of nearby moving objects. Due to the effects of ghosts and noise caused by reflected waves, broadcast reception performance may deteriorate. However, unlike general video / audio data, the additional data transmission should have a lower error rate. In the case of video / audio data, errors that the human eye and ears cannot detect are not a problem, while in the case of additional data (eg program executables, stock information, etc.), a bit error may cause serious problems. It can cause problems. therefore There is a need to develop a system that is more resistant to ghosting and noise in the channel.

The transmission of additional data will usually be done in a time division manner over the same channel as the MPEG video / sound. Since the beginning of digital broadcasting, however, ATSC VSB digital broadcasting receivers that receive only MPEG video / audio have been widely used in the market. Therefore, additional data transmitted on the same channel as MPEG video / audio should not affect the existing ATSC VSB-only receivers that have been used in the market. Such a situation is defined as ATSC VSB compatible, and the additional data broadcasting system should be compatible with the ATSC VSB system. The additional data may also be referred to as enhanced data or E-VSB data.

In addition, in a poor channel environment, the reception performance of the conventional ATSC VSB receiving system may be degraded. Especially in the case of portable and mobile receivers, robustness against channel changes and noise is required.

Accordingly, an object of the present invention is to provide a new digital broadcasting system and processing method suitable for additional data transmission and resistant to noise.

Another object of the present invention is to provide a digital broadcasting system and a processing method for improving the reception performance of a receiver by additionally encoding, layering, and transmitting the data according to the importance of enhanced data.

It is still another object of the present invention to provide a digital broadcasting system and a processing method for improving reception performance of a receiver by layering known data and enhanced data known from the transmitting / receiving side and multiplexing the main data. .

In order to achieve the above object, the digital broadcast processing method according to the present invention,

(a) further encoding and byte-extending the enhanced data which is divided and input according to a preset condition;

(b) receiving the enhanced data output by expanding the byte, grouping them in successive multiple enhanced data packet units, dividing the enhanced data group into a plurality of areas, and then assigning the enhanced data group to the corresponding area according to the characteristics of each area. Allocating the input enhanced data;

(c) multiplexing the enhanced data and the main data in the enhanced data group on a packet basis and then interleaving and outputting the data;

(d) performing additional encoding only on the enhanced data in the enhanced data packet output through the data interleaving, and not performing additional encoding on the remaining data; And

and (e) trellis encoding and transmitting the enhanced data output in step (d).

In step (a), additional encoding is performed by using any one of error correction codes including block encoding, and block interleaving is selectively performed.

In the step (b), the enhanced data group is divided into first, second, and third regions in a hierarchical manner, wherein the second region is a series of enhanced data in the enhanced data group based on the output order after data interleaving. At least a part or the whole of the region continuously output is included, and the first region is divided into a portion that is output before the second region in the enhanced data group, and the third region is a portion that is output later. It features.

In the step (b), when the known data known from the transmitting / receiving side is inserted into the enhanced data, the known data position and the initialization data position for trellis coding according to the characteristics of each region in the enhanced data group. RS parity position is determined.

The step (d) may include converting an input enhanced data byte into a symbol, removing null bits inserted for byte expansion, and performing additional encoding only on valid data bits at a preset coding rate; And converting the symbol data encoded in the step into a byte and outputting the byte.

Step (d) may include converting an input enhanced data byte into bits, removing null bits inserted for byte expansion, and performing first encoding on a valid data bit only at a predetermined coding rate; Converting the first coded data bit into a symbol and performing a second encoding at a preset coding rate; And converting the second coded symbol data into a byte and outputting the byte.

Step (e) may include performing data interleaving after performing unsystematic RS encoding on an enhanced data packet input through data deinterleaving and RS byte elimination; Initializing the data interleaved and outputting the known data and initializing the memory of the trellis encoder when the first known data sequence is continuous; And calculating truncated RS parity using the output data of the data interleaver and data for memory initialization, and performing trellis encoding by substituting the unstructured RS parity.

In accordance with another aspect of the present invention, there is provided a digital broadcast transmission system comprising: an E-VSB preprocessor configured to additionally encode and byte-enhanced enhanced data according to preset conditions and output the encoded data; After receiving the enhanced data output by extending the byte, grouping the data into a plurality of consecutive enhanced data packet units, dividing the enhanced data group into a plurality of areas or more, and inputting the data into the corresponding area according to the characteristics of each area. An E-VSB packet formatter for allocating enhanced data; An RS parity position holder inserting and interleaving unit inserting a plurality of RS parity position holders into an enhanced data packet output from the E-VSB packet formatter to perform data interleaving; And an E-VSB block processor for performing data deinterleaving and RS parity position holder removal after performing additional encoding only in a block coding scheme when the data interleaved data is enhanced data. do.

In accordance with another aspect of the present invention, there is provided a digital broadcast transmission system comprising: an unstructured RS encoder and data interleaver for performing trellis encoding after performing unsystematic RS encoding and performing data interleaving on an output of the E-VSB block processor; A trellis encoding unit capable of initializing the output data of the unstructured RS encoder and the data interleaver and known data, and performing trellis encoding after the memory initialization is performed; An unstructured RS encoder that recalculates an unstructured RS parity from an output of the unstructured RS encoder and a data interleaver and an output of the trellis encoder and replaces the unstructured RS parity input to the trellis encoder; And a transmitter for inserting a sync symbol into an output of the trellis encoder and transmitting the modulation symbol through a modulation process.

The E-VSB block processor includes: a symbol encoder which converts an input enhanced data byte into a symbol, removes a null bit inserted for byte extension, and encodes only a valid data bit at a predetermined encoding rate; A buffer for delaying and outputting input main data for a predetermined time; And a multiplexer for selectively outputting one of the output data of the symbol encoder and the output data of the buffer.

The E-VSB block processor includes: an external encoder which converts an input enhanced data byte into bits, removes null bits inserted for byte expansion, and encodes only valid data bits at a predetermined encoding rate; An internal encoder that converts the data bits output from the external encoder into symbols and then performs encoding at a predetermined coding rate and then converts the data bits into byte units; A buffer for delaying and outputting input main data for a predetermined time; And a multiplexer for selectively outputting one of the output data of the internal encoder and the output data of the buffer.

According to an aspect of the present invention, there is provided a digital broadcast reception system, comprising: an E-VSB block decoder configured to perform soft decision decoding and output a soft decision value if the received data is enhanced data; A de-randomizer for outputting the soft-determined enhanced data as it is or inverted according to a pseudo random bit value used for randomization on a transmitting side; And an E-VSB data processing unit that separates the enhanced data input according to the type of the enhanced data output from the de-randomizer, removes null data used for byte expansion, and performs additional decoding. It is characterized by.

Other objects, features and advantages of the present invention will become apparent from the following detailed description of embodiments taken in conjunction with the accompanying drawings.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention that can specifically realize the above object will be described. At this time, the configuration and operation of the present invention shown in the drawings and described by it will be described as at least one embodiment, by which the technical spirit of the present invention and its core configuration and operation is not limited.

In addition, the terminology used in the present invention is a general term that is currently widely used as much as possible, but in some cases, the term is arbitrarily selected by the applicant. It is intended that the present invention be understood as the meaning of the term rather than the name.

The present invention is to classify enhanced data having information according to a predetermined condition, and to perform additional encoding on each of the divided enhanced data separately or collectively. There may be various conditions for classifying the enhanced data, and in one embodiment, the enhanced data may be classified according to importance.

The present invention also provides a method for grouping a plurality of enhanced data packets, multiplexing the group with main data, and layering the group into a plurality of regions, and inserting the enhanced data type according to the characteristics of the layered region, It is to distinguish treatment methods.

According to the present invention, the enhanced data may be classified into N types from enhanced data having a high priority to enhanced data having a low priority. For convenience of explanation, the present invention will be described as an example of dividing the enhanced data into two types, that is, high priority enhanced data and low priority enhanced data. This is only one embodiment and the present invention will not be limited to the examples given above.

1 is a diagram illustrating an embodiment of a digital broadcast transmission system of the present invention for receiving an enhanced data input as described above and performing additional encoding separately or integrally and then multiplexing and transmitting the known data and main data. The block diagram shown.

The digital broadcast transmission system of FIG. 1 includes an E-VSB preprocessor 101, an E-VSB packet formatter 102, a packet multiplexer 103, a data randomizer 104, a scheduler 105, and an E-VSB postprocessor. 110, RS encoder / Non-systematic RS encoder 121, data interleaver 122, parity substituent 123, unstructured RS encoder 124, trellis encoder 125, a frame multiplexer 126, and a transmitter 130.

In the present invention configured as described above, the E-VSB preprocessor 101 receives the enhanced data and performs preprocessing such as additional block encoding, block interleaving, byte expansion through null data insertion, etc., and then the E-VSB packet formatter 102. )

At this time, if the input enhanced data is the aforementioned high priority enhanced data and low priority enhanced data, the E-VSB preprocessor 101 separately performs preprocessing such as additional block encoding, block interleaving, byte expansion, and the like. After that, it is output to the E-VSB packet formatter 102 while maintaining the state classified by importance. The detailed operation of the E-VSB preprocessor 101 will be described later.

The E-VSB packet formatter 102 collects and groupes a plurality of enhanced data pre-processed by the control of the scheduler 105 in packet units. In this case, the packet is an enhanced data packet of 188 bytes in which a 4-byte MPEG header is added, and the enhanced data packet may consist only of enhanced data or only known data (or known data location). For example, the enhanced data and the known data may be multiplexed. Details related to the rules for forming an enhanced data group in the E-VSB packet formatter 102 will be described later.

The output of the E-VSB packet formatter 102 is input to the packet multiplexer 103. The packet multiplexer 103 time-division-multiplexes the main data packet and the enhanced data group by a transport stream (TS) packet unit under the control of the scheduler 105 and outputs the data to the data randomizer 104. .

That is, the scheduler 105 generates and outputs a control signal to multiplex the enhanced data and the known data (or the known data position holder) in the E-VSB packet formatter 102, and also generates the packet multiplexer 103. ) Outputs a control signal so that the main data packet and the enhanced data group can be multiplexed on a packet basis.

The data randomizer 104 discards the MPEG sync bytes and randomly generates the remaining 187 bytes using pseudo random bytes generated therein and outputs them to the E-VSB post-processing unit 110.

The E-VSB post processor 110 is an RS encoder / unstructured RS parity position holder inserter 111, a data interleaver 112, an E-VSB block processor 113, a data deinterleaver 114, and an RS byte remover. And 115.

The RS encoder / unstructured RS parity position holder inserter 111 of the E-VSB post-processing unit 110 performs systematic RS encoding if the randomized data is the main data packet and unstructured RS if the enhanced data packet is an RS. Non-systematic RS parity Holder insertion is performed. That is, the RS encoder / unstructured RS parity position holder inserter 111 performs systematic RS encoding in the same manner as the existing ATSC VSB system when the 187 byte packet outputted from the data randomizer 104 is the main data packet. 20 bytes of parity bytes are added after 187 bytes of data, and then output to the data interleaver 112.

On the other hand, the RS encoder / unstructured RS parity position holder inserting unit 111 is 20 bytes in the packet for unstructured RS encoding to be performed when the 187 bytes of the packet output from the data randomizer 104 is an enhanced data packet. An RS parity position holder including null data is inserted, and the bytes of the enhanced data packet are inserted into the remaining 187 byte positions and output to the data interleaver 112.

The data interleaver 112 performs data interleaving on the output of the RS encoder / unstructured RS parity position holder inserter 111 and outputs the data to the E-VSB block processor 113.

The E-VSB block processing unit 113 performs additional encoding only on the enhanced data output from the data interleaver 112, and then outputs the data to the data deinterleaver 114, and the data deinterleaver 114 outputs the data deinterleaver 114. Data deinterleaving is performed on the input data in the reverse process of the data interleaver 112 and then output to the RS byte remover 115. An additional encoding process of the E-VSB block processing unit 113 will be described later in detail.

The RS byte remover 115 removes 20 bytes of parity added by the RS encoder / unstructured RS parity position holder inserter 111. In this case, if the input data is the main data packet, the last 20 bytes of the 207 bytes are removed. In the case of the enhanced data packet, the parity position holders of 20 bytes inserted to perform unsystematic RS encoding are removed. This is for calculating the parity again since the original data has been changed by the E-VSB block processor 113 in the case of enhanced data.

The output of the RS byte remover 115 is input to an RS encoder / unstructured RS encoder 121.

The RS encoder / unstructured RS encoder 121 adds 20 bytes of parity to the 187 byte packet output from the RS byte remover 115 and outputs the parity of 20 bytes to the data interleaver 122. In this case, the RS encoder / unstructured RS encoder 121 performs systematic RS encoding in the same way as the existing ATSC VSB system when the input data is a main data packet, and adds 20 bytes of parity bytes after 187 bytes of data. In the case of an enhanced data packet, 20 parity byte positions are determined in a packet, and 20-byte RS parity obtained by performing unsystematic RS encoding is inserted into the determined parity byte position.

The data interleaver 122 is a convolutional interleaver in bytes, and the same interleaving rule as that of the data interleaver 112 is applied.

The output of the data interleaver 122 is output to the parity substituent 123 and the unstructured RS encoder 124.

On the other hand, in order to make the output data of the trellis encoder 125 located at the rear end of the parity substituent 123 into known data defined on the transmitting / receiving side, the memory in the trellis encoder 125 needs to be initialized first. . In this case, it is necessary to generate and replace the initialization data so that the input of the trellis encoder 125 is initialized according to the state of the memory. In addition, it is necessary to recalculate the RS parity affected by the changed initialization data and replace it with the RS parity output from the data interleaver 122.

Accordingly, the unstructured RS encoder 124 receives a pre-computed unstructured RS parity for an enhanced packet including data to be replaced with initialization data from the data interleaver 122, and the trellis encoder 125. It receives the initialization data from, calculates a new unstructured RS parity and outputs it to the parity substituent 123.

The parity replacer 123 selects RS parity and data output from the data interleaver 122 when the main data packet or the enhanced data packet including the initialization byte to be replaced is input, and the trellis encoder 125. Will output On the other hand, an enhanced data packet including a parity byte to be substituted is input, and data selects an output of the data interleaver 122, and RS parity selects an output of an unstructured RS encoder 124 so that the trellis encoder Output to (125).

The trellis encoder 125 converts the data of the byte unit into the symbol unit, performs 12-way interleaving, trellis-encodes, and outputs the trellis to the frame multiplexer 126. The detailed configuration of the trellis encoder 125 will be described later.

The frame multiplexer 126 inserts field sync and segment sync into the output of the trellis encoder 125 and outputs the field sync and segment sync to the transmitter 130. The transmitter 130 includes a pilot inserter 131, a VSB modulator 132, and an RF converter 133, and thus the detailed description thereof will be omitted.

Trellis  reset

FIG. 2 shows an embodiment of a detailed block diagram of an initializeable trellis encoder 125.

The initializeable trellis encoder 125 includes a multiplexer 202, a trellis encoder 203, and a trellis for selecting an input of a byte-symbol converter 201, a trellis encoder 203. And a symbol-byte converter 204 for converting the symbol data for initializing the encoder 203 into a byte unit and outputting the symbol data to the unstructured RS encoder 124.

In FIG. 2 configured as described above, the byte-symbol converter 201 of the initializeable trellis encoder receives the output data of the parity substituent 123 in byte units, converts them into symbol units, and performs 12-way interleaving. To the multiplexer 202.

In the general case, the output of the byte-symbol converter 201 is selected by the multiplexer 202 and output to the trellis encoder 203 as it is. However, if the interleaved data is known data and the beginning of the known data string to which the known data is continuously input, the trellis encoder 203 needs to be initialized. This is because the trellis encoder 203 has a memory and the current output is influenced not only by the present but also by the past input, so that the memory in the current trellis encoder 203 is initialized to a constant value in order to output a predetermined signal at some point in time. This is because the process is necessary.

When memory initialization of the trellis encoder 203 is required, a part of the known data should be replaced with initialization data and output to the trellis encoder 203. Then, the memory in the trellis encoder 203 is initialized to the value determined by the initialization data, and the output of the trellis encoder 203 after that point is encoded known data of a desired form on the transmitting / receiving side. Can be

The trellis encoder 203 may generate an input symbol value of the trellis encoder 203 for initialization according to its memory value. The generated symbol value is output to the multiplexer 202 and the symbol-byte converter 204.

The multiplexer 202 is interleaved, converted into a symbol, and when the input data is the beginning of a known data sequence, the multiplexer 202 selects an initialization symbol output from the trellis encoder 203 instead of an input symbol, and thus the trellis encoder 203. Otherwise, the symbol output from the byte-symbol converter 201 is selected and output to the trellis encoder 203.

The symbol-byte converter 204 receives an initialization symbol output from the trellis encoder 203 and deinterleaves 12-way, converts the symbol into bytes, and outputs the RS to the unstructured RS encoder 124 to output the RS. Parity can be recalculated.

E- VSB  Pretreatment

3 shows data relationships before and after the data interleavers 112 and 122. 3A, data input to the data interleaver is input from top to bottom and left to right in the order of packets. The data output from the data interleaver is output from top to bottom and from left to right with reference to FIG. 3B. That is, the output data of the data interleaver is composed of A first output in FIG. 3A, then mixed with B and C, then output with D and E mixed, and finally F output in FIG. 3B. .

When a plurality of enhanced data packets are grouped and transmitted, it may be assumed that 104 packets of A, B, C, and D are transmitted in one enhanced data group in FIG. 3A. In this case, when the data configuration is based on the data interleaver output of FIG. 3B, the enhanced data of the B and C regions may be continuously output, but the enhanced data of the A or D region is mixed with the main data and output. .

According to the present invention, an enhanced data group is layered into three parts, which are referred to as a head, a body, and a tail area. That is, after the data interleaving, the first part of the enhanced data group is called the head, the middle part is the body, and the last part is called the tail. Herein, the body part is allocated such that at least a part of the area where the enhanced data in the enhanced data group is continuously output is included or entirely included, based on after data interleaving. In this case, the body portion may include an area in which enhanced data is discontinuously output.

FIG. 4 is a diagram illustrating an example of collecting a certain number of enhanced data packets to form a group and dividing the group into head, body, and tail regions.

In FIG. 4, the left figure shows the data configuration before data interleaving, and the right figure shows the data configuration after data interleaving.

4 illustrates a case in which 104 packets constitute an enhanced data group. This is an example of configuring an enhanced data group with multiples of 52 packets since the data interleaver operates periodically in units of 52 packets.

In addition, FIG. 4 shows a body region having a rectangular shape when viewing the data structure at the data interleaver output terminal. That is, the body region is an example in which the head, body, and tail regions are set in the enhanced data group so that the body region is a region composed entirely of enhanced data without being mixed with the main data region.

Dividing the enhanced data group into three parts is for different purposes. That is, in FIG. 4, the region corresponding to the body is composed of enhanced data without interference of the main data in the middle, and thus shows a more robust reception performance. The enhanced data of the head and tail regions is the main data and the interleaver output. This is because the reception performance is lower than that of the body area because the order is mixed between.

In addition, in the case of applying a system for inserting and transmitting known data into the enhanced data, when the long known data is periodically inserted into the enhanced data periodically, the enhanced data is the main data based on the order of the data interleaver output terminal. It is possible to insert in areas not mixed with. That is, it is possible to periodically insert known data of a predetermined length into the body region of FIG. 4. However, it is difficult to periodically insert known data into the head and tail regions, and it is impossible to insert long known data continuously. At this time, at the beginning of the known data sequence, initialization data for initializing the memory in the trellis encoder 203 is allocated.

When the enhanced data group is divided into a head, a body, and a tail area, different services may be allocated according to each area. If it is assumed that the enhanced data is divided into a high priority enhanced data and a low priority enhanced data, the high priority enhanced data and the low priority enhanced are respectively appropriately selected among the head, body, and tail areas of the enhanced data group. Allocate data. For example, high priority enhanced data may be allocated to the body region, and low priority enhanced data may be allocated to the head and tail regions.

Therefore, when the enhanced data is input, the E-VSB preprocessor 101 adds the enhanced data to the input enhanced data in consideration of the input enhanced data type and the data type allocated to each area of the enhanced data group. Preprocessing such as block encoding, block interleaving, byte expansion, or the like, may be performed, or preprocessing may be performed considering only one of a data type and an input data type allocated to each region in an enhanced data group.

5 is a detailed block diagram illustrating embodiments of the E-VSB preprocessor 101. 5A illustrates a case in which E-VSB preprocessing is integrally performed regardless of the type of enhanced data input, and FIG. 5B illustrates a case in which E-VSB preprocessing is separately performed according to the type of enhanced data input.

In the case of FIG. 5A, the E-VSB preprocessor 101 includes one block encoder 501, a block interleaver 502, and a byte expansion unit 503. It is composed.

The block encoder 501 encodes the input enhanced data using a block coding scheme. For example, the block coder may use a block code such as an RS coder, a convolutional coder, or a low density parity check (LDPC) coder. The block coder may use the block interleaver 502 according to an implementation purpose. Can be used optionally.

The method of applying the block interleaving is related to the overall system performance, and any method such as random interleaving can be used.

In this case, in order to perform encoding in block units in the block encoder 501 and block interleaving in the block interleaver 502, the size of a block must be determined.

According to an embodiment of the present invention, the number of bits of the enhanced data included in the body region of the enhanced data group is set to a size of one block, and the number of bits of the enhanced data included in the head and tail regions is collected and one block is collected. If you set the size of, the size of the two blocks are almost the same size. This can be seen in FIG. 4. The block size is one embodiment, and any block size is possible when the beginning and the end of the block are determined such that the enhanced data has a finite length, so the present invention will not be limited to the above-described embodiment.

After being encoded by the block coding scheme, the block interleaved data is byte extended by null bit insertion in the byte expander 503. The byte expander 503 may expand one byte to two bytes, expand to four bytes, or expand to another byte through null bit insertion and repetition in one embodiment.

In the case of FIG. 5B, the E-VSB preprocessor 101 includes a block encoder, a block interleaver, and a byte extender by the number N of the enhanced data types to individually perform the E-VSB preprocessing. In this case, different block encoding, block interleaving, and byte expansion may be performed according to the enhanced data type.

As in the embodiment of the present invention, if the enhanced data is divided into high priority enhanced data and low priority enhanced data, the E-VSB preprocessor 101 includes at least two block encoders, a block interleaver, and a byte extension unit. do.

In FIG. 5B, it is assumed that byte expansion is performed by encoding high priority enhanced data at a first encoder indicated by 510 and byte extension is performed by encoding low priority enhanced data at a second encoder denoted by 5N0. Further, assume that the high priority enhanced data is allocated to the body region in the enhanced data group in the E-VSB packet formatter 102 and the low priority enhanced data is allocated to the head and tail regions.

In this case, the actual data rate to be transmitted can be increased by setting the coding rate of the block encoder 511 in the first encoder 510 higher than the coding rate of the block encoder 5N1 in the second encoder 5N0. This is because good reception performance is expected in the body region and relatively low reception performance is expected in the head and tail regions.

On the contrary, since the data allocated to the body region is important data, the coding rate of the block encoder 511 in the first encoder 510 is set lower than that of the block encoder 5N1 in the second encoder 5N0. As a result, the data rate is lowered, but it may also have a high error correction capability.

In one embodiment, the block encoder 511 in the first encoder 510 uses a 9/10 LDPC having a code rate of 9/10, and the block encoder 5N1 in the second encoder 5N0 is 1. 1/2 LPDC, 1/2 convolutional coder, etc. having a coding rate of / 2 can be used. On the contrary, the block encoder 511 of the first encoder 510 uses a 1/2 LPDC, a 1/2 convolutional encoder, etc. having a coding rate of 1/2, and uses a block encoder of the second encoder 5N0 ( 5N1) can use 9/10 LDPC etc. which have a coding rate of 9/10. These are merely embodiments, and since each block encoder can use encoders having different coding rates, the present invention will not be limited to the above described embodiments.

After block coding and block interleaving are used for each type of enhanced data in each encoder, byte expansion is performed in each byte extension unit. In this case, the number of bytes to be extended may be the same or different according to the type of the enhanced data input and the type of data allocated to each area in the enhanced data group. For example, 4-byte extension may be performed on the high priority enhanced data, and 2-byte extension may be performed on the low priority enhanced data. Or vice versa or the same ratio. This is a designer's option and will not be limited to the above examples in the present invention.

The enhanced data byte-extended by each byte expansion unit is input to the E-VSB packet formatter 102. That is, according to the enhanced data type, the E-VSB preprocessed enhanced data is classified and input to the E-VSB packet formatter 102.

The E-VSB packet formatter 102 allocates the input enhanced data to the appropriate areas among the head, body, and tail areas in the enhanced group. For example, high priority enhanced data may be allocated to the body region, and low priority enhanced data may be allocated to the head and tail regions.

That is, the E-VSB packet formatter 102 forms an enhanced data group so that the enhanced data may come to a predetermined position of the head, body, and tail region after data interleaving according to the enhanced data type. The predetermined known data (or known data position holder) is inserted at a specific position in the enhanced data group according to a predetermined rule and then output to the packet multiplexer 103 in MPEG packet units of 188 bytes.

E- VSB  Block processing

Meanwhile, the E-VSB block processor 113 performs additional encoding only on the enhanced data and outputs the encoded data. That is, the E-VSB block processing unit 113 inserts an MPEG header byte or an RS encoder / unstructured RS parity position holder added when the output of the data interleaver 112 is main data and is added by the E-VSB packet formatter 102. In the unit 111, the RS parity or the RS parity position holder byte added to the enhanced data packet is output as it is without changing the data.

The known data is also output without additional encoding as the main data, but the processing method may be different.

For example, the E-VSB packet formatter 102 inserts a known data position holder, and the E-VSB block processor 113 generates the known data position holder in the E-VSB block processor instead of the known data position holder. There is a method of outputting a known data and a method of inserting known data in the E-VSB packet formatter 102 and outputting the same as it is in the E-VSB block processor 113 without changing data.

The former method is shown in Figs. 6A and 7A and the latter method is shown in Figs. 6B and 7B.

First, referring to FIG. 6A, the E-VSB block processor 113 includes a demultiplexer 610, a buffer 620, an enhanced encoder 630, and a multiplexer 640.

The enhanced encoder 630 includes a byte-to-symbol converter 631, a symbol encoder 632, a symbol interleaver 633, and a symbol-byte converter 634.

In FIG. 6A, the demultiplexer 610 outputs to the buffer 620 when the input data is main data and to the enhanced encoder 630 when the input data is enhanced data.

The buffer 620 delays main data for a predetermined time and outputs the delayed main data to the multiplexer 640. In other words, when the data input to the demultiplexer 610 is main data, the buffer 620 is used to compensate by delaying the difference of the time point generated in the process of the enhanced data through the additional encoding. The main data whose viewpoint difference is adjusted by the buffer 620 is transferred to the data deinterleaver 114 through the multiplexer 640.

In the case of known data, the E-VSB packet formatter 102 inserts a known data position holder, and the multiplexer 640 of the E-VSB block processor 113 replaces the known data position holder in place of the known data position holder. By selectively outputting the known data (training sequence, T) output at 635, it is output without additional encoding.

Meanwhile, the byte-symbol converter 631 of the enhanced encoder 630 converts the enhanced data byte into four symbols and outputs the converted symbols to the symbol encoder 632. The symbol encoder 632 is an encoder that encodes and outputs the enhanced data M bits into N bits. For example, if one bit of the enhanced data is encoded and output into 2 bits, M becomes 1 and N becomes 2.

As an example, assume that the E-VSB preprocessor 101 extends one byte of enhanced data into two bytes by inserting a null bit between bits. Then, the byte-symbol converter 631 removes the null bits extended by the E-VSB preprocessor 101 from the input bytes, constructs a symbol with only valid data bits, and outputs the symbol to the symbol encoder 632.

For example, the symbol encoder 632 encodes a symbol input having one bit of valid data to output two bits of a symbol, and the symbol interleaver 633 receives the output of the symbol encoder 632 to block interleaving in symbol units. Will be performed.

The method of applying the block interleaving is related to the overall system performance, and any method such as random interleaving can be used.

In this case, in order to perform encoding on a block basis in the symbol encoder 632 and block interleaving in the symbol interleaver 633, the size of a block must be determined. Herein, the size of the block may be set based on the trellis initialization part or may be set based on the layered area in the group.

The symbol-byte converter 634 converts the output symbols of the symbol interleaver 633 into bytes and outputs them to the multiplexer 640.

The multiplexer 640 selects main data output from the buffer 620 if the input data is main data, and selects enhanced data encoded and output from the enhanced encoder 630 if the input data is main data. In the case of the position holder, the known data output from the known data generator 635 is selected and output to the data deinterleaver 114.

FIG. 6B is almost similar to FIG. 6A, with the difference being the known data processing portion. That is, in case of FIG. 6B, if the input data is known data, the demultiplexer 660 outputs to the buffer 670, delays a predetermined time, and outputs the data to the data deinterleaver 114 through the multiplexer 680. 6 is the same as FIG. 6A described above, and thus a detailed description thereof will be omitted.

In this case, it is assumed that the known data has already been inserted into the enhanced data packet in the E-VSB packet formatter 102.

6A and 6B, the symbol encoders 632 and 682 are 1/2 encoders.

The 1/2 encoder may be any encoder that receives one bit and outputs two bits, for example, 1/2 systematic convolutional encoder, 1/2 unsystematic convolutional encoder, 1/2 repetitive encoder, 1 / 2 an inverting encoder can be used.

In addition, the 1/2 encoder may use a 1/2 convolutional encoder using a block code or a 1/2 Low Density Parity Check (LDPC) encoder, and the like. The symbol interleaver 633 and 683 may be Can be used selectively. The symbol interleavers 633 and 683 have block interleaving in symbol units.

Here, the 1/2 encoder may be applied to a wider variety of applications, and thus the present invention is not limited thereto.

7A and 7B illustrate still another embodiment of the E-VSB block processor 113.

First, referring to FIG. 7A, the E-VSB block processor 113 includes a demultiplexer 710, a buffer 720, an enhanced encoder 730, and a multiplexer 740.

The enhanced encoder 730 includes a byte-to-bit converter 731, an external encoder 732, a bit-symbol converter 733, an internal encoder 734, a symbol interleaver 735, and a symbol-byte converter 736. It is configured to include.

The external encoder 732 is an encoder that encodes and outputs an enhanced data O bit into P bits. For example, O is 1 and P is 2 when an enhanced data bit is encoded into 2 bits and output. The internal encoder 734 is an encoder that encodes and outputs the input data Q bits into R bits. For example, Q is 1 and R is 2 if the enhanced data bit is encoded into 2 bits and output.

In FIG. 7A, the demultiplexer 710 outputs to the buffer 720 when the input data is main data and to the enhanced encoder 730 when the input data is the enhanced data.

The buffer 720 delays main data for a predetermined time and outputs the delayed main data to the multiplexer 740. That is, when the data input to the demultiplexer 710 is main data, the buffer 720 may compensate for the delayed time difference of the enhanced data generated by the enhanced encoder 730 by delaying the time difference. Is used. The main data whose viewpoint difference is adjusted by the buffer 720 is transferred to the data deinterleaver 114 through the multiplexer 740.

In the case of known data, the E-VSB packet formatter 102 inserts a known data position holder, and the multiplexer 740 of the E-VSB block processor 113 replaces the known data position holder with the known data generator. By selectively outputting the known data (training sequence, T) output from 737, it is output without additional encoding.

Meanwhile, the byte-bit converter 731 of the enhanced encoder 730 converts the input enhanced byte into a string of bits. Of these bits, the null bits in the byte extended by the E-VSB preprocessor 101 are removed, and only the actual valid data bits are output to the external encoder 732. The external encoder 732 receives and encodes one or more valid bits and outputs one or more bits to the bit-symbol converter 733. The bit-symbol converter 733 converts the input two bits into a single symbol and outputs it to the internal encoder 734. The internal encoder 734 encodes an input symbol and outputs the same to the symbol interleaver 735 through the same process as the symbol encoders 632 and 682 of FIGS. 6A and 6B.

The symbol interleaver 735 receives the output of the internal encoder 734 and performs block interleaving on a symbol basis. The method of applying the block interleaving is related to the overall system performance, and any method such as random interleaving can be used.

In this case, in order to perform encoding in block units in the internal encoder 734 and block interleaving in symbol units in the symbol interleaver 735, the size of a block must be determined. Herein, the size of the block may be set based on the trellis initialization part or may be set based on the layered area in the group.

The symbol-byte converter 736 converts the output symbols of the symbol interleaver 735 into bytes and outputs them to the multiplexer 740.

The multiplexer 740 selects main data output from the buffer 720 when the input data is main data, selects enhanced data encoded and output from the enhanced encoder 730 when the input data is main data, and known data. In the case of the position holder, a training sequence output from the known data generator 737 is selected and output to the data deinterleaver 114.

FIG. 7B is almost similar to FIG. 7A, with the difference being the known data processing portion. That is, in case of FIG. 7B, if the input data is known data, the demultiplexer 760 outputs to the buffer 770 and delays a predetermined time, and then outputs the data to the data deinterleaver 114 through the multiplexer 780. 7 is the same as FIG. 7A described above, and thus a detailed description thereof will be omitted.

In this case, it is assumed that the known data has already been inserted into the enhanced data packet in the E-VSB packet formatter 102.

7A and 7B, the external and internal encoders 732, 734, 782 and 784 are 1/2 encoders.

The 1/2 encoder may be any encoder that receives one bit and outputs two bits, for example, 1/2 systematic convolutional encoder, 1/2 unsystematic convolutional encoder, 1/2 repetitive encoder, 1 / 2 an inverting encoder can be used.

In addition, the 1/2 encoder may use a 1/2 convolutional encoder using a block code or a 1/2 Low Density Parity Check (LDPC) encoder, and the like, and block interleaving may be performed on a symbol basis according to an implementation purpose. The use of the symbol interleaver to be performed can be selectively used.

Here, the 1/2 encoder may be applied to a wider variety of applications, and thus the present invention is not limited thereto.

For example, when the external and internal encoders are each encoders having a 1/2 code rate, and the external encoder is connected to the internal encoder, the overall code rate of the enhanced encoder is 1/4. To this end, the E-VSB preprocessor 101 must go through a byte expansion process of inserting three bits of null bits for one bit.

In addition, when byte expansion is performed by inserting null 3 bits into the valid 1 bit, only the valid 1 bit is encoded into 2 bits in an external encoder, one bit of which is in place of the original valid bit, and the other of the null bits. Converts to a symbol by placing it in the second bit position. Then, one symbol is composed of valid bits and null bits, and only the valid bits are encoded as 2 bits in the internal encoder. Then repeating the process of placing one bit in the original significant bit position and the other in the null bit position results in a quarter-code rate overall.

The above-described external and internal encoding processes are just one embodiment, and the encoding method, the code rate, and the location of the encoded data may vary according to the encoder designer, and thus the present invention will not be limited to the above-described embodiments.

FIG. 8 is a block diagram illustrating an embodiment of a digital broadcast reception system for receiving, demodulating, and equalizing data transmitted from a digital broadcast transmission system and restoring original data.

The digital broadcast receiving system of FIG. 8 includes a tuner 801, a demodulator 802, an equalizer 803, a known data detection and generation unit 804, an E-VSB block decoder 805, and a data deinterleaver 806. And an RS decoder / unstructured RS parity removal unit 807 and a derandomizer 808.

In addition, the digital broadcast receiving system includes a main data packet remover 809, an E-VSB packet deformatter 810, and an E-VSB data processor 811.

That is, the tuner 801 tunes the frequency of a specific channel, down-converts the intermediate frequency (IF) signal, and outputs the demodulator 802 and the known data detector and generator 804.

The demodulator 802 performs automatic gain control, carrier recovery, and timing recovery on the input IF signal to form a baseband signal and outputs the same to the equalizer 803 and the known data detection and generation unit 804. .

The equalizer 803 compensates for the distortion on the channel included in the demodulated signal and outputs it to the E-VSB block decoder 805.

At this time, the known data detection and generation unit 804 detects the position of the known data inserted by the transmitting side from the input / output data of the demodulator 802, that is, data before demodulation or data after demodulation is performed. Along with the information, a symbol string of known data generated at the position is output to the demodulator 802, the equalizer 803, and the E-VSB block decoder 805. In addition, the known data detection and generation unit 804 may include enhanced data (that is, enhanced data through any one of the enhanced encoders of FIGS. 6A, 6B, 7A, and 7B) that have been further encoded on the transmitting side. The E-VSB block decoder 805 provides information for identifying a starting point of a block of an enhanced encoder as well as a purpose of distinguishing the main data without additional encoding by the receiving E-VSB block decoder 805. )

The demodulator 802 can improve demodulation performance by using the known data symbol string during timing recovery or carrier recovery. The equalizer 803 can also use the known data to improve equalization performance. have. In addition, the equalization performance may be improved by feeding back the decoding result of the E-VSB block decoder 805 to the equalizer 803.

On the other hand, the data input from the equalizer 803 to the E-VSB block decoder 805 is main data or known data for which only trellis coding is performed without additional encoding at the transmitting side, or additional encoding and trellis. It is enhanced data on which all the encoding has been performed.

If the input data is main data or known data (or known data position holder), the E-VSB block decoder 805 performs Viterbi decoding on the input data or hard judges the soft decision value and outputs the result. You may. In addition, RS parity bytes and MPEG header bytes added to the enhanced data packet at the transmitting side are also regarded as main data at the transmitting side and no further encoding is performed. Thus, Viterbi decoding is performed or the soft decision value is hardly determined. And print the result.

Meanwhile, if the input data is enhanced data, the E-VSB block decoder 805 outputs a soft decision value with respect to the input enhanced data. This is to increase the performance of the additional error correction decoding performed by the E-VSB data processor 811 on the enhanced data.

The E-VSB data processor 811 then receives this soft decision value and performs additional error correction decoding. That is, the E-VSB data processing unit 811 performs error correction decoding on the soft determined enhanced data. As the error correction decoder, an RS decoder, a convolutional decoder, a low density parity check code (LDPC) decoder or a turbo decoder may be used.

In other words, if the input data is enhanced data, the E-VSB block decoder 805 decodes the E-VSB block processor 113 and the trellis encoder 203. At this time, the block encoder of the E-VSB preprocessor of the transmitting side becomes an external code, and the E-VSB block processor 113 and the trellis encoder 203 can be regarded as one internal code.

In order to maximize the performance of the outer code at the time of decoding the concatenated code, the soft decision must be output from the decoder of the inner code. Therefore, the E-VSB block decoder 805 preferably outputs a soft decision value without outputting a hard decision value to the enhanced data.

If the input enhanced data passes through the enhanced encoders of FIGS. 6A and 6B, a symbol deinterleaver for performing a reverse process on the symbol interleaver to convert the soft decision value output by performing soft decision decoding on trellis encoding ( (Not shown) to perform the deinterleaving process, and then the decoding can be completed through a decoding process that can perform an inverse process of the symbol encoder.

In addition, if the input enhanced data passes through the enhanced encoders of FIGS. 7A and 7B, after the symbol deinterleaving process is performed on the soft decision value for trellis encoding, an inverse process of the internal encoder may be performed. An internal decoding process is performed. As a result of the decoding, the soft decision value must be output using a decoder capable of obtaining the soft decision value as in the trellis decoding. The soft decision value is subjected to an external decoding process for performing an inverse process on the external encoder, thereby obtaining decoded enhanced data.

In this process, when the trellis decoder and the decoder for the symbol encoder of FIG. 6 (or the internal encoder of FIG. 7) are constituted by a soft decision decoder capable of outputting a soft decision value, the soft decision value of the trellis decoder. Can aid in the determination of the decoder for the symbol encoder of FIG. 6 (or the internal encoder of FIG. 7), and the soft decision value of the decoder for the symbol encoder of FIG. 6 (or the internal encoder of FIG. 7) thus assisted. The overall decoding performance can be improved by using a turbo decoding method that can be returned to the trellis decoder to assist in the determination of the trellis decoder.

Algorithms for outputting soft determination values for the enhanced data include SOVA (Soft Output Viterbi Algorithm), MAP (Maximum A Posteriori), and SSA (Suboptimum Soft output Algorithm) algorithms. In this case, when the trellis encoder of the trellis encoder as the transmission method proposed by the present invention uses the memory state initialization of the trellis encoder as a block so that the trellis encoder returns from the determined state value to the determined state value, the MAP algorithm, SOVA, etc. Optimum performance can be obtained by applying soft decision value by applying algorithm.

Meanwhile, the output of the E-VSB block decoder 805 is input to the deinterleaver 806. The deinterleaver 806 performs an inverse process of the data interleaver on the transmitting side and outputs the decoded data to an RS decoder / Non-systematic RS parity remover 807. The RS decoder / unstructured RS parity remover 807 performs systematic RS decoding when the received packet is a main data packet, and removes the unstructured RS parity byte inserted in the packet when the received packet is an enhanced data packet. Output to the randomizer 808.

The derandomizer 808 receives the output of the RS decoder / unstructured RS parity remover 807 and generates the same pseudo random bytes as the randomizer of the transmitter to bitwise XOR (exclusive OR) the MPEG. A sync byte is inserted before each packet and output in units of 188 byte packets. The output of the derandomizer 808 is output to the main MPEG decoder (not shown) and to the main data packet remover 809. The main MPEG decoder decodes only packets corresponding to the main MPEG. This is because the enhanced data packet is not used by the existing VSB receiver, or because it has a null or reserved PID, it is not used for decoding in the main MPEG decoder and is ignored.

However, the soft decision value of the enhanced data is difficult to XOR with a pseudo random bit. Therefore, the data to be output to the main MPEG decoder is hard-determined according to the sign of the soft decision value as described above, and is then output by XORing the pseudo random bits. That is, if the sign of the soft decision value is positive, it is determined as 1, and if it is negative, it is determined as 0, and this decision value is XORed with the pseudo random bit.

However, since the E-VSB data processing unit 811 needs a soft decision to improve performance when decoding the error correction code as described above, the de-randomizer 808 generates a separate output for the enhanced data. Output to the main data packet removal unit 809. In one embodiment, the derandomizer 808 reverses the sign of the soft decision value when the pseudo random bit to be XORed with respect to the soft decision value of the enhanced data bit is 1, and if it is 0, Output

The reason for changing the sign of the soft decision value when the pseudo random bit is 1 in the above description is that the output data bit is reversed when the pseudo random bit XORed to the input data bit in the transmitter's renderer is 1. That is, 0 XOR 1 = 1 and 1 XOR 1 = 0.

In other words, when the pseudorandom bit generated by the de-randomizer 808 is 1, the value is reversed when the hard decision value of the enhanced data bit is XORed. Therefore, the soft decision value is output when the soft decision value is output. The sign is reversed.

The main data packet removing unit 809 takes only the soft decision value of the enhanced data packet from the output of the derandomizer 808 and outputs the soft decision value. That is, the main data packet removing unit 809 removes the main data packet in units of 188 bytes from the output of the derandomizer 808, takes only the soft decision value of the enhanced data packet, and then uses the E-VSB packet deformatter 810. )

The E-VSB packet deformatter 810 first removes the MPEG header having the PID for the enhanced data inserted to distinguish it from the main data packet at the transmitting side, thereby obtaining a packet of 184 byte units. The 184 byte packets are collected to form a group of a predetermined size, and the known data inserted for demodulation and equalization at the transmitting side is removed at the predetermined position. In addition, the enhanced data of the head, body, and tail regions in the enhanced data group are classified and output to the E-VSB data processor 811. In other words, the E-VSB preprocessing unit of the transmitting side separately outputs the data by the E-VSB preprocessed enhanced data type.

The output of the E-VSB packet deformatter 810 is input to the E-VSB data processor 811.

The E-VSB data processor 811 performs block deinterleaving and block decoding on the soft-determined and output enhanced data.

That is, the E-VSB data processor 811 is a reverse process of the E-VSB preprocessor of the transmitting side. The E-VSB preprocessor of the E-VSB transmission system separately performs additional block encoding, block interleaving, and inserting null bits or repeatedly inserting input bits for the input enhanced data according to the type of the enhanced data. To perform. Accordingly, the E-VSB data processing unit 811 also performs the reverse process of the E-VSB preprocessing on the sender's E-VSB preprocessing separately for the enhanced data input according to the enhanced data type, and is divided according to importance or priority at the transmitter. Similarly, the separated final enhanced data is output. That is, the E-VSB data processor 811 soft-determines the input enhanced data and removes the null bit or the repetition bit inserted for byte expansion in the E-VSB preprocessor for each type, and then blocks deinterleaving and blocks. Decryption is performed to output the final enhanced data.

For example, the final enhanced data is divided into high priority data and low priority data.

On the other hand, the terms used in the present invention (terminology) are terms defined in consideration of the functions in the present invention may vary according to the intention or practice of those skilled in the art, the definitions are the overall contents of the present invention It should be based on.

The present invention is not limited to the above-described embodiments, and can be modified by those skilled in the art as can be seen from the appended claims, and such modifications are within the scope of the present invention.

As described above, the digital broadcasting system and the processing method according to the present invention have the advantage of being resistant to errors and compatible with existing VSB receivers when transmitting additional data through a channel. In addition, there is an advantage that the additional data can be received without error even in a ghost and noisy channel than the conventional VSB system.

In addition, the present invention is to group the plurality of enhanced data packets having information, and to transmit the group by multiplexing the group with the main data, the grouping of the group into a plurality of areas, the data inserted according to the characteristics of the layered area By dividing the types, processing methods, and the like, the reception performance of the reception system can be improved. In particular, by differently applying the E-VSB preprocessing process according to the type of data inserted into the layered area of the group and the type of enhanced data input, the reception performance of the receiving system may be further improved. In addition, the present invention can improve decoding performance by performing soft decision decoding on the enhanced data at the receiving side.

The present invention is more effective when applied to portable and mobile receivers that require severe channel changes and robustness against noise.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention.

Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.

Claims (31)

Coding the first enhanced data at a first coding rate for forward error correction; Coding the second enhanced data at a second coding rate for forward error correction; Generating an enhanced data packet comprising the first enhanced data and / or the second enhanced data; Multiplexing the generated enhanced data packet and a main data packet including main data; Performing systematic RS (Reed Solomon) encoding on the main data of the multiplexed data packet and performing unstructured RS encoding on the enhanced data of the multiplexed data packet; And Interleaving the RS encoded enhanced and main data; / RTI > Here, when the interleaving is performed, a data group including a first data area, a third data area, and a second data area located between the first data area and the third data area is output. And the data group includes initialization data for initializing a memory of a trellis encoder. The method of claim 1, wherein the data group is A method for processing enhanced and main data in a digital broadcast transmitter comprising at least two known data sequences inserted at regular intervals. The method of claim 1, And wherein the first coding rate and the second coding rate are different from each other. The method of claim 1, And wherein said first coding rate is higher than said second coding rate. A first encoder for coding the first enhanced data at a first coding rate for forward error correction; A second encoder for coding the second enhanced data at a second coding rate for forward error correction; A data formatter for generating an enhanced data packet comprising the first enhanced data and / or the second enhanced data; A multiplexer which multiplexes the generated enhanced data packet and a main data packet including main data; An RS encoder for performing systematic RS (Reed Solomon) encoding on the main data of the multiplexed data packet and performing an unsystematic RS encoding on the enhanced data of the multiplexed data packet; And A data interleaver for interleaving the RS encoded enhanced and main data; / RTI > Here, when the interleaving is performed, a data group including a first data area, a third data area, and a second data area located between the first data area and the third data area is output. And the data group includes initialization data for initializing a memory of a trellis encoder. The method of claim 5, wherein the data group is And at least two known data streams inserted at regular intervals. 6. The method of claim 5, And wherein the first coding rate and the second coding rate are different from each other. 6. The method of claim 5, And wherein the first coding rate is higher than the second coding rate. delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete

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