KR101174162B1 - Liquid crystal display - Google Patents

Abstract

The present invention relates to a liquid crystal display device which reduces power consumption and prevents flicker from occurring in a specific data pattern.

The liquid crystal display includes a data driver for converting digital video data into the data voltage and supplying the data voltage to the data lines; A plurality of gate lines and a plurality of data lines intersect, and a plurality of liquid crystal cells are arranged in a matrix form, in response to a scan signal from an n-1 (n is positive integer) th gate line within the same horizontal scan line. First thin film transistors for supplying the data voltage from the data line to the liquid crystal cells are continuously disposed in two or more horizontal directions and in response to a scan signal from an nth gate line in the same horizontal scan line. A liquid crystal panel in which at least two second thin film transistors for supplying a data voltage from the liquid crystal cells are continuously formed; And a common voltage generator for supplying an AC common voltage having the polarity of the data voltage reversed in units of one horizontal period to the common electrodes of the liquid crystal cells.

Description

Liquid Crystal Display {LIQUID CRYSTAL DISPLAY}

1 is a view showing a conventional liquid crystal display device.

2A and 2B are views for explaining a line inversion driving method of a liquid crystal display device.

3A and 3B are views for explaining a column inversion driving method of a liquid crystal display device.

4A and 4B are diagrams for explaining a dot inversion driving method of a liquid crystal display device.

5A and 5B illustrate an example of a data pattern in which flicker is generated in a dot inversion driving scheme.

6 and 7 are block diagrams illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

8 is a waveform diagram showing a data voltage output from a data driver and a common voltage output from a common voltage generator.

9 is a block diagram illustrating in detail the timing controller illustrated in FIGS. 6 and 7.

10 is a block diagram illustrating in detail a data driver of a liquid crystal display according to another exemplary embodiment of the present invention.

11 and 12 are block diagrams illustrating a liquid crystal display according to another exemplary embodiment of the present invention.

<Short description of the symbols in the drawings>

2, 12: liquid crystal panel 4, 14: gate driver

6, 16, 26: data driver 18: timing controller

20: common voltage generator 34: control signal generator

36: pixel data alignment unit 38: line memory

40: shift register array 42: latch array

44: delay array 46: DAC array

48: buffer array

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device to reduce power consumption and prevent flicker.

A typical liquid crystal display device displays an image by adjusting light transmittance for each liquid crystal cell according to a video signal. To this end, the liquid crystal display includes a liquid crystal panel in which liquid crystal cells are arranged in a matrix and a driving circuit for driving the liquid crystal panel.

In the liquid crystal panel, liquid crystal cells are positioned in an area formed by intersections of gate lines and data lines. Each of the liquid crystal cells is provided with pixel electrodes and a common electrode for applying an electric field. Each of the pixel electrodes is connected to one of the data lines via a thin film transistor which is a switching element. The gate terminal of the thin film transistor is connected to one of the gate lines for causing the data voltage signal to be applied to the pixel electrodes for one line. The driving circuit includes a gate driver for driving the gate lines, a data driver for driving the data lines, and a common voltage generator for driving the common electrode. The gate driver sequentially supplies the scanning signal, that is, the gate signal to the gate lines, to sequentially drive the liquid crystal cells on the liquid crystal panel by one line. The data driver supplies a data voltage signal to each of the data lines whenever a gate signal is supplied to any one of the gate lines. The common voltage generator supplies a common voltage signal to the common electrode. Accordingly, the liquid crystal display device displays an image by adjusting the light transmittance by changing the liquid crystal arrangement state between the pixel electrode and the common electrode according to the data voltage signal for each liquid crystal cell.

In fact, the liquid crystal display includes a liquid crystal panel 2 in which liquid crystal cells are arranged in a matrix form as shown in FIG. 1, and a gate driver 4 for driving gate lines GL1 to GLn of the liquid crystal panel 2. ) And a data driver 6 for driving the data lines DL1 to DLm of the liquid crystal panel 2.

In FIG. 1, the liquid crystal panel 2 includes thin film transistors TFT formed at intersections of n gate lines GL1 to GLn and m data lines DL1 to DLm and thin film transistors TFT. The connected liquid crystal cell is provided. The thin film transistor TFT supplies a video signal from the data lines DL1 to DLm to the liquid crystal cell in response to the gate signal from the gate lines GL1 to GLn. The liquid crystal cell is equivalently represented by the liquid crystal capacitor Clc as the liquid crystal cell includes a common electrode facing the liquid crystal and a pixel electrode connected to the thin film transistor. The liquid crystal cell further includes a storage capacitor (not shown) for maintaining the data voltage charged in the liquid crystal capacitor Clc until the next data voltage is charged. The storage capacitor is usually formed by overlapping the pixel electrode with the previous gate electrode.

The gate driver 4 sequentially supplies a scan signal, that is, a gate signal, to the gate lines GL1 to GLn to drive the thin film transistors TFT connected to the corresponding gate line.

The data driver 6 converts the pixel data into a data voltage signal, which is an analog signal, and supplies a video signal of one horizontal line to the data lines DL1 through DLm in a horizontal period in which the gate signal is supplied to the gate line GL. do. In this case, the data driver 6 converts the pixel data into a data voltage signal by using gamma voltages supplied for each gray level from a gamma voltage generator (not shown).

The liquid crystal display device having such a configuration has a frame inversion system, a line inversion system, or a dot inversion for driving the liquid crystal cells on the liquid crystal panel 2. It uses the same inversion driving method as the Dot Inversion System.

The frame inversion type liquid crystal panel driving method inverts the polarity of the data voltage signal supplied to the liquid crystal cells on the liquid crystal panel for each frame to prevent liquid crystal degradation.

The liquid crystal panel driving method of the line inversion method inverts the polarity of the data voltage signals supplied to the liquid crystal panel for each gate line and every frame on the liquid crystal panel as shown in FIGS. 2A and 2B. This line inversion driving method has a problem in that flicker such as a stripe pattern occurs between horizontal lines as crosstalk between horizontal pixels exists.

The column inversion type liquid crystal panel driving method inverts polarities of data voltage signals supplied to the liquid crystal panel according to data lines and frames on the liquid crystal panel as shown in FIGS. 3A and 3B. This column inversion driving method has a problem in that flicker, such as a stripe pattern, occurs between vertical lines as crosstalk exists between vertical pixels.

In the dot-inversion liquid crystal panel driving method, as shown in FIGS. 4A and 4B, a data voltage signal having a polarity opposite to that of all liquid crystal cells adjacent to each other in the horizontal and vertical directions is supplied to each of the liquid crystal cells, and the data voltage signal is transmitted for each frame. Let the polarity of be reversed. In other words, in the case of displaying the video signal of the odd frame, the dot inversion method has a positive polarity (proceeding from the upper left liquid crystal cell to the right liquid crystal cell and the lower liquid crystal cells as shown in FIG. 4A). The data voltage signals are supplied to each of the liquid crystal cells so that +) and negative polarity (-) alternately appear. In the case of displaying the video signal of the even-numbered frame, as shown in FIG. 4B, the negative polarity (-) and the positive polarity (-) proceed from the upper left liquid crystal cell to the right liquid crystal cell and to the lower liquid crystal cells. The data voltage signals are supplied to each of the liquid crystal cells so that +) alternates. The dot inversion driving method cancels the flicker generated between adjacent pixels in the vertical and horizontal directions, thereby providing an image having excellent image quality compared to other inversion methods.

However, in the dot inversion driving method, since the polarity of the data voltage signal supplied to the data lines in the data driver must be reversed in the horizontal and vertical directions, the variation amount of the data voltage, that is, the frequency of the data voltage signal, is different from that of other inversion methods. Because of the large power consumption has the disadvantage. In addition, the dot inversion driving method includes data in one cell among pixels adjacent to each other in the horizontal and vertical directions as shown in FIGS. 5A and 5B and no data in other cells (or black data). Flicker is generated in the data pattern, that is, the other other pixel data pattern. In other words, in the conventional dot inversion method, only positive data is charged to the liquid crystal cells during the odd frame period and only negative data voltage is charged to the liquid crystal cells during the even frame period in the case data pattern as shown in FIGS. 5A and 5B. This results in flicker between neighboring frame periods.

Accordingly, an object of the present invention is to provide a liquid crystal display device which reduces power consumption and prevents flicker from occurring in a specific data pattern.

In order to achieve the above object, a liquid crystal display device according to the present invention comprises a data driver for converting the digital video data into the data voltage to supply the data lines; A plurality of gate lines and a plurality of data lines intersect, and a plurality of liquid crystal cells are arranged in a matrix form, in response to a scan signal from an n-1 (n is positive integer) th gate line within the same horizontal scan line. First thin film transistors for supplying the data voltage from the data line to the liquid crystal cells are continuously disposed in two or more horizontal directions and in response to a scan signal from an nth gate line in the same horizontal scan line. A liquid crystal panel in which at least two second thin film transistors for supplying a data voltage from the liquid crystal cells are continuously formed; And a common voltage generator for supplying an AC common voltage having the polarity of the data voltage reversed in units of one horizontal period to the common electrodes of the liquid crystal cells.

Other objects and advantages of the present invention in addition to the above objects will become apparent from the detailed description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 6 to 11B.

6 illustrates a polarity of a data voltage charged in liquid crystal cells during an odd frame period as a liquid crystal display according to an exemplary embodiment of the present invention. 7 is a liquid crystal display according to an exemplary embodiment of the present invention, and shows polarities of data voltages charged in liquid crystal cells during an excellent frame period.

6 and 7 illustrate a liquid crystal panel 12 in which liquid crystal cells are arranged in a matrix, and a gate driver for driving gate lines GL1 to GLn + 1 of the liquid crystal panel 12. 14, a data driver 16 for driving the data lines DL1 to DLm of the liquid crystal panel 12, a timing controller 18 for controlling the gate driver 14 and the data driver 16, and And a common voltage generator 20 for generating a common voltage Vcom and supplying the same to the liquid crystal panel 12.

The liquid crystal panel 12 includes gate lines GL1 to GLn + 1 and data lines DL1 to DLm that cross each other while being insulated from the gate lines GL1 to GLn + 1. Liquid crystal cells are formed in each region provided at the intersection of the gate lines GL1 to GLn + 1 and the data lines DL1 to DLm. Each of the liquid crystal cells includes a thin film transistor TFT connected to one of the gate lines GL1 to GLn + 1 and one of the data lines DL1 to DLm, a common electrode facing the liquid crystal, and a common electrode. The liquid crystal capacitor Clc is formed of a pixel electrode connected to the thin film transistor TFT. Each of the liquid crystal cells further includes a storage capacitor (not shown) for maintaining the data voltage charged in the liquid crystal capacitor Clc until the next data voltage is charged.

In the liquid crystal panel 12, one more gate line is added as compared with the related art. 4n-3 (n is a positive integer) th liquid crystal cell Clc is the 4n-3th data line DL1, DL5, ..., DLm-3 among the adjacent liquid crystal cells in one horizontal scanning line. Data from the 4n- 2nd liquid crystal cell Clc charges data from the 4n- 2nd data lines DL2, DL6, ..., DLm-2. The 4n-3rd liquid crystal cell Clc and the 4n-2nd liquid crystal cell Clc charge data voltages having the same polarity. The 4n−1 th liquid crystal cell Clc is charged with data from the 4n−1 th data lines DL3, DL7,..., DLm-1, and the 4n th liquid crystal cell Clc has a 4n th data line ( Charge data from DL4, DL8, ..., DLm). The 4n-1 th liquid crystal cell Clc and the 4n th liquid crystal cell Clc are data voltages having a polarity different from that of the data voltage charged in the 4n-3 th liquid crystal cell Clc and the 4n-2 th liquid crystal cell Clc. To charge. Data voltages of the same polarity are applied to the data lines DL1 to DLm of the liquid crystal panel 12, and the liquid crystal cells charge the data voltage in a horizontal 2 dot and vertical 1 dot inversion scheme.

In other words, data voltages of the same polarity are simultaneously supplied to the data lines DL1 through DLm, and the voltage level of the data voltage is changed in units of one horizontal period according to the gray level of the digital video data. When this data voltage is supplied, the 4n-3th liquid crystal cell (Clc) and the 4n-2nd liquid crystal cell (Clc) in the n-th horizontal scanning line, and the 4n-1th liquid crystal cell (Clc) in the n + 1th horizontal scanning line ) And the 4n-th liquid crystal cell Clc charge data voltages having the same polarity, and then charge data voltages having different polarities after one horizontal period.

The thin film transistors TFT for supplying the data voltage signal from the data line DL to the liquid crystal cell in response to the gate signal are connected as follows.

In the same horizontal scanning line, the 4n-3rd thin film transistor TFT and the 4n-2nd thin film transistor TFT have their gate terminals connected to the nth gate line. The source terminal of the 4n-3th thin film transistor TFT is connected to the 4n-3th data line DL1, DL5, ..., DLm-3, and the drain terminal of the 4n-3rd thin film transistor TFT is 4n. It is connected to -3rd liquid crystal cell Clc. The source terminal of the 4n-2 th thin film transistor TFT is connected to the 4n-2 th data line DL2, DL6, ..., DLm-2, and the drain terminal of the 4n-2 th thin film transistor TFT is 4n. It is connected to the -2th liquid crystal cell Clc.

In the same horizontal scanning line, the 4n-1th thin film transistor TFT and the 4nth thin film transistor TFT have their gate terminals connected to the n-1th gate line. The source terminal of the 4n-1 th thin film transistor TFT is connected to the 4n-1 th data line DL3, DL7, ..., DLm-1, and the drain terminal of the 4n-1 th thin film transistor TFT is 4n. It is connected to the -1th liquid crystal cell Clc. The source terminal of the 4nth thin film transistor TFT is connected to the 4nth data line DL4, DL8, ..., DLm, and the drain terminal of the 4nth thin film transistor TFT is connected to the 4nth liquid crystal cell Clc. do.

The gate driver 14 sequentially supplies a gate signal (or scan signal), that is, a gate high voltage, to the gate lines GL1 to GLn + 1 to drive the thin film transistors TFT connected to the corresponding gate line. .

The data driver 16 converts the input digital video data into the same analog data voltage using analog gamma voltages and supplies the same to the data lines DL1 to DLm. The data driver 16 has 4n-3th liquid crystal cell Clc and 4n-2nd liquid crystal cell Clc of the n + 1th horizontal scanning line and 4n− of the nth horizontal scanning line within one horizontal period. The analog data voltages of the same polarity must be simultaneously supplied to the first liquid crystal cell Clc and the 4nth liquid crystal cell Clc. To this end, the data driver 16 delays n− with the digital video data of the 4n−1th liquid crystal cell Clc and the 4n−th liquid crystal cell Clc of the nth horizontal scanning line which is undelayed from the timing controller 18. Digital video data of the 4n-3rd liquid crystal cell Clc and the 4n-2nd liquid crystal cell Clc of the first horizontal scanning line are supplied.

The timing controller 18 generates control signals for controlling the driving of the gate driver 14 and the data driver 16, and supplies the pixel data signal to the data driver 16. In particular, the timing controller 18 delays the digital video data of the 4n-3th liquid crystal cell Clc and the 4n-2th liquid crystal cell Clc of the n−1 th horizontal scanning line by one horizontal line using a line memory. And then the delayed 4n-3rd liquid crystal cell (Clc) and 4n-2nd liquid crystal cell (Clc) together with the digital of the 4n-1th liquid crystal cell (Clc) and 4nth liquid crystal cell (Clc) The video data is supplied to the data driver.

The common voltage generator 20 generates an AC common voltage Vcom swinging in units of one horizontal period as shown in FIG. 8, and supplies the common voltage to the common electrode facing the pixel electrode with the liquid crystal interposed therebetween. For example, the AC common voltage Vcom is generated at a voltage lower than the data voltage supplied to the data lines DL1 to DLm for every odd horizontal line during the odd frame period, while the data lines DL1 to DLm for every even horizontal line. Is generated at a voltage higher than the data voltage supplied to The AC common voltage Vcom is generated at a voltage higher than the data voltage supplied to the data lines DL1 to DLm every odd horizontal line during the even frame period following the odd frame period, while the data lines are applied to the even horizontal line. It is generated at a voltage lower than the data voltage supplied to the DL1 to DLm.

Meanwhile, in order to charge the data voltages to the liquid crystal cells Clc by the line inversion method, the data driver 16 supplies the data voltage signals having the same polarity without the polarity inversion of the data voltage signals every horizontal period. The AC common voltage Vcom generated at 20 is swinged in units of one horizontal period. Accordingly, the data driver 16 supplies a constant data voltage to the data lines DL1 to DLm without polarity inversion, but the liquid crystal cells of the liquid crystal panel 12 are horizontal two dot inversion and vertical one dot by the AC common voltage. Charges the data voltage in inversion form.

By the AC common voltage Vcom, the data driver 16 includes only gamma voltages corresponding to the same polarity as shown in FIG. 8, thereby eliminating waste of power consumption due to polarity inversion control of data, and the data driver 16. The configuration of the gamma reference voltage generator circuit for supplying gamma voltages to the circuit is simplified.

9 is a diagram showing the timing controller 18 in detail.

Referring to FIG. 9, the timing controller 18 controls the data driver 16 through the first and second data buses 18a and 18b by rearranging the digital video data with the control signal generator 34 generating the control signals. A pixel data alignment unit 36 for outputting the same. The line memory 38 is connected to the second data bus 18b between the timing controller 18 and the data driver 16.

The control signal generator 34 uses gate input signals V, H, and MCLK to control the gate control signals for controlling the gate driver 14 and the data control signals for controlling the data driver 16. Generation (DDC).

The pixel data alignment unit 36 outputs the 4n-th data and the 4n-1th data of the n-th horizontal scan line through the first data bus 18a, and at the same time, the 4n-3th of the n-1 th horizontal scan line. Data and 4n-2th data are output via the second data bus 18a.

The line memory 38 delays the 4n-3th data and the 4n-2th data of the n-1 th horizontal scanning line input through the second data bus 18b for one line period, and then the data driver 16 To feed.

As a liquid crystal display device according to another exemplary embodiment of the present invention, a delay array 44 is added to the data driver 16 as shown in FIG. 10 without adding a line memory between the timing controller 18 and the data driver 16. You may.

Referring to FIG. 10, the data driver 26 includes a shift register array 40 for supplying a sequential sampling signal, a latch array 42 for latching and outputting pixel data in response to the sampling signal, and a latch array 42. Delay array 44 for delaying the 4n-3rd data and 4n-2nd data of the n-1 th horizontal scanning line input from the N-th horizontal scan line, and data from the latch array 42 and the delay array 44 A digital-to-analog conversion (hereinafter referred to as DAC) array 46 for converting the data into an analog data voltage, and a buffer array 48 for supplying data voltages from the DAC array 46 to the data lines.

The plurality of shift registers of the shift register array 40 sequentially shift the input source start pulse SSP from the timing controller 28 according to the source sampling clock signal SSC and output the sampling signal.

A plurality of latches configured in the latch array 42 are sequentially latched by sampling input pixel data VD by a predetermined unit in response to a sampling signal from the shift register array 40 and outputting a source from the timing controller 28. Simultaneously output in response to the enable signal SOE.

The plurality of delayers configured in the delay array 44 delay the 4n-3rd data and the 4n-2th data of the n-1th horizontal scan line output from the latch array 42 for one horizontal period.

The DAC array 46 includes 4n-3th data of the undelayed nth horizontal scanning line and 4n-1st data of the nth horizontal scanning line and 4n-3rd data and 4n-2 of the n-1th horizontal scanning line delayed by the delay array array 44. The second data is simultaneously converted into analog data voltage using the gamma voltage.

11 and 12 illustrate a liquid crystal panel according to another exemplary embodiment of the present invention. FIG. 11 illustrates a polarity of a data voltage charged in liquid crystal cells during an odd frame period as a liquid crystal display according to another exemplary embodiment. 12 is a liquid crystal display according to another embodiment of the present invention shows the polarity of the data voltage charged in the liquid crystal cells during the excellent frame period. Compared to the liquid crystal panel of FIGS. 6 and 7 described above, the liquid crystal panel 12 of this embodiment has only the arrangement of the thin film transistors TFT and the arrangement of the liquid crystal cell Clc and the signal lines being substantially the same.

11 and 12, in the same horizontal scanning line, the 4n-3rd thin film transistor TFT and the 4n-2nd thin film transistor TFT have their gate terminals connected to the n-1 th gate line. The source terminal of the 4n-3th thin film transistor TFT is connected to the 4n-3th data line DL1, DL5, ..., DLm-3, and the drain terminal of the 4n-3rd thin film transistor TFT is 4n. It is connected to -3rd liquid crystal cell Clc. The source terminal of the 4n-2 th thin film transistor TFT is connected to the 4n-2 th data line DL2, DL6, ..., DLm-2, and the drain terminal of the 4n-2 th thin film transistor TFT is 4n. It is connected to the -2th liquid crystal cell Clc.

In the same horizontal scanning line, the gate terminal of the 4n−1 th thin film transistor TFT and the 4n th thin film transistor TFT is connected to the n th gate line. The source terminal of the 4n-1 th thin film transistor TFT is connected to the 4n-1 th data line DL3, DL7, ..., DLm-1, and the drain terminal of the 4n-1 th thin film transistor TFT is 4n. It is connected to the -1th liquid crystal cell Clc. The source terminal of the 4nth thin film transistor TFT is connected to the 4nth data line DL4, DL8, ..., DLm, and the drain terminal of the 4nth thin film transistor TFT is connected to the 4nth liquid crystal cell Clc. do.

In the liquid crystal display of FIGS. 11 and 12, the delayed data are opposite to those of the liquid crystal display of FIGS. 6 and 7. That is, as a result of the different arrangements of the thin film transistors of the liquid crystal panel 12, the delay array in the line memory or the data driver connected to the output terminal of the timing controller 18 receives the 4n-1th digital video data and the 4nth digital video data. Delay.

In the liquid crystal display according to the present invention, the liquid crystal panel is driven in a horizontal 2-dot inversion and vertical 1-dot inversion so that data of the inter-cell data patterns as shown in FIGS. 5A and 5B used in a Windows end screen or a fade out screen is input. In this case, it is possible to prevent the occurrence of flicker in the frame period by charging both the positive data and the negative data in the liquid crystal cells every frame period.

As described above, the liquid crystal display according to the present invention includes two TFTs each having a TFT connected with a gate terminal to an n-1 th gate line and a TFT connected with a gate terminal connected to an n th gate line in the same horizontal scanning line. The data driver outputs a data voltage in which the data driver does not change the polarity of the data voltage compared to the common voltage, while supplying the AC common voltage to the common electrode. As a result, the liquid crystal display according to the present invention reduces the power consumption of the data driver and drives the liquid crystal panel in the form of horizontal 2 dot inversion and vertical 1 dot inversion so that the data exist in the horizontal and vertical directions in every cell unit. Flicker can be prevented in patterns.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (10)

A data driver for converting digital video data into a data voltage and supplying the data lines to the data lines; A plurality of gate lines and a plurality of data lines intersect, and a plurality of liquid crystal cells are arranged in a matrix form, in response to a scan signal from an n-1 (n is positive integer) th gate line within the same horizontal scan line. First thin film transistors for supplying the data voltage from the data line to the liquid crystal cells are continuously disposed in two or more horizontal directions and in response to a scan signal from an nth gate line in the same horizontal scan line. A liquid crystal panel in which at least two second thin film transistors for supplying a data voltage from the liquid crystal cells are continuously formed; And a common voltage generator for supplying an AC common voltage having the polarity of the data voltage reversed in units of one horizontal period to the common electrodes of the liquid crystal cells. And the data driver supplies a data voltage having opposite polarity to the data line in units of one horizontal period. The method of claim 1, A 4n-3th thin film transistor and a 4n-2th thin film transistor in the same horizontal scan line have their gate terminals connected to the n-1th gate line; A source terminal of the 4n-3rd thin film transistor is connected to the 4n-3rd data line, and a drain terminal of the 4n-3rd thin film transistor is connected to the 4n-3rd liquid crystal cell; A source terminal of the 4n-2th thin film transistor is connected to the 4n-2th data line, and a drain terminal of the 4n-2nd thin film transistor is connected to the 4n-2nd liquid crystal cell; A gate terminal of a 4n-1th thin film transistor and a 4nth thin film transistor in the same horizontal scanning line are connected to an nth gate line; The source terminal of the 4n-1th thin film transistor is connected to the 4n-1th data line; A drain terminal of the 4n-1th thin film transistor is connected to the 4n-1th liquid crystal cell; The source terminal of the 4nth thin film transistor is connected to the 4nth data line, and the drain terminal of the 4nth thin film transistor is connected to the 4nth liquid crystal cell. The method of claim 1, A gate terminal of a 4n-3th thin film transistor and a 4n-2nd thin film transistor in the same horizontal scan line are connected to the nth gate line; A source terminal of the 4n-3rd thin film transistor is connected to the 4n-3rd data line, and a drain terminal of the 4n-3rd thin film transistor is connected to the 4n-3rd liquid crystal cell; A source terminal of the 4n-2th thin film transistor is connected to the 4n-2th data line, and a drain terminal of the 4n-2nd thin film transistor is connected to the 4n-2nd liquid crystal cell; In the same horizontal scanning line, the 4n-1th thin film transistor and the 4nth thin film transistor have their gate terminals connected to the n-1th gate line; The source terminal of the 4n-1th thin film transistor is connected to the 4n-1th data line; A drain terminal of the 4n-1th thin film transistor is connected to the 4n-1th liquid crystal cell; The source terminal of the 4nth thin film transistor is connected to the 4nth data line, and the drain terminal of the 4nth thin film transistor is connected to the 4nth liquid crystal cell. The method of claim 1, A 4n-3th thin film transistor and a 4n-2th thin film transistor in the same horizontal scan line have their gate terminals connected to the n-1th gate line; A source terminal of the 4n-3rd thin film transistor is connected to the 4n-3rd data line, and a drain terminal of the 4n-3rd thin film transistor is connected to the 4n-3rd liquid crystal cell; A source terminal of the 4n-2th thin film transistor is connected to the 4n-2th data line, and a drain terminal of the 4n-2nd thin film transistor is connected to the 4n-2nd liquid crystal cell; A gate terminal of a 4n-1th thin film transistor and a 4nth thin film transistor in the same horizontal scanning line are connected to an nth gate line; The source terminal of the 4n-1th thin film transistor is connected to the 4n-1th data line; A drain terminal of the 4n-1th thin film transistor is connected to the 4n-1th liquid crystal cell; The source terminal of the 4nth thin film transistor is connected to the 4nth data line, and the drain terminal of the 4nth thin film transistor is connected to the 4nth liquid crystal cell. The method of claim 1, The liquid crystal panel, And a data polarity inversion period of horizontally neighboring liquid crystal cells is longer than a data polarity inversion period of vertically neighboring liquid crystal cells. The method of claim 1, Horizontally adjacent liquid crystal cells of the liquid crystal cell charge data voltages whose polarities are inverted every two dot periods; Liquid crystal cells vertically adjacent among the liquid crystal cells are charged with a data voltage whose polarity is inverted in one dot period. The method of claim 2, A timing controller for supplying the digital video data to the data driver and controlling the data driver and the common voltage generator; And a delay device for delaying digital video data to be supplied to the 4n-3rd liquid crystal cells and the 4n-2th liquid crystal cells in the same horizontal scanning line input from the timing controller to supply the data driver. Display. The method of claim 3, wherein A timing controller for supplying the digital video data to the data driver and controlling the data driver and the common voltage generator; And a delay device for delaying digital video data to be supplied to the 4n-1 &lt; th &gt; liquid crystal cells and the 4n &lt; th &gt; liquid crystal cells in the same horizontal scanning line inputted from the timing controller to supply the data driver to the data driver. . The method of claim 2, A timing controller for supplying the digital video data to the data driver and controlling the data driver and the common voltage generator; And the data driver comprises a delay unit for delaying digital video data to be supplied to 4n-3th liquid crystal cells and 4n-2th liquid crystal cells in the same horizontal scanning line. The method of claim 3, wherein A timing controller for supplying the digital video data to the data driver and controlling the data driver and the common voltage generator; And the data driver comprises a delay unit for delaying digital video data to be supplied to 4n-1th liquid crystal cells and 4nth liquid crystal cells in the same horizontal scanning line.

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