KR101118719B1 - Stacked semiconductor package with localized cavities for wire bonding and method of fabricating the same - Google Patents

Abstract

The present invention provides a method for manufacturing a semiconductor die comprising (a) attaching a first semiconductor die to a substrate, (b) wire bonding a wire between a pad adjacent to a side of the first semiconductor die and a pad on the substrate; Forming a second semiconductor die on the side of the second semiconductor die, the second semiconductor die comprising a local cavity occupying a portion of the entire side, and (d) attaching the second semiconductor die on top of the first semiconductor die, the wire bonding in step (b) A method for manufacturing a semiconductor device comprising the step of causing a wire to be disposed in a local cavity.

Semiconductor Die, Local Cavity, Wire Bonding, Bond Pads

Description

Stacked semiconductor package having a local cavity for wire bonding and manufacturing method therefor {STACKED SEMICONDUCTOR PACKAGE WITH LOCALIZED CAVITIES FOR WIRE BONDING AND METHOD OF FABRICATING THE SAME}

Embodiments of the present invention relate to a low profile semiconductor device and a method of manufacturing the same.

As the demand for portable consumer electronics increases, so does the need for high capacity storage devices. Nonvolatile semiconductor memory devices, such as flash memory storage cards, are widely used to meet the ever-increasing requirements for digital information storage and exchange. Due to their portability, versatility and robust design, along with their high reliability and large capacity, such memory devices are used in a variety of electronic devices, including digital cameras, digital music players, video game consoles, PDAs and mobile phones, for example. Ideal to be

A wide variety of packaging configurations are known, and flash memory cards are generally system-in-a-package (SiP) or multichip modules (MCMs) in which multiple die are mounted on a substrate in a stacked configuration. It can be prepared as. A diagram illustrating the edge of a typical semiconductor package 20 (molding compound is not shown) is shown in FIGS. 1 and 2 of the prior art. A typical package includes a number of semiconductor dies 22, 24 mounted to a substrate 26. Although not shown in FIGS. 1 and 2, die bond pads are formed on the upper surface of the die in the semiconductor die. Substrate 26 may be formed with an electrically insulating core sandwiched between upper and lower conductive layers. The upper and / or lower conductive layer can be etched to form a conductance pattern comprising electrical leads and contact pads. The wire bond is soldered between the die bond pads of the semiconductor dies 22 and 24 and the contact pads of the substrate 26 to electrically connect the semiconductor die to the substrate. Electrical leads on the substrate provide an electrical path between the die and the host device. Once an electrical connection is made between the die and the substrate, the assembly is typically enclosed in a molding compound to provide a protective package.

BACKGROUND OF THE INVENTION A method is known in which semiconductors are offset up and down from each other (Fig. 1 of the prior art) or layered in a stacked configuration (Fig. 2 of the prior art). In the simplified configuration of FIG. 1, the dies are conveniently stacked so that the bond pads of the lower die remain exposed. Such a configuration is disclosed, for example, in US Pat. No. 6,359,340 to Lin et al., Entitled " Multichip Modules With Stacked Chip Arrays. &Quot; The convenient configuration provides the advantage of easy access to the bond pads on each semiconductor die. However, the convenient configuration requires a larger footprint on the substrate where space is important.

In the stacked configuration of FIG. 2, two or more semiconductor dies are stacked directly on top of each other, thus occupying a smaller area on the substrate as compared to the convenient configuration. However, in a stacked configuration, space must be provided for the bond wires 30 between adjacent semiconductor dies. Additional space must be maintained above the bond wire, as well as the height of the bond wire 30 itself, because an electrical short may occur as the bond wire 30 of the die contacts the next die. Thus, as shown in FIG. 2, a method of providing a dielectric spacer layer 34 to provide sufficient space for the wire bond 30 to be bonded with the die bond pads on the lower die 24 is known.

Referring to FIGS. 3 and 4 of the prior art, instead of spacer layer 34, trenches along the edge of the lower (nonactive) surface 42 of the upper die, such as die 22, It is also known to etch 40). The trench 40 has space for the wire bond 30 of the lower die, allowing the two dies to be stacked directly on top of each other without the spacer layer. As shown in FIG. 4, trenches 40 are generally formed along one edge of the die. An example of a trench formed along the entire edge is described in Tan US Pat. No. 7,309,623, which discloses a trench with vertical and horizontal sidewalls (as shown in FIG. 4 of the prior art). It is. Another example of a trench formed along its entire edge is described in Tuckerman et al. US Pat. No. 5,804,004, which discloses a trench with angled sidewalls or inclined sidewalls. These two patents are incorporated by reference herein.

A disadvantage of prior art semiconductor packages that include trenches formed along the entire edge is that the formation of trenches structurally weakens the semiconductor die. That is, if the trench leaves only a thin amount of material above the trench, the die may crack or break above the trench. This phenomenon can occur in particular during the encapsulation process, since a large force is applied to the semiconductor die in order to accurately enclose the die in the molding compound during encapsulation.

Embodiments of the present invention relate to a low profile semiconductor package comprising a semiconductor die and at least first and second stacked semiconductor dies formed therefrom and mounted to a substrate. The first and / or second semiconductor die may be manufactured with local cavities along the side edges of the semiconductor die through the bottom surface of the semiconductor die. Certain sides of the semiconductor die may not include local cavities, or may include one or more local cavities. If the sides of the die include one or more local cavities, the local cavities occupy a smaller portion than the entire side.

Once assembled into a die stack on the substrate, wire bonds from the first semiconductor die are received in a local cavity of a semiconductor die mounted on top of the first die. Thus, the dies can be stacked directly on top of each other, without the wire bonds from the first die being electrically shorted to the semiconductor die mounted on the first die. Because the cavities are locally present and do not occupy the entire side of the die, the local cavities provide a high level of structural integrity for each die while allowing for low height stacking of the semiconductor dies, resulting in cracks at the edges of the die during manufacture. Prevent breakage.

In various embodiments, the location of the local cavity in the bottom surface of the die corresponds to the location of the die bond pads in the top surface of the die. Thus, such a plurality of semiconductor dies may be stacked on top of one another and the bond pads and wire bonds extending therefrom may be aligned in local cavities of adjacent upper semiconductor dies in the stack.

The semiconductor die may include local cavities spaced inwardly from each side of the semiconductor die. In embodiments involving such local cavities, components such as passive components or secondary semiconductor dies may be mounted on and contained within the local cavity below the local cavity. The cavity serves to insulate the part from the die containing the cavity. Such a configuration improves flexibility, for example when the part can be mounted on a substrate.

According to the present invention, since the cavities are locally present and do not occupy the entire side of the die, the local cavities allow for a low height stacking of the semiconductor die, while providing a high level of structural integrity to each die during manufacture. Prevents cracking or breakage of die edges.

An embodiment will be described with reference to FIGS. 5 to 22 of a low profile semiconductor package. It is to be understood that the invention can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the invention to those skilled in the art. Indeed, the invention is intended to cover alternatives, modifications, and equivalent forms of these embodiments that fall within the scope and spirit of the invention as defined by the claims. In addition, in the following detailed description of the invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without such specific details.

The terms "upper" and "lower" and "upper" and "lower" are used herein for convenience and illustration only, and the terms referred to herein are subject to change so that these terms limit the description of the invention. It is not intended to.

A process for forming a semiconductor die according to the present invention will be described with reference to the flowchart of FIG. 5 and the top and perspective views of FIGS. 6 to 12. FIG. 6 shows a top view of a semiconductor wafer 100 for batch processing a plurality of semiconductor dies 102 (referenced to one of the semiconductor dies in FIG. 6). Bond dies 104 are formed in each die 102, for example, as shown in enlarged views of FIGS. 7 and 8. The bond pads 104 are used to electrically connect the semiconductor die 102 to other semiconductor die or to electrically connect to a printed circuit board, lead frame, or other substrate as described below. Although the bond pads 104 are shown along all edges of the die in FIGS. 7 and 8, in other embodiments the bond pads 104 may be formed at one edge, two opposing or adjacent edges, or three edges. It should be understood that it can. It should be understood that the number of bond pads 104 may be more or less than shown in the figures along a predetermined edge of the semiconductor die 102.

Referring to the flowchart of FIG. 5, an integrated circuit component of semiconductor die 102 may be formed on wafer 100 by known processes such as film deposition, photolithography, patterning, and impurity diffusion in step 200. Die bond pads 104 may be formed in each die by known processes, such as plating, deposition, screen printing, or various attachment processes in step 202, but are not limited to the processes illustrated above.

According to the present invention, a local cavity can then be formed in the backside (non-active surface) of the die 102 on the wafer 100 in step 210. Such a local cavity 110 is shown, for example, in hidden lines in the top view of FIG. 9 and in the bottom perspective view of FIG. 10. Local cavity 110 may be formed by a variety of known processes including, for example, chemical wet etching, dry etching, laser ablation, or other chemical or mechanical means to controllably remove a portion of the back of die 102. Can be. To fabricate a local cavity, one of the above-described processes may be performed on the back so that the top surface (active surface) of the wafer may be secured to the chuck such that a local cavity is formed for each semiconductor die in the wafer 100.

The location of the local cavity 110 in the bottom of the die 102 corresponds to the location of the wire bond pad 104 in the top of the die 102. That is, the local cavity 110 is formed in the bottom surface of the die 102 directly under the bond pad 104 of the upper surface of the die 102. As will be described in more detail below, a plurality of dies having the same configuration of the die bond pad 104 and the local cavity 110 may be directly stacked on top of each other and do not have a spacer layer, and the local cavity 110 may be Enables wire bonding of the lower die where no electrical short of wire bond occurs with respect to the upper die.

The length dimension of each local cavity 110 may vary, but may generally be slightly larger than a group of contact pads formed above the opposite surface of the die. Thus, the length of the local cavity 110 under a single contact pad (eg, contact pad 104a) is the length of the local cavity 110 under the number of contact pads (eg, contact pad 104b). Can be less than It should be understood that in alternative embodiments all local cavities may have the same length (eg, the length of the largest group of contact pads 104).

FIG. 10A shows a cross section along line 10-10 of FIG. 10. The horizontal depth dimension x of each local cavity 110 perpendicular to the edge of die 102 and the vertical depth dimension y of each local cavity 110 perpendicular to the lower surface of die 102 are alternative implementations. It can be changed in form. However, the horizontal and vertical depth dimensions of each local cavity may be located within a local cavity of a second semiconductor die 102 in which one or more wire bonds are connected to and mounted to the first semiconductor die 102. 102 may not be sufficient. Instead of having horizontal and vertical surfaces, the local cavity 110 forms an inclined angle with respect to the bottom of the die 102 as shown in FIG. 10B (shown in the illustrated position as the cross-sectional view of FIG. 10A). It may be formed by partially curved or inclined surfaces 112.

As shown in the figure, the cavity 110 is formed locally. That is, no cavity 110 extends along the entire length of the edge of die 102. If the side comprises a plurality of local cavities, the entirety of the local cavities of the side is less than the full length of the side. Accordingly, local cavity 110 enables low height stacking of semiconductor dies and provides a high level of structural integrity for each die to prevent cracking or breakage of die edges during manufacture.

Referring to the top view of FIG. 11 and the bottom perspective view of 12, a local cavity 114 inside the die 102, with or instead of a local cavity 110 formed along one or more edges of the die. This can be formed. That is, local cavity 114 may be spaced from each edge of die 102 and formed within the back of die 102. As described in greater detail below, such a cavity 114 in a semiconductor die may be used to receive a passive or secondary die mounted to a surface below the semiconductor die. The surface may be the surface of a lower die or substrate.

In step 212, backgrind may be performed on the backside (non-active surface) of the wafer 100 as known in the art to thin the die 102 to the desired thickness. While one die 102 is shown in FIGS. 7-12, the steps described above are carried out with the die 100 still held on the wafer 100. At step 216, each die processed may be individualized from wafer 100. Since typically only memory dies are stacked on top of each other in a semiconductor package, die 102 may typically be a memory die, such as a flash memory. However, it should be understood that the type of semiconductor die formed as described above may vary.

Referring to the flowchart of FIG. 13 and the various views of FIGS. 14 to 21, a process for forming a semiconductor package according to the present invention using the aforementioned semiconductor die 102 will be described below. Referring to FIG. 14, in operation 300, the first semiconductor die 102a may be mounted on the substrate 120. Die 102a may be mounted to substrate 120 by die attach adhesive in a known adhesive or eutectic die bond process. The die 102a shown in FIG. 14 does not include a local cavity 110 (because die 102 is a bottom die). The die 102a does not require, but may comprise, a local cavity 110 in alternative embodiments, for example a bottom die in the same manner as other die in a die stack that includes the local cavity 110. This is the case when 102a is processed from a wafer.

Although not shown, the substrate 120 may be part of the substrate panel so that the semiconductor package according to the present invention can be disposed on an economical scale. Although the following describes the manufacture of one semiconductor package, it should be understood that the following description may be applied to all packages formed on a substrate panel. Substrate 120 may be a variety of chip carrier media, including PCB, leadframe or tape automated bonded (TAB) tapes. In the case where the substrate 120 is a PCB, the substrate may consist of a core having a top and / or bottom conductive layer formed thereon. The core can be a variety of dielectric materials such as, for example, polyimide laminates, epoxy resins including FR4 and FR5, bismaleimide triazine (BT), and the like.

The conductive layer may be formed of a known material used on copper or copper alloys, plated copper or plated copper alloys, Alloy 42 (42FE / 58NI), copper plated steel or other metals or substrates. The conductive layer may be etched in a conductive pattern as is known for signal communication between the semiconductor die 102 and an external device (not shown). Substrate 120 may further include an exposed metal portion forming contact pad 122 on an upper surface of substrate 120. In the case where the semiconductor package is a land grid array (LGA) package, a contact finger (not shown) may also be formed on the lower surface of the substrate 120. Contact pad 122 and / or contact fingers may be plated with one or more gold layers, for example, by electroplating processes known in the art.

After the semiconductor die 102a is attached to the substrate 120 in step 300, a wire bond may be attached between the die bond pad 104 on the die 102a and the contact pad 122 on the substrate 120 in step 302. Can be. Wire bond 130 may be formed by a known bonding process, such as, for example, forward or reverse ball bonding. In the embodiment shown in the figures, wire bond 130 is provided along all four edges of die 102a, while in other embodiments one or more edges of die 102a may be bonded pad 104 or wire bonds. It should be understood that it may not include (130).

According to the present invention, the local cavity 110 allows multiple semiconductor dies to be stacked in a fully overlapping relationship, and there is no need to space the overlapped dies into spacer layers or the like. Thus, in step 310, the second semiconductor die 102b may be attached over the semiconductor die 102a by the use of a known die attach adhesive. Once die 102b is mounted over die 102a, wire bond 130 from bottom die 102a is received in local cavity 110 below die 102b. Thus, wire bond 130 from die 102a does not contact or electrically short with die 102b. As such, the local cavity allows die 102b to be mounted directly onto die 102a without the use of a spacer layer. In step 312, die 102b may be wire bonded to substrate 120 by a second group of wire bonds 130 similar to the method described above.

As indicated by the dashed arrows in the flowchart of FIG. 13, steps 310 and 312 may be repeated to add additional dies on top of the die stack in the same manner as the dies 102b are mounted over the dies 102a. . 14 shows one additional die 102c (without wire bonds) mounted on a die stack, but in other embodiments the die stack may include only two dies or may include more than three dies. Can be. For each die stacked, the wire bond of the die in the stack is mounted thereon and then received in the space defined by the local cavity 110 of the die. Thus, the stack may include multiple dies while still maintaining a low overall height.

In the above embodiments, wire bond 130 may be uncoated gold, but may alternatively be copper, aluminum or other metal. In another embodiment of the present invention, the bond wire may be pre-insulated with polymer insulation that makes the surface of the wire electrically nonconductive. Such pre-insulated bond wires allow the wires to be subjected to strong tensions against the upper surface of die 102 without fear of electrical shorts to the die surface. Such an embodiment allows the local cavity 110 to be formed with a smaller vertical depth (because the bond wire has a lower height). Two examples of pre-insulated bond wires suitable for use in the present invention include U.S. Patent Nos. 5,396,104 and "High Density Integrated Circuits and Methods for Packaging Them," Resin Coated Bond Wires, Methods of Making the Same, and Semiconductor Devices ". US Patent Publication No. 2004/0124545, entitled "These two publications are incorporated herein by reference in their entirety.

Referring to the side view of FIG. 15, after the die stack has been formed and bonded to the die pad on the substrate 120, the die stack may be received in the molding compound 150 in step 316 and individualized from the panel in step 318. The final semiconductor die package 160 is formed. The molding compound 150 may be, for example, a known epoxy available from Sumitomo Corp. and Nitto Denko Corp. based in Japan. In some embodiments, final package 160 may be received in a lid in step 320.

In various embodiments, semiconductor die 102 used in package 160 includes one or more flash memory chips and possibly a controller, such as an ASIC, so that package 160 can be used as a flash memory device. In another embodiment of the present invention, package 160 may include a semiconductor die configured to perform other functions.

It should be understood that the local cavity may be formed in various configurations at some of the lower edges of the die 102 to provide space for various wire bond configurations. Two such other embodiments are shown in FIGS. 16-19. In the top and side views of FIGS. 16 and 17, the local cavity 110 provides space for the die bond pad 104 along the first edge 140 of the die 102, wherein the die bond pad 104 is formed. Wire bonds to contact pads 122 along the second adjacent edge 142 of die 102. In the top and side views of FIGS. 18 and 19, the local cavity forms a curved tunnel with openings at the die edges 140, 142, but the edges between the edges 140, 142 remain intact. Such a configuration also allows die bond pads 104 along the first edge 140 of the die 102 to be wire bonded to the contact pads 122 along the second edge 142 of the die 102. . While the sidewalls are shown curved, it is to be understood that in other embodiments the sidewalls may extend linearly between adjacent edges.

In the top and side views of FIGS. 20 and 21, the local cavity 114 is not used to provide space for wire bonds, but instead for the component 146, which may be a passive component or a second semiconductor die. Provide space. Cavity 114 allows die 102 to be positioned directly above component 146 while being positioned on a substrate. Cavity 114 insulates component 146 from die 102. Such a configuration increases the flexibility when the component can be surface mounted to the substrate 120.

In the description so far, it has been disclosed that the local cavity 110 is formed in a semiconductor die. Instead, in another embodiment shown in FIG. 22, a local cavity 172 can be formed in the spacer layer 170. The spacer layer 170 is located between the pair of dies 102a, 102b. The spacer layer 170 may be of known structure, but one or more local cavities 172 may be provided and formed in layer 170 as described above. The difference in the cavities in the spacer layer 170 compared to the local cavities in the die 102 is that the local cavities 172 are formed through the entire thickness of the spacer layer 170, as shown in FIG. 22. Thus, for example, the spacer layer 170 shown in FIG. 22 has its entire front edge removed. In other embodiments, it should be understood that local cavity 172 may be formed within the bottom surface of spacer layer 170 and may extend only to a portion of the thickness, as with local cavity 110.

The thickness of the spacer layer 170 need only be sufficient to prevent the wire bond 130 from the die 102a from contacting the bottom surface of the die 102b. If spacer layer 170 is present, dies 102a and 10b need not include a local cavity.

In another embodiment the spacer layer 170 may be provided as a bottom-most layer in connection with FIGS. 20 and 21, similar to the die 102 described above, and one for receiving surface mount components. The above-described local cavity 172 may be included. In this embodiment, the cavity 172 allows the spacer layer 170 to be positioned directly above the surface mount component while being positioned on the substrate. The cavity 172 insulates the part from the die 102 mounted thereon. Such a configuration increases the flexibility when the part can be surface mounted to the substrate. As used herein, the term “lowest layer” refers to a spacer layer 170 mounted on a substrate 120 and comprising a cavity or a die 102 mounted on a substrate 120 and including a cavity 114.

The foregoing detailed description of the invention has been presented for purposes of illustration and description, and is not intended to limit the invention to the disclosed form per se. Many modifications and variations are possible in light of the above teaching. The described embodiments have been selected in order to best explain the principles and practical applications of the present invention and to enable those skilled in the art to best utilize the present invention in various embodiments and various modifications suitable for the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto.

1 is a side view of a conventional semiconductor device of the prior art in which a pair of semiconductor dies are stacked for convenience;

2 is a side view of a conventional semiconductor device of the prior art in which a pair of semiconductor dies are stacked in an overlapping relationship and separated by a spacer layer.

3 is a side view of a conventional semiconductor device of the prior art in which a pair of semiconductor dies are stacked in an overlapping relationship and the upper die includes trenches along the lower edge of the semiconductor die;

4 is a bottom perspective view of a conventional semiconductor device of the prior art with the trench shown in FIG.

5 is a flow chart for forming a semiconductor die in accordance with an embodiment of the present invention.

6 is a plan view of a semiconductor wafer providing a plurality of semiconductor dies manufactured in accordance with an embodiment of the present invention.

7 is a plan view of a semiconductor die during manufacture.

8 is a perspective view of the semiconductor die of FIG. 7 during manufacture.

9 is a plan view of a semiconductor die including local cavities formed in the bottom surface of the semiconductor die.

10 is a bottom perspective view of the semiconductor die of FIG. 9 including local cavities formed in the bottom surface of the semiconductor die.

10A is a cross sectional view taken along line 10-10 of FIG. 10;

FIG. 10B is a cross-sectional view of another embodiment of a local cavity having an inclined surface in a shown position as in FIG. 10A.

11 is a side view of a semiconductor die including a local cavity embedded in a central portion of the bottom surface of the semiconductor die.

12 is a bottom perspective view of the semiconductor die of FIG. 11 including local cavities formed in the central portion of the bottom surface of the semiconductor die.

13 is a flow chart showing the manufacture of a semiconductor device according to the present invention.

14 is a perspective view of a semiconductor device including wire bonds located within local cavities of adjacent semiconductor dies during manufacture.

15 is a side view of a semiconductor device completed in accordance with an embodiment of the present invention.

16 is a plan view of a local cavity and wire bond configuration in accordance with an alternative embodiment of the present invention.

17 is an end view of a semiconductor device in accordance with an alternative embodiment of FIG. 16.

18 is a plan view of a local cavity and wire bond configuration in accordance with another alternative embodiment of the present invention.

19 is an end view of a semiconductor device in accordance with an alternative embodiment of FIG. 18.

20 is a plan view of a semiconductor device in accordance with an alternate embodiment that includes a local cavity in the central portion of the semiconductor die.

21 is a cross-sectional view of a semiconductor device in accordance with an alternative embodiment of FIG. 20.

FIG. 22 is a perspective view of an alternative embodiment showing a semiconductor device in manufacture including wire bonds located within local cavities of a spacer layer between semiconductor dies. FIG.

Description of the Related Art [0002]

100 wafer 102 semiconductor die

104: bond pad 110: local cavity

114: local cavity 120: substrate

122: contact pad 130: wire bond

140, 142: edge

Claims (15)

As a method of manufacturing a semiconductor device, (a) attaching a first semiconductor die to the substrate, (b) wire bonding a wire between the pad adjacent to the side of the first semiconductor die and the pad on the substrate, (c) forming a second semiconductor die, wherein a side of the second semiconductor die includes a local cavity occupying a portion of the entire side of the second semiconductor die, wherein two or three sides of the local cavity are located in the second semiconductor die; Forming a second semiconductor die in a plane parallel to the top surface of the die, surrounded by the second semiconductor die, the remaining side or remaining sides of the local cavity being open, and (d) attaching a second semiconductor die on top of the first semiconductor die, wherein the wire bonded wire in step (b) is disposed in the local cavity; A semiconductor device manufacturing method comprising the. The method of claim 1, The step (c) of forming a second semiconductor die comprising a local cavity at the side is a local formed on the bottom surface of the second semiconductor die and extending midway to the upper surface opposite the bottom surface of the second semiconductor die. Forming a second semiconductor die having a cavity. 3. The method of claim 2, (e) forming a die bond pad on the top surface of the second semiconductor die, wherein the position of the die bond pad in the top surface corresponds to the location of the local cavity in the bottom surface of the second semiconductor die. A semiconductor device manufacturing method. The method of claim 3, (g) forming a third semiconductor die on the side of the third semiconductor die, the third semiconductor die comprising a local cavity occupying a portion of the entire side, and (h) attaching a third semiconductor die on top of the second semiconductor die. And a wire connected in the step (f) is located in a local cavity of the third semiconductor die. The method according to claim 1 or 4, (j) forming a plurality of local cavities in one or more sides of the second semiconductor die, wherein all of all local cavities in one side of the second semiconductor die occupy a portion of the whole of one side A semiconductor device manufacturing method. The method of claim 5, (k) wire bonding a plurality of additional wires between the pad on the first semiconductor die and the pad on the substrate. The method of claim 6, (m) forming a plurality of die bond pads along the edge of the second semiconductor die on the top surface of the second semiconductor die, wherein the second formed in step (j) on the bottom surface of the second semiconductor die; The local cavity in the semiconductor die corresponds to the position of the die bond pad formed in the step (m) on the upper surface of the second semiconductor die. The method of claim 1, The step (c) of forming a second semiconductor die comprising a local cavity at the side includes forming a tunnel through a bottom portion of the second semiconductor die having openings at adjacent sides of the second semiconductor. A semiconductor device manufacturing method, characterized in that. With integrated circuits, At least one die bond pad formed on the active surface of the semiconductor die, One or more local cavities formed along one or more sides of the die within the non-active surface of the semiconductor die, One or more local cavities of each side of the semiconductor die occupy a portion of the entire side of the semiconductor die, and two or three sides of the local cavities are surrounded by the semiconductor die in a plane parallel to the active surface of the semiconductor die. And the remaining side or the remaining sides of the local cavity are open. 10. The method of claim 9, At least one die bond pad on the active surface of the semiconductor die corresponds to the location of at least one local cavity in the non-active surface of the semiconductor die. The method of claim 10, And a further cavity formed in the non-active surface and spaced inwardly from each side of the semiconductor die to receive the component. The method of claim 11, And the additional cavity is sized such that the additional component is received in the additional cavity without contacting the sidewall of the additional cavity. The method of claim 12, And wherein the local cavity comprises a tunnel through a bottom portion of the semiconductor die having openings at adjacent sides of the semiconductor die. The method of claim 13, And wherein the tunnel includes curved sidewalls. The method of claim 13, And wherein the tunnel comprises straight sidewalls.

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