KR100256306B1 - Stack multi chip module - Google Patents

Abstract

PURPOSE: A multi chip module is to improve its reliability by being inserted into a mother board of the system without need of a separate substrate and to shorten a production time and to minimize a size of the system. CONSTITUTION: A multi chip assembly(10) is formed by stacking at least three chip substrates by an adhesive tape. An upper substrate(20) is attached to top surface of the assembly whereas a lower substrate(20') is attached to lower surface of the assembly. A passivation layer(30) made by encapsulating a polyimide-based resin is formed on both sides of the assembly. Each of the chip substrates has at least three chips. A metal wire(11c) extending from a chip pad to one side edge is formed on each of the chip substrates. Each metal wire is isolated from each other by the first insulating layer and protected from exterior by the second insulating layer formed thereon. After the substrates are stacked, an end of the metal wire is electrically connected to each other by a separate metal wire(16).

Description

Stacked Multi-Chip Modules

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip module. In particular, a plurality of bare chips may be stacked up and down, and a substrate having contact pins may be attached to the top and bottom of the stacked chip and directly mounted on a motherboard of a system. The present invention relates to a stacked multi-chip module.

A module is a device in which several chips or packages are integrated on a single small substrate to increase the density and capacity of the device. Such a module is mounted to be electrically connected by inserting a pad provided on one side of a small board into a socket provided on a motherboard.

A typical example of such a module is shown in FIG. 1, which is briefly described as follows.

In the drawings, reference numeral 1 is a package, and 2 is a substrate. As shown, the package 1 is constructed by mounting its outlead 1a by soldering to the substrate 2. In the drawing, one package is mounted on a substrate, but in general, four to five or more packages are mounted on the substrate, and an electrical connection is made to one side of the substrate 2. Pads for the purpose is formed so that it can be plugged into a socket installed on the motherboard of the system, but is not shown in the drawings.

The module formed in this way can reduce the mounting area occupied on the motherboard by mounting and integrating several packages onto a single small substrate, while increasing its capacity by the number of packages mounted on the small substrate. Therefore, the system contributes to the miniaturization.

However, the general module as described above is modularized by mounting a plurality of packages on a board, but the foot print is too large to make the system small, and also solder joint cracks in mounting the package on a small board. And / or there was a problem that the reliability of the device is lowered by the occurrence of popcorn cracks.

In addition, in the conventional module, as the size of the package is gradually reduced, it is difficult to manufacture a via hole when manufacturing a PCB module, and there is a problem that a manufacturing cost increases due to limitation of design rules.

The present invention has been made to solve the above problems, it is not necessary to mount on a separate small substrate by stacking a plurality of bare chip strips up and down and modularized, such as conventional solder joint cracks and popcorn cracks It is an object of the present invention to provide a multi-layered multi-chip module capable of greatly increasing density and capacity while reducing the size.

1 is a cross-sectional view showing an example of a chip module using a conventional PCB substrate.

Figure 2 is a perspective view showing the structure of a stacked multi-chip module according to the present invention.

3 is a front view of FIG. 2;

4A and 4B are a plan view and a sectional view showing one chip in the wafer state;

5 is a cross-sectional view of a state in which a first insulating film is formed on a chip.

6 is a cross-sectional view of a state in which a pad portion of the first insulating film is etched and opened.

7A and 7B are a cross-sectional view and a plan view of a state in which a metal wiring is formed in an open portion of the first insulating film.

8 is a cross-sectional view of a state in which a second insulating film is formed on a chip on which metal wiring is formed.

9 is a plan view of a wafer that has undergone the process of FIG. 8.

Fig. 10 is a perspective view of a state in which three chips sawn in the wafer state of Fig. 9 are stacked;

FIG. 11 is a perspective view of a state in which substrates are attached to upper and lower surfaces of the stacked chip shown in FIG. 10. FIG.

12 is a perspective view of the protective plate is installed on both sides of the chip attached to the upper, lower substrate.

(Explanation of symbols for the main parts of the drawing)

10; multi-chip assembly 11, 12, 13; chip substrate

11a; chip 11b; chip pad

11c; metal wiring 14; first insulating film

15; second insulating film 16; metal wiring for wiring connection

20, 20 '; upper and lower substrates 21; contact pins

22; circuit pattern 30; protective film

According to the object of the present invention as described above, one side edge portion of the multi-chip assembly by stacking at least three or more chip substrates up and down, and a plurality of contact pins which are attached to the upper and lower surfaces of the multi-chip assembly, respectively, and are external connection terminals The upper and lower substrates are arranged at regular intervals and have circuit patterns connected to the contact pins. The multi-chip assembly includes metal wires extending from chip pads to one edges on respective chip substrates. A stacked multi-chip module is provided, which is laminated under an insulating film, and is formed by connecting metal wirings formed on respective chip substrates and circuit patterns of upper and lower substrates by metal wirings.

Here, a protective film is formed on both sides of the multi-chip assembly to protect the chip substrate and prevent moisture penetration, and an insulating film is laminated on the wiring connection portion of each chip substrate.

Such a multi-layered multi-chip module according to the present invention is formed by stacking several bare chips and modularizing them, and does not require a separate board, and can be mounted directly on a system motherboard. In addition, since a larger number of chips can be stacked than the existing modules, density and memory capacity can be increased, and a multi-functional module can be formed by alternately stacking RAM chips and logic chips. have.

Best Mode for Carrying Out the Invention Preferred embodiments of the present invention will now be described based on the accompanying drawings.

2 is a perspective view illustrating a structure of a stacked multi-chip module according to an exemplary embodiment of the present invention. FIG. 3 is a front view of FIG. 2, wherein reference numeral 10 denotes a multi-chip assembly, 20 and 20 'are upper and lower substrates, and 30 is a protective film. to be.

As shown, the multi-chip assembly 10 consists of three chip substrates 11, 12 and 13 stacked up and down by an adhesive tape or an adhesive resin (not shown). Although the drawing shows an example in which three chip substrates are stacked, the present invention is not necessarily limited thereto, and four or more chip substrates may be stacked.

The upper and lower substrates 20 and 20 ′ are attached to upper and lower portions of the multi chip assembly 10, respectively, and the passivation layer 30 is formed on both sides of the multi chip assembly 10. Here, the protective film 30 is formed by encapsulating a polyimide resin, and the protective film 30 protects the chip substrates 11, 12 and 13 and also penetrates moisture from the outside. It is formed for the purpose of preventing.

Hereinafter, a detailed description will be made with reference to FIGS. 4 to 12 attached to each component.

4A and 4B are a plan view and a cross-sectional view showing one chip in a wafer state, FIG. 5 is a cross-sectional view of a first insulating film formed on a chip, and FIG. 7A and 7B are cross-sectional views and a plan view of a metal wiring formed in an open portion of the first insulating film, and FIG. 8 is a cross-sectional view of a second insulating film formed on a chip on which the metal wiring is formed. 9 is a plan view of a wafer that has been subjected to the process shown in FIG. 8, FIG. 10 is a perspective view of three chips stacked in the wafer state of FIG. 9, and FIG. 11 is a top and bottom surfaces of the stacked chips shown in FIG. 10. 12 is a perspective view of a state in which a protective plate is installed on both sides of a chip having upper and lower substrates attached thereto.

As shown, each chip substrate 11, 12, 13 constituting the multi-chip assembly 10 includes at least three chips 11a. In each of the chip substrates 11, 12 and 13, metal wirings 11c extending from the chip pads 11b to the edges are formed. Here, the plurality of metal wires 11c are insulated from each other by the first insulating film 14, and are protected from the outside by the second insulating film 15 formed thereon. The metal wiring 11c may be formed by depositing copper, aluminum, chromium, nickel, or the like by the sputtering method, and an end thereof is exposed to the side of the chip substrate. The exposed ends of the metal wires 11c are electrically connected to each other by separate metal wires 16 after the stacks of the chip substrates 11 and 12 and 13 are stacked. The first insulating layer 14 and the second insulating layer 15 may be formed by spin coating a polyimide-based insulating agent.

Meanwhile, the upper and lower substrates 20 and 20 'are formed to have a length slightly larger than that of the chip substrates 11 and 12 and 13, and have a thickness of 2 mm or less. On the one side, several contact pins 21, which are external connection terminals, are arranged at regular intervals, and have a predetermined circuit pattern 22 connected to the contact pins 21. As shown in FIG. Here, the circuit pattern 22 is exposed to the opposite side of the contact pin 21, and the exposed end of the arc pattern 22 is formed inside the chip substrate 11 by the metal wiring 16. It is electrically connected with the metal wiring 11c formed in (12) (13).

Although not specifically illustrated, the metal wirings 11c of the chip substrates 11, 12, 13 and the circuit patterns 22 of the upper and lower substrates 20, 20 ′ are electrically connected to each other. An insulating film is formed in the metal wiring 16 part to insulate and protect the metal wiring connection part.

That is, according to the present invention, after the individual chips are stacked in a bare chip state without packaging, the upper and lower substrates having contact pins are attached to the upper and lower parts of the stacked chip, and the metal wirings and the upper and lower metals formed on the chip are attached. By connecting the circuit pattern of the lower substrate by a separate metal wiring to have an electrical signal transmission path, the manufacturing method of the stacked multi-chip module according to the present invention will be described in detail.

First, a polyimide-based insulation is coated over the entire surface of the wafer to form a first insulating film having a predetermined thickness. Herein, the wafer refers to a device in which a device is formed through a predetermined unit process. Then, the chip pad portion of the first insulating layer is etched and opened, and metal sputtered on the open portion to form a metal wiring. Then, the second insulating film is formed by coating an insulating material over the entire surface of the wafer on which the metal wiring is formed. Such a process is well illustrated in Figures 4-8.

After the process up to FIG. 8 is completed, a sawing process is carried out to separate the individual chip substrates 11, 12, and 13, and as shown in FIG. 9, at least three chips are cut. To form a chip substrate. Here, the chips included in one chip substrate may be three, four or more as shown in the figure.

Thereafter, the chip substrates 11, 12, and 13 separated as described above are stacked up and down with an adhesive to form the multi-chip assembly 10.

Then, the upper and lower substrates 20 and 20 ′ are attached to both surfaces of the multi chip assembly 10, and then a polyimide resin is encapsulated in both spaces of the multi chip assembly 10 to form a protective film ( 30).

After encapsulating both spaces of the multi-chip assembly 10, the metal wiring ends of the chip substrates 11, 12, 13 are on the upper and lower circuit patterns 22 of the substrates 20, 20 ′. After the process of the metal wiring 16 to be connected to the process, the surface is laminated with a polyimide resin to form an insulating film for wiring protection. The multi-chip module completed by such a process is shown in FIG. 12.

On the other hand, in configuring a stacked multi-chip module according to the present invention, each of the chip substrates may be configured as a RAM chip, and all may be configured as a logic chip, one is a RAM chip, the other is a logic It can also be configured as a chip. In this case, when all of the RAM chips are configured, the memory capacity can be greatly increased, and when the RAM chips and the logic chips are stacked, the multifunctional module can be configured.

As described above, the stacked multi-chip module according to the present invention is obtained by stacking several bare chips and modularizing them, and does not require a separate board, and can be mounted directly on the motherboard of the system. Therefore, since there is no room for solder joint cracks and popcorn cracks as in the prior art, reliability can be improved, and since the chips are stacked in a bare chip state without packaging, the manufacturing time can be shortened and the size can be minimized. In other words, it can contribute to the miniaturization of the system.

In addition, the stacked multi-chip module according to the present invention can be configured by stacking a larger number of chips than conventional modules, thereby increasing the density and memory capacity of the device, and alternately stacking RAM chips and logic chips. By doing so, the multifunctional module can be easily configured.

In the above has been shown and described with respect to a preferred embodiment for implementing a stacked multi-chip module according to the present invention, the present invention is not limited to the above-described embodiment, the scope of the invention as claimed in the claims below Without departing from the scope of the present invention, those of ordinary skill in the art can make various modifications.

Claims (6)

The multi-chip assembly formed by stacking at least three chip substrates up and down, and a plurality of contact pins attached to the upper and lower surfaces of the multi-chip assembly, respectively, which are external connection terminals, are arranged at regular intervals on one side and the contact pins. And a top and bottom substrate having a circuit pattern connected to each other, wherein the multi-chip assembly is formed with metal wires extending from one chip edge to one edge at each chip substrate and stacked under an insulating film. Stacked multi-chip module, characterized in that the metal wiring formed on the substrate and the circuit pattern of the upper and lower substrates are connected by a metal wiring. The multilayer chip of claim 1, wherein a protective film is formed on both sides of the multi chip assembly to protect the chip substrate and prevent moisture penetration, and an insulating film is laminated on the wiring connection portion of each chip substrate. module. The multilayer chip module of claim 2, wherein the protective film and the insulating film are formed of a polyimide resin. 3. The stacked multichip module of claim 2, wherein at least three or more chip substrates of the multichip assembly are RAM chips and / or logic chips. 5. The stacked multi-chip module of claim 4, wherein the chip substrate comprises at least three chips. The multilayer chip module of claim 1, wherein the upper and lower substrates have a thickness of 2 mm or less.

Images