KR101015342B1 - Data memory system - Google Patents

Abstract

The data memory system of the present invention stores at least binary digital data of " 1 " and " 0 " as the charge of the charge storage layer and uses the difference between the two charge amounts of the charge storage layer as the write bit and erase bit. And a nonvolatile memory cell array for collectively erasing pages in which a plurality of the memory cells are adjacent to each other, a code for correcting at least one bit of error data from information bits, and writing to the page. An error correcting code generating circuit for generating a code, an error correcting code decoding circuit for correcting an error from the error correcting code from the digital data recorded on the page, and restoring the information bits; Error correction code and an exclusive logical sum of a plurality of bits obtained by repeating the array of " write bit-erase bits " a plurality of times. And a code conversion circuit for outputting to the error correction code generation circuit.

Charge storage layer, memory cell, NAND-type EEPROM semiconductor device, MOS transistor, select transistor, NAND flash memory, drain electrode, channel potential

Description

DATA MEMORY SYSTEM

This application is based on the JP Patent application 2008-035269 (February 15, 2008), and claims the priority, The whole content is taken in here as a reference.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data storage system, and includes, for example, a semiconductor memory device, and is applied to a highly reliable system that can be repaired even if bad bits occur.

In the data storage system of the semiconductor memory device, for example, the charge injected by the tunnel current through the insulating film from the channel in the charge storage layer is used as information storage of the digital bits, and the change in conductance of the MOSFET according to the amount of charge is used. A nonvolatile semiconductor memory (EEPROM) has been developed for measuring and reading information. Among them, a NAND type EEPROM (NAND type flash memory) in which a plurality of memory cells are connected in series or in parallel to form a memory cell block can significantly reduce the number of select transistor gates than a memory cell, thereby making it possible to achieve higher density. In addition, in the NAND type EEPROM, the wells in which the memory cells are formed are commonized, so that the erase is collectively performed in a page composed of a plurality of memory cells, and the writing is performed for each memory cell. have. In the nonvolatile memory, unlike the DMM, it is possible to read a plurality of times without data destruction.

However, due to further progress of miniaturization and densification, when the capacitive coupling of adjacent cells increases, the threshold voltage margin between information bits decreases when the threshold value changes according to the charge amount of the charge accumulation layer of the adjacent cells. Particularly, in the NAND type flash memory, a write-in of which a bit to be kept in an erase state changes to a write bit occurs even in the erased bits that have been collectively erased by the data pattern during writing, which further lowers the threshold voltage margin. There was a problem.

As one solution to alleviate the problem of such error bits, for example, as disclosed in Japanese Patent Laid-Open No. 2005-243183 disclosed by the present inventors, there is a method of using error correction using an ECC (Error Correcting Code). . However, the erase threshold value and the write threshold value are increased due to capacitive coupling when the adjacent memory cell becomes the write threshold value from the erase threshold value, or a problem in which writing and writing occurs due to the pattern of the adjacent memory cells. On the other hand, the effective ECC construction method which grasped | ascertained the characteristic more is not disclosed.

More specifically, when the BCH (Bose-Chaudhuri-Hocquenghem) code and the RS (Reed-Solomon) code are used as the ECC, for example, in the BCH code, as the error correction code of t, the code length n is a natural number. It is fixed at 2 ^m -1, and the corresponding information bit number k0 is limited to k0 = 2 ^m- 1-mt. In the RS code, as an error correction code of t, one byte is m bits, the code length n is 2 ^m -1 (bytes), and the number of corresponding information bytes k1 is limited to k1 = 2 ^m -1 -2t. It is. As described above, when a BCH (Bose-Chaudhuri-Hocquenghem) code or the like is used as the ECC, it is conventionally used in a method such as a shortened code, and the degree of freedom is small due to the limitation of the code length.

As described above, in the conventional BCH short code creation method or the RS short code creation method only, a random single bit or a random constant is not a correction method that is strong against errors for a specific continuous pattern of code such as, for example, "010". It was an error correction method for number of bytes.

Therefore, the erase threshold value and the write threshold value are increased due to the capacitive coupling caused by the adjacent memory cell becoming the write threshold value from the erase threshold value, or the write-in occurs more by the pattern of the adjacent memory cell. As for the problem, the problem is not solved by grasping the characteristic of the problem. Therefore, conventionally, even when combined with a BCH code or an RS code, there is no disclosure regarding a method for constructing coding that is more effective.

As described above, in the conventional data storage system, a random single bit or a random bit is generated for randomization in which the erase threshold value and the write threshold value change due to capacitive coupling, and write-in occurs by a pattern of adjacent memory cells. It was a configuration to correct an error for a random number of bytes. As a result, for example, there was a tendency that a strong correction for an error that grasps more characteristics with respect to a specific soft pattern of code such as "010" cannot be performed.

A data storage system according to an aspect of the present invention stores at least two pieces of digital data of " 1 " and " 0 " as charges in a charge storage layer, and writes the difference between the two charge amounts in the charge storage layer. A nonvolatile memory cell array including a memory cell to be used as a plurality of memory cells to collectively erase pages comprising a plurality of the memory cells, and a code for correcting at least one bit of error data from information bits. An error correcting code generating circuit for generating an error correcting code to be recorded, an error correcting code decoding circuit for correcting an error from the error correcting code from the digital data recorded on the page, and restoring the information bit; Multiple times of the information bits or the error correction code and the " write bit-erase bits " Taking the OR, and a code conversion circuit for outputting the error correcting code generating circuit.

A data storage system according to an aspect of the present invention stores at least two pieces of digital data of " 1 " and " 0 " as charges in a charge storage layer, and writes the difference between the two charge amounts in the charge storage layer. And a nonvolatile memory cell array for collectively erasing pages in which a plurality of the memory cells are adjacent to each other, and a code for correcting at least one bit of error data from information bits. An error correcting code generating circuit for generating an error correcting code to be written to the data, an error correcting code decoding circuit for correcting an error from the error correcting code from the digital data recorded on the page, and restoring the information bits; Detecting the number of consecutive bit arrays of write bits / erase bits / write bits} of the information bits or the error correction code; Is an exclusive logical sum of a plurality of bits obtained by repeating a first counter circuit, an array of " input information bits or error correction codes ", " write bit-erase bits " a plurality of times, and write bits / erase bits / writes. The second counter circuit for detecting the number of consecutive bit arrays of bits and the number of the arrays of the output of the second counter circuit are smaller than the number of the arrays of the outputs of the first counter circuit. And a code conversion circuit which takes an exclusive logical sum of a plurality of bits obtained by repeating a bit or the error correction code} and the " write bit-erase bit " a plurality of times, and outputs the result to the error correction code generation circuit.

A data storage system according to an aspect of the present invention stores at least two pieces of digital data of " 1 " and " 0 " as charges in a charge storage layer, and writes the difference between the two charge amounts in the charge storage layer. A nonvolatile memory cell array having a memory cell used as a plurality of memory cells for collectively erasing pages in which a plurality of said memory cells are formed adjacently, and an error correction code for generating a correction code for correcting at least one bit of error data from information bits; An error correction code decoding circuit for correcting an error from the correcting code to restore the information bits, an error correcting code to which the correcting code input from the error correcting code generating circuit is added to the inputted information bits; Takes an exclusive OR of a plurality of bits by repeating an array of " write bit-erase bits " A code conversion circuit for generating data to be written, an output of the error correction code decoding circuit, and an exclusive logical sum of a plurality of bits obtained by repeating an array of "write bit-erase bits" a plurality of times to decode the error correction code. A sign inverse conversion circuit is provided.

A data storage system according to an aspect of the present invention stores at least two pieces of digital data of " 1 " and " 0 " as charges in a charge storage layer, and writes the difference between the two charge amounts in the charge storage layer. A nonvolatile memory cell array having a memory cell used as a plurality of memory cells for collectively erasing pages in which a plurality of said memory cells are formed adjacently, and an error correction code for generating a correction code for correcting at least one bit of error data from information bits; An error correction code decoding circuit for correcting an error from the correcting code to restore the information bits, an error correcting code to which the correcting code input from the error correcting code generating circuit is added to the inputted information bits; Takes an exclusive logical OR of a plurality of bits by repeating an array of " write bit-erase bits " A code conversion circuit for generating data to be written and digital data recorded on the page are input, and an exclusive logical sum of a plurality of bits obtained by repeating an array of " write bit-erase bits " a plurality of times is used to decode the error correction code. And a code counter conversion circuit comprising: a first counter circuit for detecting the number of consecutive bit arrays of write bits / erase bits / write bits of the input error correction code; and inputting the error correction code; And a second counter circuit for taking an exclusive OR of a plurality of bits by repeating an array of "write bit-erase bits" a plurality of times, and detecting the number of consecutive bit arrays of write bits / erase bits / write bits. If the number of arrays of outputs of the second counter circuit is smaller than the number of arrays of outputs of the one counter circuit, the error correction code and " An exclusive logical OR of a plurality of bits obtained by repeating the array of write bit-erase bits " a plurality of times is taken and written in the page.

[Comparative Example]

First, in order to compare with the data storage system which concerns on Example 1 thru | or 8 which concerns on this invention demonstrated below, the data storage system which concerns on a comparative example is demonstrated using FIG. 1 shows a circuit configuration of a memory cell element of a NAND type EEPROM semiconductor device according to a comparative example.

As shown in Fig. 1, nonvolatile memory cells M0 to M31 made of MOS transistors having charge storage electrodes are connected in series, and one end thereof is connected to a data transfer line written as BL through selection transistor S1. The other end is connected to the common source line written as SL through the selection transistor S2. In addition, each transistor is formed on the same p-type well 23. The control electrodes of the respective memory cells M0 to M31 are connected to data selection lines (hereinafter referred to as WL) written as WL0 to WL31. In addition, in order to select one memory cell block from a plurality of memory cell blocks along the data transfer line and connect it to the data transfer line, the control electrode of the selection transistor S1 is connected to the block select line SSL. The control electrode of the select transistor S2 is connected to the block select line GSL, forming a so-called NAND type memory cell block 49 (region of dotted line). Here, in this comparative example, the control wirings SSL and GSL of the selection gate are connected in cells adjacent to each other in the left and right directions of the paper by the conductors of the same layer as the charge accumulation layer 26 of the control wirings WL0 to WL31 of the memory cell element. It is formed. In this comparative example, the memory cell array structure connected to three data transmission lines BL1, BL2, BL3 will be described by way of example in order to make the problem easy to understand without overly complicated drawings. However, of course, the number of these parallel numbers is not three, but many more, for example, assume the structure which connected about 2100, 4200, 8400, 16800, 33600 in parallel.

Here, in order to explain the problem that the potential of the charge accumulation electrode is changed by the capacitive coupling of adjacent memory cells, for example, the threshold distribution of the M1a (?) Cells formed at the intersections of WL1 and BL2 is described as an example. For example, it is shown in FIG. In a multi-value memory cell having a charge storage layer, negative charge accumulates in adjacent memory cells, causing a problem that the threshold value rises through capacitive coupling between adjacent memory cells. In order to explain this problem, memory cells M2b (β) and M1b '(γ) adjacent to the BL direction and M1a (α) cells are connected in series adjacent to the S1 terminal side in the WL direction ( The threshold value variation in the case where ε) is changed from the erase state to the write state is shown in FIG.

In Fig. 2, (i) shows the erase threshold distributions of the memory cells α in which the adjacent memory cells β and γ on the adjacent data transfer line side and the adjacent memory cells ε on the word line side on the S1 side are all in an erased state. . In addition, in FIG. 2, in consideration of the four-state write state, for example, four-value memory is assumed, and the write threshold value 3, the write threshold value 2, and the write threshold value 1 are in order from the side where the threshold value is higher. It is assumed that the write threshold is set.

Further, in (ii), one memory cell? On the adjacent data transfer line side is in a write state, and the memory cell? Adjacent to the opposite side and an adjacent memory cell? On the word line side on the S1 side are erased. The erase threshold distribution of the memory cell alpha in the case of. In this case, since the adjacent memory cell 1 cell γ is in the write state, electrons are stored rather than the erase state. Therefore, compared with (i), the threshold value of the memory cell of alpha rises due to the capacitive coupling of adjacent memory cells. In addition, there is a problem that the threshold value rises and the upper hem distribution occurs as compared with (i) due to so-called writing, but this will be described in detail below. Here, in a NAND flash memory, a memory cell commonly connected to a data select line applies a potential of WL which is a data select line, for example, a potential of about 15 V or more and about 30 V or less, and a data transfer line ( BL) The potential is set to 0V, the source electrode and the drain electrode of the memory cell in which writing is selected are set to 0V, for example, and the channel potential is also set to 0V. On the other hand, the source electrode, the drain electrode, and the channel potential of the memory cell to be kept in the erased state without selecting the write, that is, the so-called unselected memory cell, are kept between 5V and 10V, for example, so that the data select line and the data transfer line are maintained. The write operation is prevented by reducing the potential difference of. In addition, in order to realize an unselected memory cell, the potential of the electrically connected BL is increased by more than 0V. In addition, in the NAND flash memory, in order to reduce the distribution width of the write threshold value, the potential of the BL is applied to the memory cell that reaches the lower limit threshold value (write verification threshold value) of the write by performing the verification read after the write operation. Is selectively raised from 0V to prevent additional writing.

Here, the case where the potential of WL1 is applied to a potential of about 15V or more and about 30V or less in order to keep the memory cell α connected to WL1 in an erased state and to write another memory cell connected to WL1 is considered. In this case, at the time of writing in the state of (ii), the source electrode, the drain electrode, and the channel potential of the memory cell γ to write are 0 V, and the source electrode, the drain electrode, and the channel potential of the memory cell α are about 5 V or more. It stays around 10V.

On the other hand, at the time of writing in the state of (i), the source electrode, the drain electrode, and the channel potential of the memory cell γ and the memory cell α are maintained at about 5V to about 10V. Therefore, in the case of writing in the state of (ii), a current flows from the source electrode or the drain electrode of the memory cell α to the source electrode or the drain electrode of the memory cell α, whereby the potential of the source electrode or the drain electrode of the memory cell α Falls. Alternatively, the potential of the source electrode and the drain electrode of the adjacent memory cell γ and the potential of the channel portion are lower in the case of (ii) than in (i), so that the channel portion of the memory cell? The voltage is also lower in the case of (ii) than in (i). As a result, in the case of (ii) as compared with (i), since the voltage of the channel portion of the memory cell α is lowered, writing and writing occurs in the non-selected memory cell, and the threshold of the memory cell α is generated. Value rise occurs. As described above, in the case of (ii) as compared with (i), a problem arises in that the threshold value is higher for the memory cell alpha in the erased state. In particular, in memory cells subjected to write and erase stress, charge traps are formed in the tunnel insulating film, and stress induced induced current (SILC) easily flows from the charge storage layer due to weak write stress. In this case, since the difference in the accumulated charge amount of the charge storage layer in the state of (ii) is larger than that in (i), an electric field stress is applied in the direction of the adjacent memory cell. The upper hem distribution of an erase distribution becomes easy to generate | occur | produce.

The problem that the above erase threshold value becomes large in the case of (ii) is that in (ii), one cell (β) adjacent to the adjacent data transmission line is in a write state, and the memory cell (γ) and S1 adjacent to the opposite side are in the write state. The same occurs in the erase threshold distribution of the memory cells α in the case where the adjacent memory cells? On the word line side in the erase state are in the erase state.

Further, in (iii), the erasing threshold of the memory cell α in the case where both of the adjacent memory cells? And? On the adjacent data transfer line side is in the write state, and the adjacent memory cell? On the word line side on the S1 side is in the erase state. Indicates a value distribution. In the case of (iii), since both of the memory cells β and γ adjacent to the BL direction are in the writing state, the electrons are stored more than in the erase state as compared with the case of (ii). Therefore, compared with (ii), the threshold value of the cell of alpha rises due to capacitive coupling of adjacent memory cells. In addition, the threshold value rises further compared to (ii) by the so-called write-in stress, so that the upper hem distribution occurs.

Here, the case where the potential of WL1 is applied to a potential of about 15V or more and about 30V or less in order to keep the memory cell α connected to WL1 in an erased state and to write another memory cell connected to WL1 is considered. In this case, at the time of writing in the state of (ii), the source electrode, the drain electrode, and the channel potential of the memory cells β and γ to write are 0 V, and the source electrode, the drain electrode, and the channel potential of the memory cell α are It is maintained at 5V to 10V. On the other hand, at the time of writing in the state of (ii), the source electrodes, the drain electrodes, and the channel potentials of the memory cells β, the memory cells γ, and the memory cells α are maintained at about 5V to about 10V. Therefore, in the case of writing in the state of (iii), a current flows from the source electrode or the drain electrode of the memory cell α to the source electrode or the drain electrode of the memory cell? The potential of the electrode is lower than in the case of (ii). Alternatively, the potentials of the source and drain electrodes of the adjacent memory cells β and the memory cells γ and the potentials of the channel portions are lower in the case of (iii) than in (i), whereby the memory cells α are formed by capacitive coupling in the BL direction. The voltage of the channel portion of also decreases. As a result, in the case of (iii) as compared with (i), since the voltage of the channel portion of the memory cell α is lowered, writing and writing occurs in the non-selected memory cell, and the threshold of the memory cell α is generated. Value rise occurs. In addition, even when compared with the case of (ii), since the potential of the channel portion of the memory cell adjacent to both sides in the BL direction is low, misfeeding is more likely to occur than in (ii). As described above, in the case of (iii) as compared with (ii), a problem arises in that the threshold value rises more with respect to the memory cell α in the erased state.

In addition, in Fig. 2 (iv), the memory cells α when the two adjacent memory cells β and γ are both in the write state on the adjacent data transfer line side, and the adjacent memory cells ε on the word line side on the S1 side are in the write state. Shows the erase threshold distribution. In the case of (iv), since the adjacent memory cell epsilon on the word line side on the S1 side is in the write state, electrons are accumulated more than in the erase state than in the case of (iii). Therefore, compared with (iii), the threshold value of the cell of alpha is further raised by the capacitive coupling of adjacent memory cells epsilon. Since the contribution of the capacitive coupling of memory cells in the diagonal direction with respect to WL and BL is less than 40% or less than 1% compared to the respective contributions of the capacitive coupling in the other BL and WL directions, in multi-value memory cells, this is (iv In the state of), the erase threshold value becomes a main pattern in which the distribution is expanded to be higher than in the case of (i) to (iii).

In addition, in the multi-value NAND flash memory, the data of the same multi-value level is conventionally written to the BL side from the cell on the SL side. For this reason, since the data of the same level is written in the adjacent memory cell? On the word line side on the S1 side after the memory cell?, The influence of the write threshold value of the adjacent memory cell? Is affected by the memory cell? You will receive this. In the case where the adjacent memory cells β, γ, and ε are in the write state, the problem that the threshold distribution of the memory cells α is expanded to the side higher than that when the adjacent memory cells are set to the erased state is that between adjacent memory cells. Because of the capacitive coupling, the memory cell α is a problem that also occurs for the write threshold. That is, in order to clarify the main problem of this invention, although description and illustration are abbreviate | omitted, also in the case of the write thresholds 1, 2, and 3 of FIG.

On the other hand, in (v) of FIG. 2, for example, after a write erase (commonly referred to as Endurance) of an arbitrary value of 10 to 100,000 times, for example, from 1 year to 85 degrees, The distribution of the write threshold value 1 in case of leaving, so-called, data retention for 10 years is shown. After the endurance, an electron trap is formed in the vicinity of the semiconductor substrate of the tunnel insulating film by tunnel current or an electric field stress after the endurance. The electron trap has a characteristic that the charge trapped in the tunnel insulating film is easier to be released than the charge accumulated in the charge accumulation region by allowing electrons to be trapped at the time of writing and then left for a long time. Therefore, as in (v), a problem arises that the threshold value is lowered for the electron emission than the threshold value immediately after writing. Of course, after endurance, an electron or hole trap is formed in the tunnel insulating film by tunnel current or an electric field stress, so that a leak current flows through this trap level. When this problem occurs, it is likely to be a distribution in which the hem is lined up below the threshold value as shown in the lower part of FIG. In any case, after charge retention, compared with the distribution immediately after writing, the writing threshold value decreases and the distribution tends to expand.

Here, it is assumed that the write thresholds 1, 2, and 3 are higher than the neutral threshold, but this is a reasonable assumption in the conventional NAND type semiconductor memory device. In this case, when the write threshold value 3 is high, for example, the electric field of the tunnel insulating film at the time of charge holding increases, so that the leakage current through the tunnel insulating film increases, and the data holding characteristic deteriorates. In addition, when the write threshold value 3 is high, the electric field during the writing or charge holding of the so-called interpoly insulation film between the charge storage layer and the control electrode increases, so that leakage current increases or dielectric breakdown occurs. The reliability of the cell is deteriorated. Therefore, the write threshold has an upper limit for maintaining the reliability of the memory cell. For example, the upper limit is set in the range of about 4V or more and about 8V or less. On the other hand, if the erase threshold value is low, the electric field during the erasing of the so-called interpoly insulation film between the charge storage layer and the control electrode increases, so that leakage current increases or dielectric breakdown occurs. Reliability deteriorates. Therefore, the erase threshold has a lower limit for maintaining the reliability of the memory cell. For example, the lower limit is set in the range of about -4V or less and about -10V or more. Since these are accompanied by deterioration of reliability of the memory cells, breakdown of insulation, and the like, it is necessary to set the memory cell to have all of the write threshold distribution and the erase threshold distribution within the range of the upper limit of the write threshold and the lower limit of the erase threshold. have. As shown in Fig. 2, the distribution of the erase threshold value is changed to the higher side due to capacitive coupling or write-in between adjacent memory cells, and a threshold value drop occurs in the characteristic after the write threshold value is maintained. As shown in v), when an overlap of threshold distributions occurs, a problem of an error bit that incorrectly detects or incorrectly corrects write bits as erase bits or incorrectly corrects erase bits as incorrectly detects write bits occurs. As described above, the upper and lower limit ranges in which the threshold value can be set are determined, and in order to narrow the write threshold distribution, it is necessary to narrow the write program voltage step. do. In addition, when the physical interval between adjacent memory cells becomes smaller and the capacitive coupling between adjacent memory cells becomes larger, the threshold value also changes with respect to the write amount 1 and 2 depending on the charge amount of the charge storage layer of the adjacent cell, and thus the threshold width. This increasing problem occurs. Therefore, in the high-density NAND memory cell in which the miniaturization of the memory cell is advanced, it is difficult to suppress the problem of this error bit only by the threshold distribution control.

In order to alleviate the problem of such an error bit, for example, as disclosed by the present inventors in the above-mentioned Patent Publication 2005-243183, a method of using error correction using an Error Correcting Code (ECC) is known. However, the erase threshold value and the write threshold value are increased due to capacitive coupling when the adjacent memory cell becomes the write threshold value from the erase threshold value, or a problem in which writing and writing occurs due to the pattern of the adjacent memory cells. On the other hand, it is not disclosed about the configuration method of ECC which grasps a characteristic further and is effective.

More specifically, when the BCH (Bose-Chaudhuri-Hocquenghem) code and the RS (Reed-Solomon) code are used as the ECC, for example, in the BCH code, as the error correction code of t, the code length n represents m. As a natural number, it is fixed at 2 ^m- 1, and the corresponding information bit number k0 is limited to k0 = 2 ^m- 1-mt. The RS code is an error correcting code of t, with 1 byte being m bits, the code length n being 2 ^m -1 (bytes), and the number of corresponding information bytes k1 limited to k1 = 2 ^m -1-2t. It is. When the BCH (Bose-Chaudhuri-Hocquenghem) code is used as the ECC, since the degree of freedom is smaller than the restriction such as the code length, a method such as a shortened code has been used.

Fig. 3A shows a method of a shortened code for a BCH code according to a comparative example.

First, as shown in Fig. 3A1, k bits of information bits smaller than the aforementioned k0 bits are prepared. Next, 1-bit " 0 " is added to (a2) to match the number of bits corresponding to the aforementioned k0 bits. Further, an information sequence to which "0" bits are added is BCH encoded, and as shown in (a3), an n-bit codeword is added to which parity serving as a check bit is added. Next, as shown in (a4), 1-bit " 0 " of the coded code words is removed, and a code word of (n-1) bits is stored in the nonvolatile memory. In this way, ((n-1), k (= k0-1)) BCH short codes are formed from the (n, k0) BCH codes. Here, the information bits are information bits as they are after the BCH code and are separated from the check bits. This feature is likewise present in the RS code.

However, as described above, in the BCH short code creation method or the RS short code creation method only, a random short bit or a random number of bytes is not corrected for a specific soft pattern such as "010". Error correction method. Therefore, the erase threshold value and the write threshold value are increased in the case where the adjacent memory cell becomes the write threshold value from the erase threshold value and rises due to capacitive coupling, or in the case where the write-in occurs more by the pattern of the adjacent memory cell. On the other hand, when the characteristic of this problem is grasped | ascertained and it combines with a BCH code or RS code, it is not a more effective method of the structure of coding.

As described above, in the data storage system according to the comparative example, the erase threshold value and the write threshold value are changed due to capacitive coupling, and randomization is performed on the problem of randomization in which write and write occur due to a pattern of adjacent memory cells. It is a configuration for correcting errors for a single bit or a random number of bytes. As a result, for example, it is disadvantageous in the point that the specific soft pattern of code | symbol, such as "010", can hardly correct an error which grasped | ascertained the characteristic more.

Hereinafter, some Example 1 thru | or Example 7 considered the best are demonstrated. In addition, in this description, the common reference numeral is attached | subjected to the part which is common across all drawings.

Example 1

Next, the data storage system and the error correction operation thereof according to the first embodiment of the present invention will be described with reference to Figs.

<1. Configuration Example>

First, the entire structural example of the data storage system which concerns on Example 1 is demonstrated using FIG. 4 shows a layout of a block diagram of a data storage system according to the first embodiment.

As shown, the data storage system according to the present example is constituted by the storage device 7 and the memory controller 5.

The portion enclosed by the dotted lines as the storage device 7 is formed on one semiconductor substrate as, for example, a NAND type flash memory. The portion surrounded by the dotted line as the memory controller 5 shows a circuit configuration corresponding to a so-called controller of a flash memory, and typically shows a circuit formed on a semiconductor substrate separate from the memory device 7, but of course You may form in the same semiconductor substrate. In this manner, for example, the memory controller 5 and the memory device 7 are formed in the same package, board, or card, thereby forming a data storage system.

The data input / output buffer 45 is connected by the data input / output buffer 101 of the flash memory controller 5 and the first internal I / O line.

Here, in all the embodiments of the present application, the memory cell is a memory cell that can be read out multiple times without involving data destruction. In addition, the specific structure of the memory cell block 49 is demonstrated below. In addition, according to the convention of the flash memory, the logic value of the erase state is " 1 " and the logic value of the write state is " 0 ". In addition, in the following all the embodiments, for the sake of simplicity, the threshold values of the binary memory cells are described unless otherwise described. However, in the case of multi-value memory cells, the embodiment can be applied. In this case, in a case where the threshold distributions for representing the bits of each data retention are arranged in order from the high side to the low side of the memory cell, any two adjacent threshold distributions a, b (a is greater than b). Low threshold distribution), the threshold distribution below a may be replaced by " 1 ", and the threshold distribution above b by " 0 ". Further, in the NAND type flash memory, a method of collectively erasing erase memory cells connected to the same data control line and collectively erasing in the NAND cell block 49 can be employed. Therefore, the distribution of the erase threshold value is 2V or more and 6V or less. Therefore, it becomes wider than the distribution width of the write threshold of 0.1V or more and 1V or less. Therefore, when the threshold value of any one of the adjacent memory cells β, γ, and ε is changed from the erase threshold value in FIG. 5A to the write threshold value, the influence of the threshold value change of the corresponding memory cell α is affected. Since it is the largest, it is preferable to replace the logic value of the erase state with "1" and the logic value of any other write state with "0" in the multi-value memory cell.

Next, a planar configuration example of the memory cell array will be described with reference to FIGS. 5A and 5B. 5A and 5B are equivalent circuits and plan views of the NAND cell block 49, respectively.

FIG. 5B shows a structure in which three cell blocks 49 of FIG. 5A are arranged in parallel. In particular, in FIG. 5B, only the structure below the control gate electrode 27 is shown in order to make the cell structure easier to understand. In Fig. 5A, nonvolatile memory cells M0 to M31 made up of MOS transistors having charge storage electrodes 26 are connected in series, and one end thereof is connected to a data transfer line written as BL through selection transistor S1. The other end is connected to the common source line written as SL through the selection transistor S2. In addition, each transistor is formed on the same p-type well 23. The control electrodes of the respective memory cells M0 to M31 are connected to data selection lines written as WL0 to WL31. In addition, in order to select one memory cell block from a plurality of memory cell blocks along the data transfer line and connect it to the data transfer line, the control electrode of the selection transistor S1 is connected to the block select line SSL. In addition, the control electrode of the selection transistor S2 is connected to the block selection line GSL to form a so-called NAND type memory cell block 49 (dotted region). Here, in the present embodiment, the control wirings SSL and GSL of the selection gate are connected to memory cells adjacent in the left and right directions of the paper by conductors of the same layer as the charge storage layers 26 of the control wirings WL0 to WL31 of the memory cell element. It is formed. Here, the memory cell block 49 may have at least one block selection line for SSL and GSL, and is preferably formed in the same direction as the data selection lines WL0 to WL31 for high density. In the present embodiment, an example in which 32 = 25 ^five memory cells are connected to the memory cell block 49 has been described. However, the number of memory cells connected to the data transmission line and the data selection line may be plural and divided by 2 ^n. It is preferable to address decode a block of a multi-value memory cell by adding 2 ⁿ +2 (n is a positive integer) between two or dummy memory cells between S2 and WL0, and between S1 and WL31.

6A and 6B, a cross-sectional configuration example of the memory cell array will be described. 6A and 6B are cross-sectional views taken along arrows BB 'and AA' in FIG. 5B. A BB 'direction cross section corresponds to a memory cell section cross section. 6A and 6B, for example, silicon having a thickness of, for example, 3 to 15 nm, in the p-type silicon region 23 having a boron impurity concentration of between 10 ¹⁴ cm ⁻³ and 10 ¹⁹ cm ^−3. Charge accumulation made of, for example, polysilicon containing 10 ¹⁸ cm ^-3 to 10 ²¹ cm ^{-3 of} phosphorus or arsenic through a tunnel gate insulating film formed of oxide film or oxy nitride film 25, 25 _SSL , 25 _GSL Layers 26, 26 _SSL , 26 _GSL are formed with a thickness of 10 nm to 500 nm. These are self-aligned with the p-type silicon region 23 on a region where, for example, the element isolation insulating film 24 made of a silicon oxide film is not formed. This is, for example, after depositing reference numerals 25 and 26 in the semiconductor region 23 as a whole, and then patterning and reaching the semiconductor region 23 until the semiconductor region 23 reaches, for example, 0.05 to 0.5 um. It can form by deeply etching and embedding the insulating film 24. Thus, since 25 and 26 can be formed in the whole surface in the plane without a level | step difference, the film forming with the more uniformity improved characteristic can be performed.

On this, for example, a silicon oxide film or an oxynitride film having a thickness of 5 nm to 30 nm, or a silicon oxide film / silicon nitride film / silicon oxide film or an oxide film containing silicon, hafnium, lanthanum and zirconium elements, a silicon oxide film and silicon For example, polysilicon or WSi (tungsten) in which impurity is added to phosphorus, arsenic, or boron 10 ¹⁷ to 10 ²¹ cm ^-3 through block insulating films 50, 50 _SSL , and 50 _GSL made of a laminated film from a nitride film. A control gate 27 having a stack structure of silicide) and polysilicon or a stack structure of W and polysilicon or a stack structure of NiSi, MoSi, TiSi, CoSi and polysilicon is formed to a thickness of 10 nm to 500 nm. The control gate 27 is formed up to the block boundary in the left-right direction of the paper in FIG. 5B so as to be connected to the adjacent memory cell blocks in FIG. 5B, and forms the data selection lines WL0 to WL31. In addition, the p-type silicon region 23 is capable of applying voltage independently of the p-type semiconductor substrate 21 by the n-type silicon region 22, thereby reducing the load of the boost circuit during erasing to reduce power consumption. In order to suppress, it is preferable. In the gate shape of this embodiment, since the sidewall of the semiconductor region 23 is covered with the insulating film 24, the gate electrode 26 is not exposed in the etching before forming the floating gate electrode 26. Coming below (23) can be prevented. Therefore, it is difficult to produce parasitic transistors in which the gate electric field concentration and the threshold value fall at the boundary between the semiconductor region 23 and the insulating film 24. In addition, since the phenomenon of lowering the write threshold value, so-called sidewalk phenomenon due to electric field concentration is less likely to occur, a more reliable transistor can be formed.

As shown in Fig. 6B, n-type gates are formed on both sides of these gate electrodes, for example, as source or drain electrodes with a sidewall insulating film 43 made of a silicon nitride film or a silicon oxide film having a thickness of 5 nm to 200 nm interposed therebetween. The diffusion layer 28 is formed. The diffusion layer 28, the charge accumulation layer 26, and the control gate 27 form a floating gate type EEPROM cell whose information amount is the amount of charge accumulated in the charge accumulation layer 26. , 0.5um or less and 0.01um or more. Examples of these source and drain n-type diffusion layer 28, for example, is formed between the phosphorus or arsenic, antimony, the surface concentration is 10 to 500㎚ 10㎚ depth such that the ¹⁷ ㎝ ^-3 to 10 ²¹ ㎝ ^-3. In addition, these n-type diffusion layers 28 are shared between adjacent memory cells, and a NAND connection is realized. In the figure, reference numeral 26 _SSL and reference numeral 26 _GSL are gate electrodes connected to block selection lines corresponding to SSL and GSL, respectively, and are formed in the same layer as the floating gate electrode of the floating gate type EEPROM. . The gate lengths of the gate electrodes 26 _SSL and 26 _GSL are longer than the gate lengths of the memory cell gate electrodes, and are formed to be, for example, 1 μm or less and 0.02 μm or more, thereby greatly increasing the on-off ratio between block selection and non-selection. We can secure and can prevent wrong entry and misreading.

Further, n-type diffusion layer (28 _d) which is a source or drain electrode formed on one side of the reference numerals 27 _SSL, for example, tungsten or tungsten silicide, titanium, titanium nitride, copper, or a data transmission line made of aluminum (36 (BL)) and is connected via a contact (31 _d).

Here, the data transmission line 36 (BL) is formed to the block boundary in the vertical direction of the paper in FIG. 5B so as to be connected to the adjacent memory cell block. On the other hand, n-type diffusion layer serving as the source or drain electrode formed on one side of the reference numeral 27 (GSL) (28 _S) is connected with the source line SL to be a via contact (31 _S). This source line SL is formed to the block boundary in the left-right direction of the paper in FIG. 5B so as to be connected to adjacent memory cell blocks. Of course, the n-type diffusion layer 28 _S may be formed as a source line by forming the block boundary in the paper left and right directions. As these BL contacts and SL contacts, for example, polysilicon, tungsten, and tungsten silicide doped with n-type or p-type, tungsten silicide, Al, TiN, Ti, and the like are filled to form a conductor region. Further, between the SL and BL and the transistor, for example, it is filled by an interlayer film 68 made of Si0 ₂ or SiN. In addition, the BL upper portion, for example, SiO _2, SiN or the insulating protective layer 37 made of polyimide or, although not shown in the figure, for example, W, the upper wiring is formed consisting of Al or Cu have.

As illustrated in FIG. 5A, the cell array 1 is configured by arranging memory cell blocks 49 in which nonvolatile memory cells are connected in series or in parallel. In order to sense the data of the data transfer line of the memory cell array 1 or to hold the write data, a sense amplifier circuit 46 is provided through the data transfer line select transistor. This sense amplifier circuit also serves as a data register, and is mainly composed of a flip-flop circuit. In addition, the sense amplifier circuit 46 is connected to the data input / output buffer 45. These connections are controlled by the output of the column decoder 48 which receives the address signal from the address buffer 47, writes the data supplied to the data input / output buffer into the memory cell array 1, and writes the data in FIG. 1 The internal I / O line can be read. In order to select the memory cells with respect to the memory cell array 1, specifically, the row decoder 3 is provided to control the data control lines WL0 to WL31 and the block selection gates SSL and GSL. .

The substrate potential control circuit 42 is provided in order to control the potential of the p-type substrate 21 (or p-type well) in which the cell array 1 is formed, and in particular, to be stepped up to an erase voltage of 10 V or more during erasing. It is preferably formed. Further, when data is written to the selected memory cells of the memory cell array 1, a circuit 41a for generating the write voltage Vpgm boosted up from the power supply voltage is formed. Apart from the Vpgm generating circuit 41a, the circuit 41b for generating the write intermediate voltage Vpass supplied to the unselected memory cell at the time of data writing, and the unselected memory cell at the time of reading data is supplied. An intermediate voltage Vread generating circuit 41c for reading out and a circuit Vref generating circuit 1 41d for applying the threshold determination voltage of the selected cell are provided. These are controlled by the control circuit 40 so that a necessary voltage output is applied to the data control line driver 2 in each state of writing, erasing, and reading. As Vpgm, a voltage of 6 V or more and 30 V or less, Vpass is a voltage of 3 V or more and 15 V or less, and Vread is a voltage of 1 V or more and 9 V or less. It is desirable to secure enough to reduce the read disturb. In addition, the Vref generation circuit 41 is set to the middle of each adjacent threshold value of the memory cell, for example, the separation threshold value of the threshold distribution of " 1 " and " 0 ". The data control line driver 2 also applies a switch circuit for applying the voltage output to the control gates WL0 to WL15, SSL, and GSL of the memory cells that need to be written or read out in accordance with the output of the row decoder 3. to be.

Further, in all the embodiments of the present application, the number of data bits read in a series of sequences is the number of data bits read in a series of sequences with m being a natural number and t being a natural number, [2 ^m-1 -t X (m-1) -1] and less than or equal to (2 ^m −t × ^m −1), at least (2 ^m −1) or more memory cells 49 may be connected to (a) of FIG. It is prepared in parallel in the left and right directions of the page b, that is, the direction in which the data selection lines extend, and used as one page. In addition, in order to obtain an effect by adding 2 to 6 bits of additional bits to the information bits, the characteristic of the present embodiment is that at least 4 or more is required for m to suppress the increase of the array area. m is used in 8 or more and 20 or less in NAND flash memory. Further, for a memory cell belonging to one page, for example, it is preferable to use a plurality of memory cells commonly connected to one data selection line because a plurality of memory cells can be simultaneously selected by one data selection. . By preparing a memory cell in this manner, for example, a bit error of t bits read into a series of sequences of the cell array 1 is detected using a Bose-Chaudhuri-Hocquenghem (BCH) code, and the position thereof is determined. Can be. Also in the case of the RS code, since the data in one byte are read out simultaneously, the memory cells 49 are prepared in parallel in the left and right directions of the paper in Fig. 5A or 5B, that is, the direction in which the data selection lines extend, as described above. We use as one page.

In addition, the input / output of the sense amplifier 46 is connected to the control logic 40 which controls reading, writing, and erasing of the memory cells. The control circuit 40 uses, for example, data supplied to the data buffer as a command input to control reading, writing, and erasing of the memory cells. Although not shown in the figure for simplicity, a control signal for controlling the operation of the sense amplifier and control signals sel1 and se12 are connected from the control circuit 40. In addition, the part enclosed with the dotted line shown with the reference number 7 has shown the memory device conventionally formed on one semiconductor substrate as a NAND type flash memory. Here, about each said structure, since a well-known circuit block should just be used, for example by Unexamined-Japanese-Patent No. 2002-150783, detailed description is abbreviate | omitted.

In addition, in order to make it easier to understand later, according to the convention, the data string before encoding is called an information bit, and the bit added after encoding is called a check bit. Both the BCH code and the RS code form a code by adding a check bit to the original information bit. As described in the prior art, the check bits are usually in the form added after the information bits in order to simplify the circuit construction of the sign and the decoding.

Here, the part enclosed by the dotted line 5 in FIG. 4 shows the circuit equivalent to the so-called controller of a flash memory, and normally shows the circuit formed on the semiconductor substrate separate from the memory | storage device 7, Of course, You may form in the same semiconductor substrate. For example, reference numerals 5 and 7 are formed in the same package, board, or card to form a data storage system. The data input / output buffer 45 is connected to the data input / output buffer 101 of the flash memory controller 5 by the first internal I / O line.

On the other hand, the external input / output (I / O) is connected to another data input buffer 111, and inputs address and data control information for writing / erasing / reading the flash memory. In addition, the flash memory controller 5 controls the data input / output of the input / output of the two data input / output buffers 101 and 111 by the controller control circuit 112. The information bits input through the external I / O from the data input / output buffer 111 are input to the code occurrence probability averaging first coding circuit 106. Here, the number of bits of the information bit inputted at the reference numeral 106 is k0 bit. The code appearance probability averaging first coding circuit 106 is, for example, to distribute the probability that "0" and "1" of the input data are equally distributed. As the reference numeral 106, for example, a period code generation circuit or an M series (Maxium length code) generation circuit having a period of a1 bit shorter than k bits may be used for the averaging bit mask generation circuit 110, for example. . The M sequence code thus generated is characterized by having bits of "0 " and " 1 " dispersed in M1 periods, and " 0 " and " 1 " Therefore, the information bits are divided in order for every a1 bit, take an exclusive logical sum with each bit of a1 of the generated M series, and output it to the circuit 104, and, for example, an appropriate increment for each WL or every block of a1. As a result, the cycle start position is changed. Or after generating a second M-series code having a length of a2 bits, not the period start position, further dividing the information bits in order every a1 bits, and taking an exclusive OR with each bit of a1 in the generated M-series, The bits are partitioned in order every a2 bits, and an exclusive OR is performed for each bit of a2 of the generated second M series. As a concrete example, since the raw polynomial of the 2-bit Linear Feedback Shift Register (LFSR) is x + 1, the exclusive OR of the 2nd bit (x) and the 1st bit (1) is 1 bit of the following code. The second bit is obtained by shifting the first bit from the first bit, whereby 2 ² -1 = 3 states of "10", "01", and "11" can be obtained. Since the four states by adding "0", which is a vector of 0, become M series, the information bits are divided in order every two bits, and the order of each data in the order "10 01 11 00 10 01 11 00 ....". You can take an exclusive OR with.

By doing in this way, the first coded information bits in which "0" or "1" are properly distributed even if they are all information bits of "0" or all "1" inputs are transmitted to reference numeral 104. As a result, even when information data is randomly supplied from the external I / O, the information bits are inputted to the reference numeral 104 with the probability P = 0.5 that is equal to "0" and "1", and thus the adjacent memory cell states of the memory cells. Can be made uniform. Of course, the averaging bit mask generation circuit 110 shares the same M-series circuit or the second M-series circuit in the decoding circuit 107, so that each bit of a1 and a2 of the M-series generated in the same way as the decoding circuit is generated. By taking an exclusive OR with, the decoding can be performed correctly.

In addition, the information bits averaged by "0" and "1", inputted at the reference numeral 104, are used by the adjacent memory cell disturbance reduction second code conversion circuit 104 to the information bits of which the disturbance by the adjacent memory cells is reduced. The flag is added to the bit string to be added to the error correction code generation circuit 102. Here, the reference numeral 102 may be, for example, a commonly known BCH code generation circuit or an RS code generation circuit. For example, since the present inventors can realize using the BCH coding circuit disclosed in Japanese Patent Laid-Open No. 2005-243183, the description is omitted here. Thereby, the error correction code output from the reference numeral 102 is stored in the nonvolatile semiconductor memory element 7 via the data buffer 101.

In addition, since the present invention is an encoding that reduces the capacity interference or the write-in problem between physically adjacent memory cells, the information bits of adjacent time series supplied to the nonvolatile semiconductor memory device 7 are well boundary and source shunt. Except for regions and the like, it is assumed that they are generally written in physically adjacent memory cells. It goes without saying that such coding is possible if proper physical-logical mapping is performed.

On the other hand, a code string that may contain an error read from the nonvolatile memory 7 is input to a circuit 103 that decodes an error correction code through the data buffer 101, thereby correcting the code error, Information bits with reduced disturbance by adjacent memory cells and bit strings with flags are added. As the reference numeral 103, a generally known BCH code decoding circuit or an RS code decoding circuit may be used. The BCH decoding circuit can be realized by, for example, using the BCH coding circuit disclosed in Japanese Patent Laid-Open No. 2005-23183, and is omitted here. Similarly, since the RS code is a kind of BCH code of multiple circles and 2 ^m circles (m is an integer), it is well known and obvious that a decoding circuit can be similarly formed.

Next, the information bits of which the disturbance by the adjacent memory cells are reduced and the bit string to which the flag is added are input to the neighboring memory cell disturb reduction second code inverse conversion circuit 105, and the second code decoding circuit 105 It is decoded by the information bits given the first code. In addition, the original information bits are decoded by inputting the information bits subjected to the first code into the first code decoding circuit 107. The output of this information bit outputs data from external I / O via the data input / output buffer 111.

The first code decoding circuit 107, as described above, takes an exclusive OR with the same M-series as those generated by the reference numeral 110 and used in the circuit 106, thereby being exclusive with the M-series in encoding and decoding. It is clear that by taking the logical sum twice, the original information bits can be recovered. In Fig. 9, for example, the input of the circuit 104 in various information bit patterns, and the state of the sequence in the middle, and also an example of output are shown. The position indicated by "...." is supposed to repeat the 4-bit pattern on the right side periodically. In general, when the input information bits are k bits, the probability of appearance in the circuit 106 is averaged, but it is necessary to consider the overall state that all information bits can take arbitrarily varying to "0", "1". have. That is, as long as it can be encoded by reference numeral 106 and decoded by reference numeral 107, 2 ^k states exist in k-bit information bits, and a combination of all 2 ^k × 2 ^k combinations exists between two adjacent word lines. The probability of appearance is roughly averaged in all states by the circuit 106. In addition, in all the embodiments below, the error correction code generation circuit 102, the adjacent memory cell disturb reduction second code conversion circuit 104, the code occurrence probability averaging first coding circuit 106, and the error correction code decoding circuit ( 103), the adjacent memory cell disturb reduction second code conversion circuit 105, first code decoding circuit 107, averaging bit mask generation circuit 110, " 01010101 .... 0101 "&Quot; 010 " counter 113, " 010 " symbol counter 108, " 101 " symbol counter 109, counter 116 after taking exclusive OR of " 010 " counter 112, " 10101010 .... 1010 " ), The counter 117, the counter 118, the counter 119, the page buffer 114 for rearranging information bits, and the page buffer 115 for storing data on one source line side are implemented in a hardware circuit. If the calculation processing time is not a problem, the so-called software, firmware, or a combination thereof may be used. Of course it is. In all the following embodiments, for the sake of simplicity, a case in which the number of information bits k bits is divided by an even number, for example, by 2 or by 4 is shown. In addition, in the case of the number of undivided bits, for example, a method of enlarging the information bits by adding "1" until it becomes a multiple of 4 and encoding them so as to divide them may be used. For example, in the case of " 10101 " having 5 bits of information, if it is " 10101 111 " (an enlarged coded portion with an underline added) of 8 bits, it becomes clear that two or four are divided codes. In addition, as a code to add, in order to prevent the generation | occurrence | production of the "010" pattern by an additional code, "1" is more preferable than "0".

<2. Error Correction Code / Decoding Behavior>

Next, the error correction code / decoding operation of the data storage system according to the first embodiment will be described with reference to Figs. A specific sequence of reference numeral 104 is shown in FIG. In this description, description will be made based on the sequence of FIG. 7 or FIG. 8.

In the second code conversion circuit 104, first, in the SE1, a "010" symbol counter 108 for counting the number of occurrences of the symbol "010" in the information bit for three consecutive bits, and a three-bit sequence for the "101" in the information bit. A " 101 " symbol counter 109 that counts the number of occurrences of the generated symbol is reset, and a flag 1 and a flag 2 indicating the state of encoding are reset. In the following, for example, the "abc" symbol indicates a contiguous 3 bit indicated by "abc" in an information bit or a sign.

Next, in SE2, the number of consecutive bits of "010" in the k-bit information bits is counted and stored in the "010" symbol counter 108. The number of consecutive "101" bits in the k-bit information bits is also counted and stored in the "101" symbol counter 109.

For example, as shown in Fig. 10, the "010" detection circuit inputs the shift register at the clock synchronized with the information bit from the beginning of the information bit, and easily combines the "010" detection circuit and counts it in the counter. It can be realized. In Fig. 10, Z- ¹ of reference numeral 208 denotes a one-bit time delay element of 1 bit, reference numeral 209 denotes an inverter, reference numeral 210 denotes a three-input AND gate. In addition, the information bits are inputted in time series from the information bit input in a series of information bits. In the unit time in which "010" is input in sequence, in the unit time in which "010" is last input, the "010" output is from "L" to "H", and in other cases, "L". . Therefore, this "010" output is synchronized with the unit time of the information bit input, and for example, the number of "010" of the information bits is triggered and counted in a stable portion of the logic value of the "010" output in the unit time. Can be counted. The count of " 101 " can be similarly performed. For example, the counter of Fig. 10 can be constituted by a generally known binary counter, and thus the details of the counter are omitted here. In addition, as a 1-bit unit of time delay element denoted by Z ⁻¹ of 208 of the present example, for example, a D-type flip-flop or a latch circuit is used, in particular, the clock input is " L " At 0 [V]) to "H" (here, Vcc for convenience), the output is confirmed, and after that the clock remains "H" or "L" whether it is "H" Can be easily achieved by using an edge trigger type flip-flop whose output does not change even if it changes from " L "

Next, in SE3, it is determined whether the value of the "010" counter of reference numeral 108 is greater than the first threshold value. Here, when greater than the first threshold, a sequence that takes an exclusive OR of the information bit and the first bit mask pattern "01010101 .... 0101" (that is, repeatedly generating "01" for k bits) in SE4. Is performed, the information bit is replaced, and the flag 1 is set. As the first bit mask pattern, " 10101010 .... 1010 " generated by repeatedly generating " 10 " for k bits may be used. In addition, the 1st threshold value considers (k / 2) -1 half of the largest number of "010" of FIG.9 (a1) and FIG.9 (c1) among the information bits, and k is 2 In consideration of the case of not dividing by 4, it is preferable to set {(k / 4) to an integer value} -1 to suppress the upper limit of the number of occurrences of the sign of "010" to a constant value.

In the case of performing SE4, in the SE5, the "010" symbol counter 108 counts the number of occurrences of the symbol "010" in the information bits, and the occurrence of the symbol "101" in the information bits. The counting " 101 " symbol counter 109 is reset, and a flag 1 and flag 2 indicating the state of encoding are reset. In SE6, the number of consecutive bits of " 010 " in k-bit information bits is counted and stored in the " 010 " The number of consecutive "101" bits in the k-bit information bits is also counted and stored in the "101" symbol counter 108.

Next, after joining the branch determined to be NO in SE3, it is judged in SE7 whether it is greater than the value of the "010" symbol counter 108 and the value of the "101" symbol counter 109. Here, when the value of the "010" symbol counter 108 is larger than the value of the "101" symbol counter 109, in SE8, all of the k-bit information bits are bit inverted, that is, the "0" bit is "1". Bit, "1" bit is changed to "0" bit, and flag 2 is set. Next, after joining the branch determined to be NO in SE7, the symbols corresponding to the flags 1 and 2 are added to the information bits in SE9.

(Sequence of Decoding Circuit 105)

8 shows a specific sequence of the decoding circuit 105 of the second code. In the reference numeral 105, first, in SE10, information corresponding to the flag 1 and the flag 2 added to the information bit is stored in, for example, a register or a temporary memory. Next, in SE11, after determining whether flag 2 is set, and if flag 2 is set, in SE12, all bits of the information bits of k bits are inverted, that is, "0" bits are "1" bits, and "1". Change the bit to the "0" bit and replace it with the information bit. Next, after joining the branch determined to be NO in SE11, it is determined whether or not Flag 1 is set in SE13. In SE13, if YES, i.e., flag 1 is set, an exclusive logical OR between the information bit and the first bit mask pattern "01010101 .... 0101" (that is, "01" has been repeated for k bits) is obtained. A sequence is taken and information bits and substitutions are made. This first bit mask pattern uses the same "1010101010 .... 1010" mask bits when "10101010 .... 1010" is generated by repeatedly generating "10" for k bits at the time of encoding 104. You can use

Here, the pattern in which the erase threshold value increases due to the increase in the threshold voltage of the adjacent memory cells shown in (iii) and (iv) in FIG. 2 of the comparative example occurs in the erase state. Since the cells β and γ adjacent in the BL direction are in the write state, they correspond to "010" as the bit string. Here, as shown in Figs. 9A to 9A4, in the configuration of the comparative example without the sequence of reference numeral 104, in the k-bit sequence of "01010101 .... 0101", "010" is [ (k / 2) -1], and the problem that the erase threshold value increases by the threshold voltage rise of the adjacent memory cell arises with a large probability. For example, one memory cell α overlaps with the write threshold value v of FIG. 2, the read level exceeds the threshold value determined as the write threshold value, and the erase bit is misrecognized as the write bit and is defective. If the probability is p0, p0 is sufficiently smaller than 1, so that a defect of [(k / 2) -1] × p0 may occur. 9 (a1) and 9 (c1) are the worst case patterns in which "010" occurs most in the comparative example. On the other hand, by using the sequence of reference numeral 104 of the present embodiment, the number of " 010 " exists in the data pattern inputted at reference numeral 104 as shown in Fig. 9A, but [(k / 2) -1] exists. By performing the sequence of SE3, the number of " 010 " before SE7 can be suppressed to {{k / 4) truncated to an integer} -1 or less. Because, in the branch of SE3, when going to SE4, the number of "010" is greater than {(k / 4) truncated to an integer} -1, and in the worst case, "010" is most densely arranged. Even in this case, " 01010101 .... 01010 " is occupied by consecutive bits of (k / 2) + 1 bit or more. Therefore, the number of bits in which the pattern other than "010", especially "000" exists, is at most smaller than (k / 2) bits. Therefore, when the information bit is taken as an exclusive OR in a mask of "01010101 .... 0101", the place where the "000" bit is inverted into a continuous bit of "010" and "010" increases is at most {(k / 4) is increased to less than or equal to the value} -1.

On the other hand, when "010" is taken as an exclusive logical OR from a mask with "01010101 .... 0101", the pattern of either "010" or "101" depending on the start position of the bit of "010". And an exclusive OR. Since these are converted into "000" and "111", respectively, the pattern of "010" which becomes a problem of all decreases to {or less of {(k / 4) cut off to an integer} -1 as a whole. Of course, using "01010101 .... 0101" in which "01" is repeated as a mask with the information bits is effective for reducing the pattern of "010" of the most information bits. However, for example, in the well contact or source shunt contact portion, the dummy memory cells are adjacent in the bit line direction, for example, between 1 and 16 between the memory cell for storing information and the well contact or source shunt contact portion. Dogs may be formed. For example, since the present inventor has described in detail about the structure of this dummy cell part, it abbreviate | omits here. In this case, in the dummy memory cell, since writing or erasing of the memory cell is not performed in accordance with the information data, in the comparative example, the end of the cell column for storing information adjacent to the dummy memory cell is "0" or "1". The problem of threshold value change caused by the adjacent memory cell described above is unlikely to occur. Therefore, for example, "01010101 .... 0101", which is a repetition of "01", or "10101010 .... 1010", which is a repetition of "10", is appropriate for each array section of a memory cell such as a well contact or a source shunt contact. It is of course possible to use either of them by switching, and the information bits are divided into each of the array partitions of the memory cell, and the number of " 010 " and " 101 " It is of course possible to reduce the probability that "010" appears more by attaching flags 1 and 2 indicated by the reference numeral 104 corresponding to the partial string. You may apply this to any Example of the Example mentioned later. As described above, when the number of " 010 " is larger than the threshold value 1, an exclusive OR is performed at " 01010101 .... 0101 " or " 10101010 .... 1010 " The number can be reduced to the value of {(k / 4) truncated to an integer} -1 or less, which is about half of the comparative example [(k / 2) -1] to the worst value. 1 unique feature. From the above, according to the sequence shown in FIG. 7, {(k / 4) is rounded down to an integer from {(k / 2) -1], which is the worst value of the comparative example, in the number of "010" in the comparative example} -1 It can be suppressed below. Of course, since the exclusive OR is taken in the bit mask with "01010101 .... 0101", the original information can be restored by taking the exclusive OR in the same bit mask after encoding. In addition, if the number of error correction symbols is t, decoding of the BCH code or RS code increases the amount of information processing proportional to almost two or more powers of t, resulting in a problem of decoding speedup. On the other hand, in the second coding circuit 104 and the second code decoding circuit 105, at most, in the coding and decoding, only the information processing amount which increases only about one power of the information bit length is required even if the information bits are long. If t is 3 or more, the information processing amount of the shift of the LFSR required for encoding the BCH code or the RS code, which has a much smaller information processing amount than decoding, is about the same. Therefore, for example, even in the case of a code length longer than 1000 bits, it can be converted in a short enough time for the conversion to the second code or the inverse conversion.

9A, 9B, 1C, 1D, and 1E show examples of inputting various information bits, the number of " 010 " and the number of " 101 " Next, the state after SE3 within the reference numeral 104 is shown in (a2), (b2), (c2) and (d2) of FIG. 9. In Figs. 9A and 9C, the number of "010" is greater than {(k / 4) of the threshold 1, which is rounded up to an integer} -1, and the branch of SE3 is "Yes". Then, in SE4, the flag 1 is set, and in Figs. 9A and 9C, the number of "010" in SE3 is equal to or less than the threshold value 1, and the branch of SE3 is "no". Next, the state before SE9 is shown in (a3), (b3), (c3) and (d3) of FIG. 9 at 104.

Here, the pattern in which the erase threshold value increases due to the increase in the threshold voltage of the adjacent memory cells shown in FIGS. 2 (iii) and (iv) of the comparative example is caused to occur in the erase state of the memory cell α. Since the cells β and γ adjacent in the BL direction are in the write state, they correspond to " 010 " as the bit strings, and the problem of the comparative example does not occur in " 101 " In addition, the bit string that becomes "010" in question is a bit inversion of "101". By comparing the number of "010" and the number of "101" in SE7, it is effective only by replacing these two types of patterns. The number of occurrences of 010 "can be reduced. Here, in Fig. 9 (d1) to (d4), an example in which flag 2 is set in SE8 is shown. As shown in (d1) of FIG. 9, in the pattern of information bits that repeat "0100", the number of (k / 4) "010" and the number of "101" exists. Therefore, after branching to the "no" side in SE3, in SE7, it is determined whether the counter 108 which counted the number of "010" is more than the counter 109 which counted the number of "101", and "Yes." Proceed to the branch of ". Next, by performing the whole bit inversion in SE8, the number of zero "010" and the number of (k / 4) "101" becomes, so that the number of "010" can be reduced eventually. Of course, it is determined in advance whether the counter 108 which counted the number of "010" in SE7 is larger than the counter 109 which counted the number of "101", and in the case of "no", bit inversion is not performed. In this case, the number of "010" does not increase.

As described above, by using the sequence of SE7 and SE8 of reference numeral 104 of the first embodiment, the number of "010" in the information bits has already been truncated before SE7 {(k / 4) to an integer}} Since the number of " 010 " is less than or equal to {(k / 4) to be an integer}}-1 or less before SE8, the number of " 010 " You can convert this into bits that do not occur.

Because, in the sequence from SE3 to SE6, each information bit only takes an exclusive OR with the mask pattern, so in circuit 106, the probability that "0" of each information bit will come out and "1" will come out. When this is averaged approximately equally, the probability that "0" of each information bit and the probability that "1" comes out of the information bits inputted at 104 are equal. Thus, in the branch of SE7, given all combinations of k powers of two of the information bits, the probability that the counter 108 will be larger than the counter 109 is equal to the probability that the counter 108 will be smaller than the counter 109. Will be the same. Thus, by performing SE7 and SE8, the counter 108 has the information bit string matching the counter 109, e.g., "010" in the remaining half except for the case of "01010111111111111 .... 1111". By reducing the probability of this occurrence, it is possible to effectively realize information bits in which fewer "010" occur.

Also, as a method of adding the flag 1 and the flag 2 to the information bits, a method of adding each flag to the information bit as two bits of continuous data has been described. This method selects that the state "010" does not occur in any of the states of flags 1 and 2, but of course, encoding other than this, for example, allocates the same 2 bits of flag 1, and flags 2 1 bit. May be assigned to the. In FIG. 9, the bits corresponding to flags 1 and 2 are aabb (a and b are "0" and "1" states corresponding to flags 1 and 2, respectively), but the order of bbaa, aab, bba, etc. May be added as a bit corresponding to the flag. Of course, the bits corresponding to this flag are not added before or after the information bits, but, for example, may be divided into two information bits and embedded in the information bits as bbaa. Of course, the information bits may be divided into three, and bb and aa may be embedded so as to fall between the three information bits.

After the error correction coding, the check bit (parity) bits may be divided into several, and may be rearranged (interleaved) so that flags composed of two or more identical bits such as aa and bb are sandwiched between the check bits. In this way, since the bit in contact with the flag consisting of two or more identical bits cannot be in the "010" pattern, the possibility of occurrence of the "010" pattern of the check bit portion can be reduced more.

9 (e1) to (e4) show an example of the worst pattern in which "010" occurs in this embodiment. As shown in (e1) of FIG. 9, when (k / 2) bits are repeated by "10" bits, and (k / 2) bits are repeated by "00", the "010" pattern The number is (k / 4) -1 and the number of "101" patterns is also (k / 4) -1. In this case, therefore, in the sequence of FIG. 7, although the flag 1 is reset and the flag 2 remains in the reset state, the sequence of SE4, SE8, and both of SE4 and SE8 is temporarily performed is shown in FIG. e2), (e3) and (e4). In this case, in all cases, the number of "010" patterns is (k / 4) or (k / 4) -1, and the number of "101" patterns is also (k / 4) or (k / 4) -1, From this, even if SE4 or SE8 is performed, the number of selections of the "010" pattern is (k / 4) -1, which is an example of the worst case pattern of the k-bit information bit "010" pattern. This worst case pattern can be further improved by the method described in the third embodiment.

In addition, the first embodiment does not require the addition of the counters 112 and 113, compared to the second and third embodiments described later, and has the advantage that the circuit scale can be further reduced and a circuit having a small area can be configured.

<3. Effect according to this embodiment>

According to the data storage system according to this embodiment, at least the effects of the following (1) to (2) are obtained.

(1) For example, it is advantageous for error correction which grasped | ascertained the characteristic with respect to the specific soft pattern of code | symbol, such as "010".

As described above, in the present embodiment, the number of worst-case states in which "010" appears effectively is simply added by adding only 3 bits to 4 bits and at most 2 bits as information for k bits of information bits. k / 2) -1] to {(k / 4) cut to an integer} -1 or less, that is, about half or less can be suppressed.

For example, as indicated by arrow Y1 in FIG. 29, when the number of symbols of "010" is about 100, compared with the comparative example, the worst case number in which "010" appears can be suppressed to half or less. .

Further, the number of occurrences of "010" in the information bits of the output of the second code conversion circuit 104 can be equal to or reduced than the number of "010" occurrences in the information bits that enter the second code conversion circuit 104. have. Therefore, regardless of the state in which k bits of information bits are ^2k , the threshold rise due to capacitive coupling of adjacent memory cells in the BL direction or in the worst-case pattern can be suppressed. In addition, since the upper limit of the increase in the code length for the addition of the flag bit, the increase in the information bit length k, can be suppressed at the upper limit of 4 / k. In the case of lengthening, in particular, the effect of suppressing the worst case number in which " 010 " appears is large, and even if the number of information bits k increases, the encoding and decoding increases at most in proportion to k bits. Can be encoded and decoded using Therefore, it is possible to prevent an increase in the write threshold value due to the capacitive coupling of adjacent memory cells, thereby reducing the electric field of the tunnel insulation film during charge retention, suppressing the leakage current through the tunnel insulation film, and deteriorating data retention characteristics. The problem of mitigation can be prevented. In addition, since the increase in the write threshold value can be prevented, the electric field during the writing or charge holding of the so-called interpoly insulation film between the charge storage layer and the control electrode can be suppressed. And the data retention characteristics and the reliability of the memory cells can be maintained. In addition, in the worst case pattern, the rise of the threshold value due to the write-in and the capacity-combination of adjacent memory cells in the BL direction can be suppressed, so that a margin of separation between the erase threshold value and the adjacent write threshold value can be secured. For example, the threshold separation margin between the write threshold 1 and the write threshold 2 or the write threshold 2 and the write threshold 3 can be ensured. The number of bits whose distribution of the erase threshold fluctuates to the higher side due to capacitive coupling or write-in between adjacent memory cells can be suppressed, and a drop in threshold value occurs in the characteristic after the write threshold value is maintained, and (iv) of FIG. When overlapping threshold distributions occur, as in (v) and (v), the problem of an error bit that incorrectly detects or miscorrects a write bit as an erase bit or incorrectly detects or miscorrects an erase bit as a write bit occurs. can do.

In addition, the upper and lower ranges of the erase threshold lower limit and the write threshold upper limit are determined by the reliability of the interpoly insulation film and the tunnel insulation film. In order to narrow the write threshold value distribution, it is necessary to narrow the write program voltage step. By using the present embodiment, the threshold value distribution can be secured widely, the writing step can be wider, and the writing speed can be further improved.

(2) It is advantageous for high speed operation.

In the first embodiment, the BCH code or the RS code is used as the error correction code. However, these codes read the entire code string including the check code at the time of decoding, calculate the error code and the occurrence point thereof, and perform error correction. Therefore, since it is necessary to output after correcting the first portion of the code, the code correction circuit 103 has a buffer of one code length, that is, one page stored in the nonvolatile semiconductor device 7 at a time. Connected. Since the page buffer needs to read and output data modified at high speed, the page buffer is formed of a volatile memory that can be read at high speed such as an SRAM or a shift register. Therefore, since the sequence SE4, SE6, SE8, and the decoding sequences SE12, SE14 of the second encoding of the present embodiment can be performed on the information bits copied on the page register, no new page register circuit area is required. It can be realized at high speed.

In addition, even if it is not a BCH code or an RS code as an error correction code, when the information bit and the check bit are separated and a so-called separated code in which the information bit is included in the codeword is used, the characteristics of the second encoding are maintained. . This is because the present embodiment has the effect of reducing the maximum number of " 010 " in the information bits, which is a feature that is maintained even in code words if it is a separated code. Therefore, for example, instead of the BCH code or the RS code, the code on the full difference may be used in the majority vote code, that is, the cyclic code that can be decoded by the majority vote logic. Alternatively, among the so-called Low-Density-parity-check (LDPC) codes, the present embodiment can be used as long as the information bits and the check bits are separated and the information bits are included in the codeword.

Example 2 (an example including counter circuits 112 and 113)

Next, the data storage system according to the second embodiment will be described with reference to FIGS. 11 to 14. Fig. 11 shows a block diagram of Embodiment 2 of the present invention.

This embodiment is substantially the same as the first embodiment, but takes an exclusive logical sum of the "01010101 .... 0101" bit mask and the information bits in advance, quantitatively compares and judges the result by counting the number of patterns of "010" as a result. The difference from the first embodiment is that the number of "010" bits is more surely reduced. In addition, the same code | symbol is attached | subjected to the same part or the same operation part as Example 1, and detailed description is abbreviate | omitted.

In addition, the difference in the configuration of the first embodiment and the second embodiment is as apparent when comparing Figs. 11 and 4, k-bit information bits and "01010101 .... 0101", that is, "01" k. It has a symbol counter 112 that counts the number of occurrences of a 3-bit contiguous symbol of " 010 " in a bit string that takes an exclusive OR of bit repetition. Also, a symbol counter for counting the number of occurrences of the 3-bit contiguous symbol of "010" in the bit string that takes an exclusive OR of k-bit information bits and "10101010 ... 1010", i.e., repeating k bits of "10" ( 113). Thus, for the four types of code conversion of SE4 and SE8 of the first embodiment, the number of " 010 " The probability of appearance of a 3-bit consecutive symbol of "010" is further reduced.

<Sequence of Error Correction Codes of Second Code Conversion Circuit 104>

12 shows a specific sequence of the reference numeral 104 of the second embodiment.

In the reference numeral 104, first, in the SE15, a "010" symbol counter 108 that counts the number of occurrences of the symbol "010" in the information bit, and the number of occurrences of the symbol "101" in the information bit, which are three bits in sequence. The " 101 " symbol counter 109 and the symbol counters 112 and 113 that count the numbers are reset, and a flag 1 and a flag 2 indicating the encoding state are reset.

Next, in SE16, the number of consecutive bits of "010" in the k-bit information bits is counted and stored in the "010" symbol counter 108.

The number of consecutive "101" bits in the k-bit information bits is also counted and stored in the "101" symbol counter 109. Further, the number of consecutive 3-bit symbols of " 010 " in the bit string obtained by performing an exclusive OR between k bits of information bits and " 01010101 .... 0101 " It stores in the counter 112. Further, the number of consecutive 3-bit symbols of " 010 " in the bit string obtained by performing an exclusive OR between k bits of information bits and " 10101010 .... 1010 " It is stored in the counter 113.

<Configuration example of counters 112 and 113>

For example, the structural example of the counter 112 and the counter 113 which concern on this example is shown like FIG. As shown in the figure, the counter 112 and the counter 113 are inputted to the shift register from the beginning of the information bit, and can be realized by combining the "000" detection circuit and the "111" detection circuit and counting them in the counter. . In Fig. 13, reference numeral 212 denotes a two-input AND circuit, and reference numeral 214 denotes a two-input 0R circuit. The circuits connected to the two counters 108 and 109 in FIG. 13 are the same as the circuits described in FIG. The information bits are inputted in time series in a sequence of information bits rather than information bit inputs. In Fig. 13, in the circuit written as the "000" output connected to the counter 112, the "000" output goes from "L" to "H" at a unit time in which "000" is sequentially input. Becomes "L". This " 000 " corresponds to a case where an exclusive logical sum is taken from a 3-bit consecutive information bit of " 010 " and a " 010 " mask in a " 01010101 .... 0101 " bit mask. Further, in the circuit written as "111" output connected to the counter 112, the output of "111" becomes "H" from "L" in the unit time input of "111" in order, and in other cases " L ". This " 111 " corresponds to a case where an exclusive logical OR is taken from a 3-bit consecutive information bit of " 010 " and a " 101 " mask in a " 01010101 .... 0101 " bit mask. Here, when the clock giving the information bits is divided by the 1/2 frequency divider 213, the output thereof is, for example, the x-th bit of the information bit, where "1" and "0" are even in an odd number of x-bits. Are output respectively. Therefore, the input electrically connected to the symbol counter 112 is, for example, (when the logic of the "000" output is "H" and the x bit is odd), and the "000" output. The logic is " H " and the x bit is an even number), which is a 3-bit sequence of " 010 " in an information bit and a bit string in which an exclusive logical sum of " 01010101 .... 0101 " In the case where the symbol is present, the last symbol of the three consecutive symbols is " H " in the input unit time, otherwise it is " L ". On the other hand, the input electrically connected to the symbol counter 113 is, for example, (when the logic of the "111" output is "H" and the x bit is odd) and ("000" output of the The logic is " H " and the logical sum of the case where the x-bit is even. This means that in the unit time at which the last symbol of the three consecutive symbols is input in the case where there are three bit consecutive symbols of "010" in the bit string in which the information bits and the exclusive logical sum of "10101010 .... 1010" exist, "H" ", Otherwise, it is" L ". Therefore, by synchronizing the outputs of these two-input OR circuits 214 with the unit time of the information bit input, for example, by triggering and counting when the logic value of the OR output is stable at the unit time, the " 01010101 ... The symbol counter 112 can count the number of consecutive bits of " 010 " in the bit string in which the exclusive logical sum of the .0101 ", i.e., " 01 " The symbol counter 113 can count the number of consecutive bits of " 010 " in the bit string in which an exclusive logical sum of bits and "10101010 .... 1010", that is, "10" is k-bit repeated. . For example, since the counter of FIG. 13 should just be comprised with the well-known binary counter, the detail of a counter is abbreviate | omitted here.

Next, in SE17, it is determined whether the minimum values of the counter 108 and the counter 109 are larger than the minimum values of the counter 112 and the counter 113.

Here, in the case of "Yes" in SE17, in SE18, a sequence that takes an exclusive logical OR of the information bits and the first bit mask pattern "01010101 .... 0101" (that "01" is generated by k bits repeatedly) is taken. Information bits and replacements are performed, and flag 1 is set.

Next, in SE19, it is determined whether the value of the symbol counter 112 is greater than the value of the symbol counter 113.

Here, when the value of the symbol counter 112 is larger than the value of the symbol counter 113, in SE20, all bits of the information bits of k bits are inverted, that is, "0" bits are "1" bits, and "1" bits. Is changed to the "0" bit, and flag 2 is set.

Next, in SE23, codes corresponding to flags 1 and 2 are added to the information bits.

On the other hand, if it is determined "NO" of SE17, it is judged in SE21 whether it is larger than the value of the "010" symbol counter 108 and the value of the "101" symbol counter 109.

Here, when the value of the "010" symbol counter 108 is larger than the value of the "101" symbol counter 109, in SE22, all of the k-bit information bits are bit inverted, that is, the "0" bit is "1". Bit, "1" bit is changed to "0" bit, and flag 2 is set.

Next, in SE23, codes corresponding to flags 1 and 2 are added to the information bits.

Through the above sequence, in the four cases in which the code conversion of SE4 and SE8 of the first embodiment is performed, the number of " 010 " The probability of appearance of a 3-bit consecutive symbol of " 010 " The decoding of the second code of the present embodiment may be omitted since the method described in Embodiment 1 can be used.

Here, the pattern in which the erase threshold value increases due to the increase in the threshold voltage of the adjacent memory cells shown in (iii) and (iv) in FIG. 2 of the comparative example is generated in the erase state. Since the cells β and γ adjacent in the BL direction are in the write state, they correspond to "010" as the bit string. Here, as shown in Figs. 9A to 9A4, in the configuration of the comparative example without the sequence of reference numeral 104, in the k-bit sequence of "01010101 .... 0101", "010" is [ (k / 2) -1], and the problem that the erase threshold value increases by the threshold voltage rise of the adjacent memory cell arises with a large probability. For example, one memory cell α overlaps with the write threshold value v of FIG. 2, the read level exceeds the threshold value determined as the write threshold value, and the erase bit is misrecognized as the write bit and is defective. If the probability is p0, p0 is sufficiently smaller than 1, and a defect of [(k / 2) -1] × p0 occurs.

Here, Fig. 14A shows an example in which the probability of generating a three-bit string of "010" can be made smaller in Example 2 than in Example 1. FIG.

As shown in Fig. 14 (a), in the data pattern inputted by the reference numeral 104 of the second embodiment, the number of occurrences of consecutive three-bit symbols of "010" is stored in the counter 108 (k / 4) -1. Number of consecutive three-bit symbols of " 101 " is stored in the counter 109, and k bits of (k / 4) -1, " 01010101 .... 0101 ", i.e., " 01 " The number of consecutive 3-bit symbols of " 010 " in the bit string obtained by the exclusive OR with the bit string is stored in the counter 112, and 0, " 10101010 .... 1010 " The number of consecutive 3-bit symbols of " 010 " in the bit string obtained by the exclusive logical sum is stored in the counter 113 and is one. Therefore, in the sequence of the reference numeral 104 of the first embodiment, the number of symbols for which "010" occurs in the output of the reference numeral 104 remains as (k / 4) -1, but the sequence of the reference numeral 104 of the present embodiment is used. Thus, the number of symbols for which "010" occurs in the output of the reference numeral 104 can be reduced to zero. Of course, the effect of (1) and (2) of Example 1 can also be obtained in a present Example.

Of course, in the comparison of the counters of the present embodiment, in the case of four kinds of mask bits and bit inversion patterns similar to those of the first embodiment, the number of occurrences of the three consecutive symbols of "010" is more accurately compared to the comparison of SE3. Since it is a comparison, for example, even if "010" of a comparative example generate | occur | produces the worst [(k / 2) -1] like FIG. 9 (a) and FIG. 9 (c), {( It is clear that k / 4) can be suppressed below the value} -1 cut out to an integer. For example, one memory cell α overlaps with the write threshold value v of FIG. 2, the read level exceeds the threshold value determined as the write threshold value, and the erase bit is misrecognized as the write bit and is defective. If the probability of p0 is set to p0, p0 is sufficiently smaller than 1, and the probability that a defect of [(k / 2) -1] × p0 of the comparative example occurs is [{(k / 4) cut off to an integer}} -1] x p0 can be reduced. An example of the worst case pattern in which the number of occurrences of the three consecutive symbols of "010" in the case of the second embodiment increases most is a bit string as shown in Fig. 9E.

Example 3 (an example further comprising a page buffer 114)

Next, a data storage system according to the third embodiment will be described with reference to FIGS. 15 to 19. First, the whole structural example of Example 3 of this invention is shown in FIG.

According to the third embodiment, in addition to the above-described second embodiment, the number of occurrences of the 3-bit continuous symbol of "010" can be reduced. The same reference numerals are attached to the same portions or the same operation portions as those of the first and second embodiments, and detailed description thereof is omitted. In the following description and drawings, it is assumed that input / output of k bits of information bits is performed in a time series, and the even-numbered bits are even-numbered bits and the odd-numbered bits are odd bits.

The difference in configuration between the second embodiment and the third embodiment is that it further has a page buffer 114 for rearranging even and odd bits of information bits, as will be apparent when comparing Figs. 11 and 15. . In the present embodiment, in addition to the second encoding in the second embodiment, the page bits 114 are used again, and the information bits of the first, third, fifth, ..., and (k-1) th odd numbers are After dividing the bit into 2nd, 4th, 6th, ..., and kth even bits, and outputting the odd information bits to the error correction code circuit 102 in order, the even information bits Are rearranged in order and output to the error correction code circuit 102, and in the case of decoding, the second code decoding circuit 105 rearranges them in reverse, thereby further reducing three consecutive symbols of "010". In the present embodiment, the characteristics assume that the total number of information bits is an even number of k bits, but the data transfer in the normal NAND input / output and the first internal I / O line in Fig. 15 is 1 byte (= 8). Since data input / output is performed in units of bits) × integer, there is no problem in practical use, and in the case of odd bits, an extension code may be formed by the method described in the first embodiment.

The page buffer 114 for reordering the information bits described above is connected to, for example, a second code conversion circuit 104 which reduces disturbance of adjacent memory cells, and further reduces the disturbance of adjacent memory cells. The second code inverse transform circuit 105 is connected. In addition, the page buffer 114 is composed of a page buffer of at least k-bit equal to the number of information bits, for example, a flip-flop of an n-bit shift register used in the error correction decoding circuit 103 is common. It can be used to reduce the circuit scale. Of course, when it is not necessary to reduce the circuit scale, it may be formed separately from the n-bit shift register used in the error correction decoding circuit 103.

<Specific Circuit Example of Page Buffer 114>

16A and 16B are specific circuit examples of the page buffer 114 of this embodiment. In order to make the drawing easier to understand, in Fig. 16A, the information bits are assigned to the 1st, 3rd, 5th, ..., the (k-1) odd bits and the 2nd, 4th, The portion of the circuit which is separated into the sixth, ..., and k-th even bits and output to the error correction code circuit 102 is omitted, and this portion is shown in Fig. 16B.

In addition, the transistors and wirings as Q2 and Q3 in FIG. 16A are applied to a substantial portion in FIG. 16B, so that the entire circuit configuration is achieved. In addition, as Q1 to Q8, an NMOS transistor is taken as an example, of course, if an input is inverted, a PMOS transistor may be sufficient and a bidirectional switch mentioned later may of course be used.

In Fig. 16A, a part of the n-bit shift register used in the error correction decoding circuit 103 is assumed, and the k-bit D flip-flops 208a and 208b are connected in series through Q1. This forms a k-bit shift register equal to the number of information bits. Here, D-type flip-flops are used as reference numerals 208a and 208b, but of course, a circuit may be formed by a latch circuit or another flip-flop circuit. Here, as a D flip-flop, the clock input rises from "L" (here, 0 [V] for convenience) to "H" (here, Vcc for convenience) at the time of pulse rise of the clock input of the table. At the moment, the output is determined to be the data input to the D input, and after that, the output does not change even if it changes from "H" to "L" whether the clock remains "H" or "L". An edge trigger type flip flop is used. The gate electrode of Q1 is commonly connected to the input written as S1. By setting S1, for example, from 0 V to Vcc and bringing it into a conduction state from the cutoff state, i is an integer of 1 to (k-1), and the reference numerals 208a or 208b of the (i + 1) bit connected in series are The output and the input of the i-bit reference numeral 208a or 208b are connected. That is, it operates as a k-bit shift register as a whole. In this case, the subscript of the first input and shifted bit is allocated to the smaller one in consideration of the operation as a shift register, and FF1, FF2, .... FF (k / 2), FF ( In FIG. 16 (a) and FIG. 16 (b), it describes in order k / 2 + 1), ... FF (k). In Fig. 16 (b), FF1, FF2, .... FF (k / 2) and FF (k / 2 + 1), .... FF (k) are shown again. The same flip-flop connection circuit as in (a) is used.

In addition, the bidirectional switch is formed by the NMOS at 215, the PMOS at 216, and the inverter 209. The bidirectional switch is a circuit in which the current terminals of reference numerals 215 and 216 are in the conduction state when the data output control inputs 1 or 2 are "H", and the shutoff state is in the case of "L". The voltage can be transferred between the current terminals of the NMOS 215 and the PMOS 216 without any problem. For example, when there is no problem in output reduction due to a threshold value, the NMOS transistor may be substituted. Here, by the element 217 taking exclusive OR with Q5 and the bidirectional switch and the bit mask string input, the output of FF1 is fed back to the input of FF (k), so-called linear feedback shift register. Resistor: LFSR). Therefore, with this k-stage shift register, k bits of the information bits are held in First-In-First-0ut (FIFO), and information is held in FF1, FF2, ..., and FF (k). Information can be output in order according to the clock input. Fig. 17A shows the operation of the circuit. First, sl is set to Vcc ("H"), / sl, p1, and bit mask string input to 0V ("L") at the time of reading and storing in order to operate as a k-bit series of shift registers.

When data is stored in the D-type flip-flop, first, the data output control inputs 1 and 2 are all set to "L" so that the output of the flip-flop 208 is not output to the data input / output line. After supplying the digital data of the first bit of Vcc ("H") or 0 V ("L") to the data input / output (I / O) line, the clock inputs 1 and 2 are both "L" to "H". Shall be. As a result, the digital data of the first bit is held in the leftmost flip-flop FF (k) in Fig. 16A. Next, after supplying the second digital data of Vcc ("H") or 0V ("L") to the data input / output (I / O) line, the clock inputs φ1 and φ2 are all changed from "L" to "H". do. As a result, the digital data of the first bit is transmitted and held in the second flip-flop FF (k-1) from the left in FIG. 16A, and the second digital data is in the left-most flip-flop FF (k). Is maintained. Subsequently, the digital data is sequentially supplied to the data input / output (I / O) line up to k [bit], and the clock is supplied so that the digital data is held in order from the flip-flop on the right side of FIG. k [Bit] can hold data.

Next, when reading data from the reference numeral 104, first, the data output control input 1 is set to "H", the data output control input 2 and the bit mask string input are set to "L", and the rightmost flip-flop FF1 Output the output to the data input / output line. As a result, the same data as that of the digital data of the first bit is output to the data input / output line. The clock inputs φ1 and φ2 are both set from "L" to "H". As a result, one-bit data is transmitted and held from the left to the right flip-flop. As a result, the same data as the data of the digital data of the first bit is output to the data input / output line. Subsequently, by setting all (k-1) clock inputs φ1 and φ2 from " L " to " H ", the data input / output (I / O) lines are arranged in order from the flip-flop on the right side of Fig. 16A. The data is output as is, and the data of k [Bit] can be output. As described above, it is clear that the data of k [bit] can be sequentially stored in the circuit of Fig. 16A and taken out in the order of storage.

In FIG. 16A, the gate electrodes of Q2 and Q3 are commonly connected to the input written as / Sl. The / Sl of the gate input of Q3 is set from 0 V to Vcc, for example, and the conduction state from the cutoff state is used, so that the D-type flip-flop of the odd bit of the k-bit shift register is written by the transistor written as Q3. 208b) is electrically connected in series to form (k / 2) shift registers. Specifically, through Q3, for example, i is an integer from 1 to (k / 2) -1, and the output of reference numeral 208b of the (2i + 1) th bit is output from the (2i-1) th It is connected to the input 208b of the bit. Further, the / Sl of the gate input of Q2 is set from 0V to Vcc, for example, and the conduction state from the cutoff state is used, so that the D-type flip of even-numbered bits of the k-bit shift register is passed through the transistor written as Q2. The flops 208a are electrically connected in series to form (k / 2) shift registers. Specifically, for example, i is an integer from 1 to (k / 2) -1, and the output of reference numeral 208a of the (2i + 2) th bit is determined by the reference numeral 208a of the (2i) th bit. It is connected to the input.

Here, by means of the bidirectional switch and the element 217 taking an exclusive OR with the bit mask string input, the output of FF1 is fed back to the input of FF (k-1), a so-called linear feedback shift register. Resistor: LFSR). In addition, Q4 allows the input of FF (k-1) to be connected to the data input / output (I / O) when / Sl is Vcc ("H"). Therefore, this (k / 2) stage shift register allows (k / 2) bits, which are odd bits of the information bits, to be First-In-First-Out (FIFO), and information to be converted into FF1, FF3, FF5, ...., the information held in FF (k-1) can be output in order according to the clock input .phi.2.

In addition, by the element 217 which takes an exclusive OR with the Q6 and the bidirectional switch and the bit mask string input of 217, the output of FF2 is fed back to the input of FF (k), a so-called linear feedback shift register. (Linear Feedback Shift Resistor: LFSR). Therefore, the (k / 2) -stage shift register allows (k / 2) bits, which are even bits of the information bits, to be First-In-First-Out (FIFO), and information FF2, FF4, FF6, ...., the information held in FF (k) can be output in order according to the clock input .phi.1. They can read and store information independently without mixing bits with even and odd bits.

17B and 17C show reading and storing operations of the circuit. First, in order to operate as a series of shift registers of (k / 2) bits, when reading and storing, / sl is set to Vcc ("H"), sl, p1, and bit mask string input is 0V ("L"). )

Here, description will be given from the writing of FIG. When storing odd bit data in a D flip-flop, first, data output control inputs 1 and 2 are set to "L" so that the output of the flip-flop 208 is not output to the data input / output line. After supplying the digital data of the first bit of Vcc ("H") or 0V ("L") to the data input / output (I / O) line, the clock input? 2 is set from "L" to "H". As a result, the first bit of digital data (corresponding to the first bit) is held in the second flip-flop FF (k-1) from the left in Fig. 16A. Next, after the second digital data (corresponding to one skipped third bit) of Vcc ("H") or 0V ("L") is applied to the data input / output (I / O) line, clock input φ2 is set to "." From L "to" H ". As a result, the digital data of the first bit is transferred to and held in the fourth flip-flop FF (k-3) from the left in FIG. 16A, and is transferred to the second flip-flop FF (k-1) from the left. Second digital data is maintained. Thereafter, by supplying digital data to the data input / output (I / O) line up to (k-1) [bit] and supplying a clock, every other one in the flip-flop of FIG. The data is retained, and data for all data (k / 2) bits of odd bits can be held.

When storing even-bit data in a D flip-flop, first, data output control inputs 1 and 2 are set to "L" so that the output of the flip-flop 208 is not output to the data input / output line. do. In addition, after supplying the digital data of the first bit of Vcc ("H") or 0V ("L") to the data input / output (I / O) line, the clock input? 1 is set from "L" to "H". As a result, the digital data of the first bit (corresponding to the second bit) is held in the first flip-flop FF (k) from the left in Fig. 16A. Next, the second input of Vcc ("H") or 0V ("L") of second digital data (corresponding to one skipped fourth bit) is applied to the data input / output (I / O) line, and then clock input φ1 is applied. From "L" to "H". As a result, the digital data of the first bit is transferred to and held in the third flip-flop FF (k-2) from the left in FIG. 16A, and the second digital data is stored in the left-most flip-flop FF (k). Is maintained. Thereafter, by supplying digital data to the data input / output (I / O) line up to k [bit] and supplying a clock, the digital data is held in every other order in the flip-flop of Fig. 16A. In addition, even-numbered bits of data (k / 2) bits can be held.

Next, reading of FIG. 17B is described. When reading odd bit data from the reference numeral 104, first, the data output control input 2 is set to "H", the data output control input 1 is set to "L", and the output of the rightmost flip-flop FF1 is inputted to the data. To the line. As a result, the same data as the digital data of the first bit of odd bits is output to the data input / output line. In addition, clock input phi 2 is made into "H" from "L". As a result, the output of FF3 is transmitted and held to FF1, and odd bit data is transferred and held to the flip-flop from left to right in order. As a result, the same data as the digital data (corresponding to the third bit) of the second bit of odd bits is output to the data input / output line. Subsequently, by setting the clock input? 2 from " L " to " H " altogether (k / 2-1) times, every other one in the flip-flop on the right side of FIG. The data is output in order, so that the data of all the odd (k / 2) bits of odd bits can be output in the 1st bit, 3rd bit, 5th bit, ... (k-1) bit. . At this time, since the clock input .phi.1 is not changed, the even bit data is kept unchanged.

On the other hand, when reading even-bit data from the reference numeral 104, first, the data output control input 1 is set to "H", the data output control input 2 is set to "L", and the second flip-flop FF2 on the right is made. Outputs to the data I / O line. As a result, the same data as the digital data of the first bit of even bits is output to the data input / output line. In addition, the clock input phi 1 is set from "L" to "H". As a result, the output of FF4 is transmitted and held to FF2, and even-bit data is transferred and held to the flip-flop from left to right in order. As a result, the same data as the data of the digital data (corresponding to the fourth bit) of the even bits is output to the data input / output lines. Subsequently, by setting the clock input? 1 from " L " to " H " altogether (k / 2-1) times, every other one in the flip-flop on the right side of Fig. 16A is connected to the data input / output (I / O) line. The data is output in order, and the data for all the even (k / 2) bits of even bits can be output in the second, fourth, sixth, ..., (k) bits. At this time, since the clock input .phi.2 is not changed, the odd bit data is kept unchanged.

On the left side of Fig. 17D, an exclusive logical sum of an odd bit data string held in the flip-flop 208b and a bit mask of, for example, "01010101 .... 0101" is taken, and an exclusive logical sum is obtained. A method of re-memorizing the flip-flop 208b while outputting the taken data is shown. In this case, the "01010101 .... 0101" input pulse serving as a bit mask is supplied to the bit mask string input in synchronization with the clock input.

First, the data output control input 2 is set to "H", the data output control input 1 is set to "L", and the output of the rightmost flip-flop FF1 is the first bit of the bit mask string input at the exclusive-OR element 217. Output to the data I / O line by exclusive OR with "0". As a result, the same data as the digital data of the first bit of odd bits is output to the data input / output line. In addition, clock input phi 2 is made into "H" from "L". As a result, the output of FF3 is transmitted and held to FF1, and odd bit data is transferred and held to the flip-flop from left to right in order. As a result, the exclusive OR element 217 takes an exclusive OR with the second bit " 1 " of the bit mask string input and outputs it to the data input / output line. Therefore, in this case, inverted data of digital data (corresponding to the third bit) of the second bit of odd bits is output to the data input / output line. Subsequently, by setting the clock input? 2 from " L " to " H " altogether (k / 2-1) times, every other one in the flip-flop on the right side of Fig. 16A is connected to the data input / output (I / O) line. The data is output in order, and the data of all the odd (k / 2) bits of odd bits is divided into 1 bit, 3 bit, 5 bit, ... (k-1) bit, and bit mask respectively. The exclusive ORs of the first, second, third, ..., (k / 2) bits of the column input are output in order. Finally, by setting the clock input φ2 of the (k / 2) th time from "L" to "H", the 1st bit, 3rd bit, 5th bit, ... (k-1) bit, The exclusive ORs of the 1st bit, 2nd bit, 3rd bit, .... (k / 2) bit of the bit mask string input are respectively FF1, FF3, FF5, .... It is remembered in flip-flops. At this time, since the clock input .phi.1 is not changed, the even bit data is kept unchanged. In this example, " 01010101 .... 0101 " is used as the bit string mask input, but of course, other patterns may be used. For example, by using a bit mask of " 11111111 .... 1111 ", the data obtained by bit inverting the odd bit data string held in the flip-flop 208b as shown in the left side of Fig. 17E is outputted. In the meantime, the method of re-memorizing the flip-flop 208b can be easily realized.

On the right side of Fig. 17D, the exclusive logical sum of the even bit data string held in the flip-flop 208a and the bit masks of, for example, "01010101 .... 0101" is taken, and the exclusive logical sum is taken. A method of re-memorizing the flip-flop 208a while outputting the taken data is shown. In this case, the "01010101 .... 0101" input pulse serving as a bit mask is supplied to the bit mask string input in synchronization with the clock input.

First, the data output control input 1 is set to "H", the data output control input 2 is set to "L", and the output of the second flip-flop FF2 from the rightmost side is set by the exclusive OR element 217 of the bit mask string input. Outputs to the data input / output line in an exclusive OR with the first bit "0". As a result, the same data as the digital data of the first bit of even bits is output to the data input / output line. In addition, the clock input phi 1 is set from "L" to "H". As a result, the output of FF4 is transmitted and held to FF2, and even-bit data is transferred and held to the flip-flop from left to right in order. As a result, the exclusive OR element 217 takes an exclusive OR with the second bit " 1 " of the bit mask string input and outputs it to the data input / output line. In this case, therefore, inverted data of digital data (corresponding to the fourth bit) of the even bits is output to the data input / output lines. Subsequently, by setting the clock input? 1 from " L " to " H " altogether (k / 2-1) times, every other one in the flip-flop on the right side of Fig. 16A is connected to the data input / output (I / O) line. Data is output in order, and the data for the even-numbered bits of all data (k / 2) bits is input to the 2nd bit, the 4th bit, the 6th bit, the ... (k) bit, and bit mask string input, respectively. The exclusive ORs of the 1st, 2nd, 3rd, ... (k / 2) th bits of are output in order. Finally, by setting the clock input φ1 of the (k / 2) th time from "L" to "H", the 2nd bit, the 4th bit, the 6th bit, ... (k) bit, and each bit The exclusive OR of the 1st bit, 2nd bit, 3rd bit, .... (k / 2) bit of the mask string input is reset to the flip-flop of FF2, FF4, FF6, .... FF (k). I remember. At this time, since the clock input .phi.2 is not changed, the odd bit data is kept unchanged. In this example, " 01010101 .... 0101 " is used as the bit string mask input, but of course, other patterns may be used. For example, by using a bit mask of "11111111 .... 1111", as shown in the right side of Fig. 17E, the data obtained by bit inverting the even-bit data string held in the flip-flop 208a is outputted. It is possible to easily realize the method of re-memory storing the flip-flop 208a. Of course, for this bit mask string input, for example, as described in the first embodiment, when the output of the averaging bit mask generation circuit 110 such as the M series is inputted, the sequence described in FIG. In addition, the code occurrence probability averaging first coding circuit 106 and the first code decoding circuit 107 can be realized.

In Fig. 16B, the gate electrode of Q7 is commonly connected to the input written as p1. By setting p1 of the gate input of Q7, for example, from 0V to Vcc and bringing it into a conducting state from the cutoff state, the transistor written as Q7 makes i an integer from 1 to k / 2, and FF (k / 2 + The output of i) is connected to the input of FF (i). Further, with i being an integer from 1 to k / 2-1, the output of FF (iH) is connected to the input of FF (k / 2 + i). As a result, as shown in FIG. 17 (f), in the adjacent memory cell disturb reduction second code inverse transform circuit, the original odd number of information bit strings separated into even bit strings and odd bit strings in encoding is used. -Even-Odd-Even .... Inverted to bit stream and output.

In Fig. 17 (f), when the input of p1 is " H ", data that is odd bits before the second encoding is sequentially input to FF1, FF2, ..., FF (k / 2), and FF (k / 2 + 1), FF (k / 2 + 2), FF (k), FF1, FF (k / 2 + 1) Indicates that data can be read from the page buffer in the order of FF2, FF (k / 2 + 2), that is, odd even order.

Here, as the output after decoding the error correction code, data that was odd bits before the second encoding is sequentially input to FF1, FF2, ..., FF (k / 2), and FF (k / 2 + 1), FF. (k / 2 + 2), ... FF (k) is inputted data to the adjacent memory cell disturb reduction second code inverse conversion circuit 105 in order, and the data which were even bits before the second encoding is sequentially inputted into the page buffer. It is assumed that it is input to (114). First, in order to operate as a series of k-bit shift registers, p1 is set to Vcc ("H"), sl, / sl, and bit mask string input as 0V ("L") at the time of reading and storing.

The odd-even-odd-even number before the second encoding from the reference numeral 104.... First, the data output control input 1 is set to "H", the data output control input 2 is set to "L", and the output of the first flip-flop FF1 on the right side is output to the data input / output line. As a result, the same data as the digital data of the first bit of odd bits is output to the data input / output line. In addition, the clock inputs phi 1 and phi 2 are set from "L" to "H". Thereby, the output of FF (k / 2 + 1) is transmitted and maintained at FF1, the output of FF2 is transmitted and held at FF (k / 2 + 1), and is electrically connected by the current terminal of Q7. Is transmitted and maintained in flip-flops for one bit. As a result, the same data as the digital data of the (k / 2 + 1) th bit is output to the data input / output line. In addition, the clock inputs phi 1 and phi 2 are set from "L" to "H". As a result, the same data as the digital data of the second bit is output to the data input / output line.

Subsequently, by setting the clock input φ1 from " 1 " to " H " altogether (k-1) times, FF1, FF (k / 2 + 1), FF2, before reading to the data input / output (I / O) line. Data is output in the order of FF (k / 2 + 2), ..., FF (k / 2), FF (k). In the case where the odd bit data and the even bit data are separated and arranged in time series by the second encoding, the inverse conversion is performed to restore the odd-even-odd-even bit strings of the original code and output them in time series. It must have been one.

As described above, when the page buffer 114 of the present embodiment is used, at least (information bit-1) x 3 + 8 transistors and two inverters, and two two, for an error code decoding circuit using a conventional shift register. It is clear that only the input exclusive OR element can realize the code conversion circuit of the information bits for the second encoding necessary for the third embodiment.

<Sequence of Second Encoding Circuit 104>

Next, the concrete sequence of the 2nd coding circuit 104 which concerns on Example 3 is demonstrated using FIG.

In the reference numeral 104, first, the flag 1, the flag 2, and the flag 3 are reset in the SE24, and the first, third, and fifth bits of the page buffer 114 are .... (k-1) Reads information bit data of the number of (k / 2) bits of odd bits of the bit. In this method, the odd bits may be outputted to the counter by, for example, outputting odd bits of information by the method on the left side of FIG.

Next, in SE25, information bit data of the number of (k / 2) bits of the even bits of the 2nd, 4th, 6th, ... k-th bits is read out from the page buffer 114. For example, an even number of information bits may be output after the odd bit output by the method on the right side of FIG. 17B and input to the circuit of FIG.

Next, in SE26, for example, the " 010 " symbol in the information bit is counted in the counter 108, the " 101 " symbol is counted in the counter 109, and the odd and even bits of k-bit length are added. The counter 112 counts consecutive "01010101 .... 0101", that is, "01" symbols repeatedly arranged from the beginning of the bit, and the "010" symbol which takes an exclusive OR. Also, the counter 113 counts the " 10101010 .... 1010 ", i.e., " 10 "

This may be done by inputting the information bits of SE24 and SE25 into the information bit input of FIG.

Next, in SE27, the values of the symbol counter 108, symbol counter 119, symbol counter 112, and symbol counter 113 are copied into registers a, b, c, and d, respectively.

Next, in SE28, in the page buffer 114 of the third embodiment, the first bit, the second bit, the third bit, ..., the k-bit from the page buffer are odd even odd even order, that is, normal Reads k bits of information bit data in the order of. This may be done by outputting the information bits by the method on the right side of Fig. 17A.

Next, in the SE28, the counter 108 counts, for example, the "010" symbol in the information bits arranged in k-bit lengths of the 1st bit, the 2nd bit, the 3rd bit, and the ... kth bit. And counting " 101 " symbol at counter 109, " 01010101 .... 0101 ", i.e., " 01 " repeatedly arranged from the beginning of the bit and " 010 " Count). Also, the counter 113 counts the " 10101010 .... 1010 ", i.e., " 10 " The information bit output of SE28 may be input to the information bit input of FIG.

In SE30, the contents of the counters 108, 109, 112, and 113 and the registers a, b, c, and d are compared, respectively, to determine whether it is a counter or a register that contains the minimum contents.

As a result, next, in SE31, it is determined whether the minimum value is the counters 108, 109, 112, and 113 rather than the registers a, b, c, and d.

Here, when the counters 108, 109, 112, and 113 have a minimum value condition, the same sequence as that of SE17-SE22 is performed while the flag 3 is reset.

Subsequently, instead of SE23, in SE33, the code corresponding to the flag 1, the flag 2, and the flag 3 is added to the information bit (k-bit) and output to the error correction code generating circuit of reference numeral 102.

Next, if there is no condition on the counters 108, 109, 112, and 113 as the minimum value, flag 3 is set in SE32.

Next, the information bits are divided into odd bits and even bits, for example, the first bit, the third bit, the fifth bit, .... (k-1) bits, the second bit, the fourth bit, The sixth bit is used as the information bit for the array of the k-th bit, and the same sequence as in SE17-SE22 is performed.

Here, in SE34, it is determined whether the minimum value of the register a and the register b is larger than the minimum value of the register c or the register d.

Here, in the case of "YES" in SE34, in SE35, flag 1 is set, odd bits of information bits and the first bit mask pattern "01010101 .... 0101" ("01") are set from the beginning of the bit (k / 2) a sequence of exclusive ORs of bits generated repeatedly) is stored in the page buffer 114 again. What is necessary is just to perform this sequence to the left of FIG.17 (d).

Next, in SE36, the exclusive logical sum of the even bits of the information bits and the first bit mask pattern " 01010101 .... 0101 " (" 01 " generated by repeating (k / 2) minutes from the beginning of the bits). Sequence is taken and stored in the page buffer 114 again. This may be performed by performing the sequence on the right side of FIG. 17D.

Next, in SE37, it is judged whether or not the register c in which the value of the symbol counter 112 is stored is larger than the register d in which the value of the symbol counter 113 is stored. Here, in the case of "YES" in SE37, in SE38, all bits of the information bits of k bits are inverted, that is, "0" bit is changed to "1" bit, "1" bit is changed to "0" bit, and flag 2 is changed. Set. For example, the sequence of FIG. 17E may be performed.

On the other hand, if it is determined "NO" of SE34, it is determined in SE39 whether the value of register a in which "010" symbol counter 108 is stored is greater than the value of register b in which "101" symbol counter 109 is stored. Is done. In case of "Yes" in SE39, in SE40, all k bits of information bits are bit inverted, that is, "0" bit is changed to "1" bit, "1" bit is changed to "0" bit, and flag 2 is set. . For example, the sequence of FIG. 17E may be performed.

Subsequently, the SE41 reads the first, third, ..., and (k-1) th bits of odd data that has entered the flip-flop at the reference numeral 208b in the information bit, and the error correction coding circuit 102 ) The output of this information may be performed, for example, in the sequence on the left side in Fig. 17B.

Further, in SE42, the even data entered in the flip-flop of the reference code 208a in the information bits is read out in the second, fourth, ..., and k bits, and output to the error correction code generation circuit 102. . The output of this information may be performed, for example, in the sequence on the right side of Fig. 17B.

In SE43, the symbols corresponding to the flags 1, 2, and 3 are output to the information bits at 102.

In addition, as in the first embodiment, as a method of adding the flag 1, the flag 2, and the flag 3 to the information bits, there is a method of adding each flag to the information bit as two bits of continuous data. This method selects that the state "010" does not occur in any of the states of flags 1 and 2, but of course, any other encoding, for example, any one of flags 1, 2, 3 is the same 2 bits. The method of assigning and assigning the remaining one flag to 1 bit may be sufficient. This means that the bits corresponding to flags 1, 2, and 3 before or after the information bit are aabbcc (a, b, and c are "0" and "1" states corresponding to flags 1, 2, and 3, respectively). It is also possible to add, as bits corresponding to the flags, those whose order numbers are appropriately replaced, such as ccbbaa, aabbc, or ccbba. Of course, the bits corresponding to this flag are not added before or after the information bits, but, for example, may be divided into two information bits and embedded in the information bits as in ccbbaa. Of course, the information bits may be divided into four, and aa, bb, and cc may be embedded so as to fall between four information bits, respectively. In addition, after error correction coding, the check bit (parity) bits may be divided into several parts and rearranged (interleaved) so as to sandwich a flag composed of two or more identical bits such as aa, bb, and cc between the check bits. In this way, since the bits on both sides of the flag composed of two or more identical bits cannot be in the "010" pattern, the possibility of occurrence of the "010" pattern of the check bit portion can be reduced more.

<Sequence of Decoding of Second Code Inverse Conversion Circuit 105>

Next, the specific sequence of decoding of the 2nd code inverse conversion circuit 105 of this Embodiment 3 is demonstrated using FIG.

In the second code inverse conversion circuit 105, first, in SE44, information corresponding to the flag 1, the flag 2, and the flag 3 added to the information bit is stored in, for example, a register or a temporary memory.

Next, in SE45, after determining whether flag 2 is set, and if flag 2 is set, in SE46, all bits of information bits of k bits are inverted, that is, "0" bits are "1" bits, and "1". Change the bit to the "0" bit and replace it with the information bit.

Next, after joining the branch determined to be NO in SE45, it is judged in SE47 whether flag 1 is set.

If "YES", i.e., flag 1 is set in SE47, the exclusive logical sum of the information bit and the first bit mask pattern "01010101 .... 0101" (that is, "01" is repeated for k bits) in SE48. Sequence is taken and information bits are replaced. This first bit mask pattern uses the same "10101010 .... 1010" mask bits when using "10101010 .... 1010", which is generated by repeatedly generating "10" for k bits at the time of encoding 104. You can use

Next, after joining the branch determined to be NO in SE47, it is determined whether or not Flag 3 is set in SE49.

In addition, when flag 3 is set, odd data before the second encoding is sequentially input to FF1, FF2, ..., FF (k / 2) in SE50, and FF (k / 2 + 1), FF. Since even data before the second encoding is sequentially input to (k / 2 + 2), ..., FF (k), FF1, FF (k / 2 + 1), FF2, FF (k / 2 + 2). ), That is, odd even number before the second encoding, data is read from the page buffer and output to the first code decoding circuit 107. For example, the sequence of FIG. 17F may be used for this.

If the flag 3 is not set, the first, second, third, ..., k-bit, odd-numbered, odd-numbered, even-numbered order from the page buffer 114, that is, k in the normal order The information bit data of the bits may be read out and output to the first code decoding circuit 117.

Through the above sequence, the number of "010" in the information bits after each conversion is counted in advance and quantitatively compared to the eight cases in which the code conversion of the third embodiment has been performed. It is reducing the probability of the appearance of 3bit consecutive symbols.

Here, in the third embodiment than in the first and second embodiments, the probability that a sequence of "010" three-bit symbols can be generated can be made smaller with reference to Fig. 20A. FIG. 20A shows a case where a bit string as shown in FIG. 9E, which is an example of the worst case pattern in which the number of occurrences of the three consecutive symbols of "010" in the case of Embodiment 2, increases most is shown. . In this case, odd bits and even bits are divided into 1st bit, 3rd bit, 5th bit, .... (k-1) bit, 2nd bit, 4th bit, 6th bit, .... k By rearranging bit by bit, the information bits of " 10101010 .... 1010 " of the (k / 2) bits and " 00000000 .... 0000 " of the (k / 2) bits of FIG. Since the rearrangement is performed by the information bits of "11111111 .... 1111" of (k / 4) bits and (00000000 .... 0000 "of (3k / 4) bits of Fig. 20A, The number of occurrences of "010" can be reduced to zero. As a result, the data corresponding to FIG. 20A are rearranged, and the flags 1, 2, and 3 are reset, reset, and set, respectively. As a result, an example of the code string output to the error correction code generation circuit 112 is shown in Fig. 20A3. In this way, the number of occurrences of "010" in the information bits including the flag can be reduced to zero. In addition, in this time, in order to simplify description, the case where the whole bit inversion or the information bit and the exclusive logical sum of "01010101 .... 0101" are not taken is explained, but this time is the all bit in the code | symbol of FIG. Even when the inversion, the exclusive bit of the information bits, and " 01010101 .... 0101 " are taken or both are performed, the number of occurrences of " 010 " can be set to zero as in the sequence of the third embodiment. This is suitable for the case of the information bits of "10101010 .... 1010 11111111 .... 1111" instead of "10101010 .... 1010 00000000 .... 0000", for example.

Therefore, in k bits of information bits more than 16 bits in general, by using this embodiment, the number of occurrences of the worst "010" is at most {(k / 6) truncated to an integer} -1 or less. It can be reduced to a point. This is because, in the same manner as in the discussion of the first and second embodiments, it is assumed that the number of "010" in the information bits subjected to the code conversion in the third embodiment is larger than {(k / 6) truncated to an integer} -1. do. In this case, even when "010" is arranged at the most densely, "01010101 .... 010" is occupied by (k / 3) + 1 bit or more consecutive bits. Therefore, the number of bits of the pattern other than "010" is at most (2k / 3) -1 bit or less. Here, the pattern "010" is increased by an exclusive OR with "01010101 .... 010", and the largest pattern of the increase number per partial code length is "00000000 .... 0000". Therefore, in the case where the information bit and the exclusive OR of "01010101 .... 01" are taken, the location of {(k / 6) truncated to an integer} -1 at most where the worst "010" occurs. The minimum partial code pattern to be limited to "00000000 .... 0000" is [(k / 3) -1] bit length, and "01010101 .... 010" is (k / 3) +1 bit. An abnormally continuous bit (hereinafter referred to as a continuous bit a pattern) is obtained. Therefore, in order to satisfy the above-described assumption, the overlapping of "0" of one bit at the end in the a pattern is considered, and all k bits of information bits, except for the continuous bit a pattern, remainder (k / 3) + 1 bit. In the following number of bits, there is a need for a combination of information bits having a larger number of "010" in the second encoding of the third embodiment than {value of truncated {(k / 6) to an integer} -1}. Here, from the discussion of the encoding of Fig. 20A in the second and third embodiments, the odd bits and the even bits of the third embodiment are the first bit, the third bit, the fifth bit, ... (k -1) The sequence for rearranging the bit, the second bit, the fourth bit, the sixth bit, the ... k-bit is a sequence that performs bit inversion of the sign of the first and second embodiments and " 01010101 .. It is clear that each of the eight types of states can be performed independently of a sequence that takes an exclusive logical sum of a .0101 "bit mask and an information bit, and is represented by flags 1, 2, and 3, respectively. In Fig. 20A, only the even-numbered odd bit rearrangement allows the continuous bit a pattern to reduce the number of occurrences of "010" to zero. Therefore, in order to satisfy the above assumption, in the number of bits of (k / 3) + 1 bit or less except for the continuous bit a pattern, in particular, in the even odd bit rearrangement, {(k / 6) becomes an integer. It is necessary to be a pattern in which the continuous pattern of "010" increases rather than the truncated value} -1. In the even odd bit rearrangement, the pattern in which the "010" pattern increases has a pattern of "0x1x0x" (x is either "0" or "1"), and particularly in the even odd bit rearrangement, most "010" The pattern in which the pattern increases in the even odd bit rearrangement becomes a repeating pattern of "00110011 .... 001100". Another variation is a pattern in which the repetition pattern of "00110011 .... 001100" is bit inverted, the exclusive logical sum of "01010101 .... 0101" is applied to the repetition pattern, and both are applied. do. The bit string at the right end of FIG. 20B1 corresponds to it, and the second (k / 3) bit of the code of FIGS. 20B2, B3, and B4 is the second code of the third embodiment. The pattern change in the case of processing is shown. In this case, in FIG. 20B3, only a minimum of (k / 6) -2 "010" occurs. In particular, it should be noted that in the combination of the bit inversion described in the second embodiment and the exclusive OR of "01010101 .... 0101", three consecutive bits of "010" do not occur in the "00110011 .... 0011" portion. do.

Here, in general, in order to increase the "010" pattern from {{k / 6] to an integer}}-1 by rearrangement, at least (k / 3) + 4 bits or more "00110011 .. ..001100 "is required. Except for duplication of two bits of " 00 " at the end of the continuous bit a pattern, the rest except for the continuous bit a pattern requires at least (k / 3) + 2 bits or more. Therefore, since the assumption that the number of "010" is greater than {(k / 6) truncated to an integer} -1 among the information bits subjected to the code conversion according to the third embodiment is contradictory, the information subjected to the code conversion according to the third embodiment The number of " 010 " in the bit is equal to or less than {(k / 6) truncated to an integer} -1.

In addition, the bit inversion of the second embodiment is applied to "00110011 .... 0011", the exclusive OR of "01010101 .... 0101" is applied to the repeating pattern, and both are applied to "0011". Since it becomes a circulation pattern, for example, "01100110 .... 0110", similarly at most (k / 6) -1 or less "010" generate | occur | produces.

In the above, even if the sign conversion in Example 3 of FIG. 20 (b1) is performed, the number of "010" is an example many. In this case, the number of " 010 " can be suppressed to (k / 6) -2, and the number of occurrences of the worst "010" is at most {(k / 6) truncated to an integer} -1 or less It can be reduced to the point of. The code of the third embodiment is likewise applied to the code of Fig. 20B1 with an exclusive OR of all the bit inversions, the information bits of the second embodiment, and " 0101010 .... 1010 " By this, at most, the number of occurrences of "010" can be set to "010" equal to or less than the value {(k / 6) truncated to an integer} -1 at most.

In addition, when FIG. 20 (c1) includes the pattern of "010", and takes an exclusive logical sum with "0101010 .... 1010" with all the bit inversions and the information bits, or both are performed. FIG. 11 shows an example where the frequency of occurrence of "010", which occurs almost identically to the pattern of "010", is high. The values of the registers a, b, c, d and the counters 108, 109, 112, and 113 are also shown on the right. This pattern is a 4-bit repetition of "0100" or "0001", and is a pattern which cannot reduce the number of occurrences of "010" even in even-numbered odd bit rearrangements. Since the number of "010" is invariant in the time series inversion of the sign, it is clear that the repetition of "0010" or "1000" in consideration of the time series inversion also becomes the same count number. This pattern also performs the sequence of Example 3, so that similarly to the above, the number of occurrences of "010" is at most {(k / 6) truncated to an integer} -1 or less, here, (k / 8) It can be set to "010" or less, and the pattern (b) of FIG. 20 is a pattern in which the number of "010" patterns increases. In this way, in the consecutive bits of "01010101 .... 0101" or "10101010 .... 1010", the frequency of occurrence of "010" occurs about (bit length / 2) -1, but the symbol of "010" Subsequently, in the case where a code is created by inserting another bit, for example, in a continuous bit of "01000100 .... 0100", "010" decreases to the maximum (bit length / 4). Therefore, the number of generated bits per bit of the partial information of "010" is "01010101 .... 0101" or "10101010 ..." when the "010" is distributed and arranged like the pattern of FIG. Compared to the case where .1010 "continuous bits are generated by the encoding of the third embodiment, the length of the continuous bits is 1/2 or less when the length of the continuous bits is longer than 16 bits.

On the other hand, the upper limit of the number of occurrences of "010" in Examples 1 and 2, i.e., the value {{k / 4) is truncated to an integer} -1 value and the number of occurrences of "010" in Example 3, respectively. The ratio of the upper limit value, that is, the value {(k / 6) is truncated to an integer}-1 is 2 times or less when k is 16 bits or more. In addition, when k is 20 bits or more, it becomes smaller than twice. Therefore, when "010" is distributed and arranged, when k is 16 bits or more, it becomes less than the upper limit of the number which the worst "010" occurs, compared with the case where "10101010 .... 1010" is arranged continuously. When k is 20 bits or more, it becomes smaller.

As described above, according to the third embodiment, at least the same effects as in the above (1) to (2) can be obtained.

From the above, by the second sign conversion in the third embodiment, the number of occurrences of the "010" pattern can be suppressed to the value of {(k / 6) truncated to an integer} -1 or less at the worst. Therefore, by performing the operation of Example 3, the number of occurrences of "010" worst than Example 1 or 2 can be reduced to the location of {(k / 6) truncated to an integer} -1 at most. have.

For example, as indicated by arrow Y3 in FIG. 29, when the number of symbols of "010" is about 100, compared with the first and second embodiments, the worst case number in which "010" appears can be further reduced. have.

20 (b4) and 20 (c4), the pattern after rearrangement of even odd bits of the third embodiment is "01010101 .... 0101", "10101010 ...." 1010 "," 0000000 .... 0000 ", and" 11111111 .... 1111 "are a combination of partial information bit strings. Therefore, the even-numbered bits are rearranged again with respect to the information-bit sequence in which the even-numbered odd bits are rearranged, and then the inversion of all bits or an exclusive logical sum of "01010101 .... 0101" with the information bits, or By doing both, it is possible to further reduce the number of occurrences of "010" again. At this time, it is obvious that a new one-bit flag 4 and a code corresponding thereto are added to the information bit in the same manner as the flag 3, and thus it is omitted.

Here, an example in the case where rearrangement of Embodiments 2 and 3 and the even odd bits is performed again is shown in FIG. In this example, all of the information bit arrays of binary 16 bits, that is, 2 ^ 16 = 65536 types of code length k = 16 are assumed, and the number of consecutive "010" is measured. The horizontal axis represents the number of "010" included in one 16-bit code, and the vertical axis represents the cumulative number of information bits including the "010" number. In addition, in order to make the relation of each symbol easy to understand, the symbols are connected by lines, but of course, only the discrete values of 0 and natural numbers are meaningful as the number of symbols, and a value smaller than 1 means 0 symbols. Doing.

As described in the examples, the worst number of "010" included in one information bit includes (k / 2) -1 = 7 in the comparative example indicated by ○, which corresponds to Example 2 In () corresponding to Example 3 in which {(k / 4) was truncated to an integer} -1 = 3, and even-numbered odd rearrangement was performed once, {(k / 6) is an integer. It is clear that the value} -1 = 2 cut | disconnected and the suppression of the worst number are suppressed. In addition, the above-described example of Example 3 in which the even-numbered bits are rearranged once and then rearranged even-numbered bits is regarded as information bits once again is shown by a rhombus and a two-dot chain line. Specifically, a, b, c, d, e, f, g, h .... m, n, o, and p are bits corresponding to 1 bit, respectively, and "abcdefgh .... mnop" In the case where the information bit sequence called is divided into 16 bits, rearrangement of "aceg .... mo bdfh .... np" is performed and finally "ae .... m cg .... o bf .... n dh .... p "corresponds to a rearrangement. After this rearrangement, "010" is included in the case of 8 + 4 types = 12 types by taking an exclusive OR of all bits and information bits and "01010101 .... 0101", or both. Minimal cases of numbers were extracted and plotted. Thus, by repeating the rearrangement of the even-numbered odd bits twice, again, the number of "010" included in the information bits can be reduced to 1 or less in this example, and the number including "010" In the case of one individual information bit, the number can be reduced more than in the comparative example. Of course, in these second encodings, since only the rearrangement is performed on the information bits, whether the entire bits are inverted or the exclusive OR, it is clear that there is no loss of information due to the encoding and the inverse transformation can be facilitated.

Of course, in the above embodiment, the even-numbered rearrangement puts even bits in front of the odd bits, but appropriately, this may be done in front of the even bits and behind the odd bits. In addition, although the example which performed rearrangement of the even-numbered odd bit twice was demonstrated this time, when the information bit length is long, you may use it again and again three times and four times.

In the third embodiment, of course, the functions and effects of the second embodiment and the features of (1) and (2) of the first embodiment also exist in this embodiment. In addition, in the present embodiment, compared with the second embodiment, by adding one bit as the information called flag 3 and two bits as the physical bits to the information bits, the upper limit of the number of occurrences of "010" in the second embodiment is {(k / 4) can be reduced from the value} -1 or less cut off to {(k / 6) to the integer value} -1 or less. For example, one memory cell α overlaps with the write threshold value v of FIG. 2, or the read level exceeds a threshold value determined as the write threshold value, and the erase bit is incorrectly recognized as the write bit. If the probability is p0, p0 is sufficiently smaller than 1, and the probability that a defect of [(k / 2) -1] × p0 occurs in the comparative example is [{(k / 6) is cut off to an integer}} -1] x p0 can be reduced.

In addition, although the remarkable characteristic of Example 1, 2, 3 of this application is repeated, it exists in providing the numerical value of the upper limit of the number of numbers which "010" generate | occur | produces in each Example clearly. Thereby, another improvement method can be used together as it is in the state which suppressed the upper limit of the number which "010" generate | occur | produces below fixed as described in SE59 of Example 4 mentioned later.

Example 4

Next, the data storage system according to the fourth embodiment will be described with reference to FIGS. 21 to 23. 21 shows an example of the overall configuration of a data storage system according to the fourth embodiment.

In the fourth embodiment, in addition to the first to third embodiments, in particular the third embodiment, the "1" bit M1a (?) And WL in the middle of the portion where the "010" symbol in FIG. By reducing the combination where bits M2a (ε) that are physically adjacent in the direction are the write bits " 0 ", the problem of increasing the threshold value due to the capacitive coupling of adjacent memory cells can be further reduced. In addition, although the present embodiment can be performed independently of the first to third embodiments, the same effect as the first to third embodiments, that is, the effect of alleviating the influence of the capacitive interference of adjacent memory cells, is best used in combination. desirable. The same parts as the first embodiment, the second embodiment, and the third embodiment or the same operation part are denoted by the same reference numerals and detailed description thereof will be omitted. The present embodiment can be applied to any of the first to third embodiments, but the application example of the third embodiment having the highest effect will be described here.

The differences in the configurations of the third embodiment and the fourth embodiment include memory cells adjacent to the WL direction with respect to the memory cells to write, in particular, memory cells that have already been written, as will be apparent when comparing FIGS. 15 and 21. It further has a page buffer 115 which stores the threshold value of the information bit of the word line (data selection line).

In multi-value NAND flash memory, multi-value data of the same level is written in order from the side closest to the source line. Therefore, it is preferable that the page buffer 115 is a buffer for storing data of memory cells formed in adjacent word lines on the source line side. Thereafter, a word line (data selection line) including a memory cell to write is referred to as WLn, and a word line (data selection line) including memory cells physically adjacent to WLn and already written is referred to as WLn-1 or It is briefly expressed as WL (n-1).

The page buffer 115 is connected to an error correction code decoding circuit 103 and stores information bits of a word line (data selection line) including memory cells already written from the flash memory 7. Here, it is preferable that the data stored in the page buffer 115 is configured to store data in which " 0 " and " 1 " However, when the error correction time and the circuit scale increase, the information bit portion of the code before the error correction may be used directly as the information bit of WLn-1 from the data input / output buffer 101. This is because the error correction code in the present embodiment is a separation code in which the information bits and the check bits are separated and the information bits remain in the error correction code. The reading method of this embodiment is from the first to third embodiments. Similarly, unlike writing, there is no need of reading WLn-1, and a bit error of WLn-1 at the time of reading does not directly cause a bit error. For example, when the present embodiment is applied to the configuration of the third embodiment, a plurality of times of reading of the data of WLn-1 is required for encoding of data at the time of writing. Therefore, when the information bits are quickly read from the nonvolatile memory 7 and the processing time is not a problem, the page buffer 115 is omitted, and the nonvolatile memory 7 is replaced with the reference numeral 115 instead. You can substitute them in the way that data is read. The specific configuration of the page buffer 115 may be omitted if it is configured in the same manner as the page buffer 114.

Further differences in the configurations of the first to third embodiments and the fourth embodiment include the " 1 " bit M1a (?) In the middle of the portion of the WLn-1 in which writing has already been made and " 010 " The present invention further provides symbol counter circuits 116, 117, 118, and 119 for counting combinations in which the adjacent bits M2a (ε) formed in WLn to write are the write bits " 0 " '. For the combination of eight types of code conversions used in the third embodiment with respect to WLn, "010" in the information string of the memory cells in WLn-1 and "x0x" of WLn after each conversion in advance (x is "0"). The occurrence of the state shown in (iv) of FIG. 2 which is more problematic than the case of (iii) in FIG. It is reducing the probability.

<Example of circuit configuration of symbol counters 116 to 119>

FIG. 22 shows a circuit configuration example of the symbol counters 116, 117, 118, and 119 of the fourth embodiment.

For example, as shown in Fig. 22, the counter 116 and the counter 117 input a series of information bits from the beginning of the information bits of WLn into the one-unit time delay circuit composed of the reference numeral 208 in time series in order. &Quot; H " in combination with a circuit for detecting the number where the bit in the middle of the symbol of 010 consecutive to " 010 " in WLn-1 becomes " 1 " It is easy to realize by counting the number of unit hours when the value is set to the counter. In Fig. 22, in the input connected to the counter 116, WLn-1 becomes "010" and WLn becomes "x0x" in the unit time in which WLn-1 is input in order of "010". In the unit time at which the "010" last "0" of WLn-1 was input, the output becomes "H" from one unit time "L", and "L" in other cases. In Fig. 22, in the input time connected to the counter 117, WLn-1 becomes " 010 " at the unit time in which " 010 " is input in sequence, and WLn becomes " x1x " In unit time in which "010" last "0" of -1 was input, the output becomes "H" from one unit time "L", and "L" in other cases. And a "0" detection circuit are realized by counting a logical product with a circuit (corresponding to the lower left of Fig. 22) that detects that WLn-1 is a symbol of three consecutive "010" symbols at WLn-1, where WLn-. From the page buffer 115 containing the information bits of 1, it is assumed that a series of information bits are sequentially inputted in order from the beginning of the information bits in synchronization with the information bit input of the WLn.

On the other hand, the circuit for detecting the case where WLn-1 is a symbol "010" and WLn becomes "x0x" after taking an exclusive OR with the bit mask of "01010101 .... 0101" is the circuit of FIG. Like the description, the circuit of FIG. 22 can be realized. Here, when the clock for giving the information bits is divided by the 1/2 divider 213, the output thereof is, for example, the y-th bit of the information bit and is " 1 " and " 0 " Is printed. Therefore, the input electrically connected to the symbol counter 118 is, for example, a symbol in which WLn-1 is "010", and (WLn is "x1x", and the y-bit is even. Or OR (when WLn is " x0x " and y-bit is odd), this is a symbol in which WL (n-1) is " 010 " and an information bit of WLn. And a 3-bit consecutive symbol of " x0x " in the bit string in which the exclusive OR of " 01010101 .... 0101 " is present, the " 010 " last " 0 " Is 1 unit time "H", otherwise, "L" On the other hand, the input electrically connected to the symbol counter 119 is, for example, that WL (n-1) is "010". The symbol is also a logical sum of (when WLn is " x1x " and y-bit is odd) or (when WLn is " x0x " and y-bit is even). (n-1) is a symbol called "010" In the case where there is a 3-bit consecutive symbol of "x0x" in an information bit of WLn and an exclusive logical OR of "10101010 .... 1010", the last "0" of WLn-1 is "0". In the input unit time, the unit time is "H", otherwise, it is "L". Therefore, the outputs of these two-input 0R circuits 214 are synchronized with the unit time of the information bit input, for example. By counting by triggering at a stable portion of the OR output in the unit time, the counter can be counted by the counter 118 and the counter 119. For example, the counter of Fig. 22 comprises a generally known binary counter. Since the details of the counter are omitted here.

<Specific sequence of second code conversion circuit 104 according to the fourth embodiment>

23 shows a specific sequence of the reference numeral 104 of the fourth embodiment.

In the reference numeral 104, first, in S51, the first, third, and fifth bits of WLn which reset the flag 1, the flag 2, and the flag 3 to write from the page buffer 114, (k-1) Reads information bit data of the number of (k / 2) bits of odd bits of the bit. Further, from the nonvolatile memory circuit 7 or the page buffer 115, the first, second, third, ..., (k / 2) of WLn-1 in which writing is performed adjacent to WLn. Read the information bit data of the (k / 2) bit number of the bit. As a method of outputting the odd bits to the counter, for example, the odd information bits may be output by the method on the left side of Fig. 17B.

Next, in SE52, the information bits of the number of (k / 2) bits of the even bits of the 2nd, 4th, 6th, ... k-bits of WLn to write from the page buffer 114. Read the data. In addition, from the page buffer 115, the (k / 2) + 1st bit, (k / 2) + 2nd bit, (k / 2) + 3rd bit of WLn-1 in which writing is made adjacent to WLn, .... Reads information bit data of (k / 2) bit number of k-bit. For example, even-numbered information bits are output after odd-bit output by the method on the right side of FIG.

Next, in SE53, for example, the " 010 " symbol in the information bit of WLn is counted in the counter 118, the " 101 " symbol is counted in the counter 109 and is even with the odd bits of k bits in length. The counter 112 counts " 01010101... 0101 ", ie, " 01 " repeatedly arranged from the beginning of the bit, and " 010 " Further, the counter 113 counts the information bits of length 1010010010 .... 1010, that is, the sequence "10" repeatedly arranged from the beginning of the bit, and the "010" symbol which takes an exclusive OR. In this case, information bits of SE51 and SE52 may be input to the information bits input of FIG. 13, for example.

Next, in SE54, for example, the "010" symbol in the information bits in WLn-1 and the "x0x" bit in the adjacent WLn after the second code conversion are detected. For example, the circuit shown in FIG. 22 may be used for this symbol detection. The following is performed on the condition which detected this symbol. First, the symbol counter 116 counts the number of bits of " x0x " (write second bit) of the information bits (k-bits) of WLn. The number of bits of " x1x " (the second bit is erased) of the information bits (k-bits) of WLn is counted by the symbol counter 117. Then, the symbol counter 118 counts the number of consecutive bits of "x0x" of the bit string that takes an exclusive logical sum of the information bit (k-bit) of WLn and "01010101 .... 0101". Then, the symbol counter 119 counts the number of consecutive bits of " x0x " in the bit string in which the information bit (k-bit) of WLn and the exclusive logical sum of " 10101010 .... 1010 " These should just input the information bits of WLn and WLn-1 of SE51, SE52 to the information bit input of FIG.

Next, in SE55, symbol counter 108, symbol counter 109, symbol counter 112, symbol counter 113, symbol counter 116, symbol counter 117, symbol counter 118, symbol counter The value of (119) is copied into the registers a, b, c, d, e, f, g and h, respectively.

Next, in SE56, in the page buffer 114 of the third embodiment, the odd-numbered odd-numbered even-numbered order is first, second, third, ..., k-bits from the page buffer of WLn to write. That is, k bits of information bit data are read in a normal bit output order. What is necessary is just to output an information bit to this by the method of the right side of FIG. Also, from the nonvolatile memory circuit 7 or the page buffer 115, the first, second, third, ..., k-bits of WLn-1, which have already been written adjacent to WLn, (k) Read bit information bits. At this time, since the output order and contents of the data of WLn-1 of SE51, SE52, and SE56 are the same, the page buffer 115 can read out faster than the normal nonvolatile memory 7. Therefore, high speed processing can be realized by writing data from the nonvolatile memory 7 to the page buffer 115 in SE51 and reading data from the page buffer 115 in SE56.

Next, in SE57, for example, the " 010 " symbol in the information bit of WLn is counted in the counter 108, the " 101 " symbol is counted in the counter 109, and the odd even odd order of k bits length is followed. That is, the counter 112 displays the " 01010101 .... 0101 ", i.e., " 01 " repeatedly arranged from the beginning of the bit, and " 010 " To count. Also, the counter 113 counts the " 10101010 .... 1010 ", i.e., " 10 " In this case, information bits of SE56 may be input to the information bits input of FIG. 13, for example.

Next, in SE58, the "010" symbol in the information bits in WLn-1 and the "x0x" bit of the adjacent WLn after the second code conversion are detected. For example, the circuit shown in FIG. 22 may be used for this symbol detection. The following is performed on the condition which detected this symbol. First, the symbol counter 116 counts the number of bits of " x0x " (write second bit) of the information bits (k-bits) of WLn. The number of bits of " x1x " (the second bit is erased) of the information bits (k-bits) of WLn is counted by the symbol counter 117. Then, the symbol counter 118 counts the number of consecutive bits of "x0x" of the bit string that takes an exclusive logical sum of the information bit (k-bit) of WLn and "01010101 .... 0101". Then, the symbol counter 119 counts the number of consecutive bits of "x0x" in the bit string that takes an exclusive logical sum of the information bit (k-bit) of WLn and "10101010 .... 1010". These should just input the information bits of WLn and WLn-1 of SE56 to the information bit input of FIG.

Next, in SE59, the values of the counter 108, the counter 109, the counter 112, the counter 113, the register a, the register b, the register c, and the register d are compared, and the value is determined in advance. Select all counters and registers that fall below threshold 2. Let this be a selection. As the predetermined threshold 2, when Example 3 is used simultaneously, {(k / 6) is cut off to an integer}}-1, and when Example 1 or Example 2 is used simultaneously, {( It is good to set k / 4) to the value} -1 cut to an integer. The basis of these values is the upper limit of the number of occurrences of " 010 &quot;, and detailed descriptions are described in Examples 1, 2, and 3, and thus are omitted here. From Embodiments 1, 2, and 3, it becomes clear that even if a combination of 2 ^k information bits of ^k bits is used, the number of symbol strings in which " 010 " is consecutive can be encoded to a predetermined threshold 2 or less. Therefore, the code of the fourth embodiment is a code that satisfies the symbol string in which " 010 "

Here, in the SE59 and SE60, when the counter 116 is selected, the counter 108 corresponding to performing the same encoding process to WLn is also selected. In addition, when the counter 117 is selected, the counter 119 corresponding to performing the same coding process to WLn is also selected. In addition, when the counter 118 is selected, the counter 112 corresponding to performing the same encoding process to WLn is also selected. In the case where the counter 119 is selected, the counter 113 corresponding to performing the same encoding process to WLn is also selected.

Here, when register e is selected, register a corresponding to performing the same encoding process to WLn is also selected. When the register f is selected, the register b corresponding to performing the same encoding process to WLn is also selected. In the case where the register g is selected, the register c corresponding to performing the same encoding process to WLn is also selected. In the case where register h is selected, register d corresponding to performing the same encoding process to WLn is also selected.

Next, in the SE60, among the registers and counters for which selection a has been performed, the counters 116, 117, 118, and 119 are compared with the contents of the registers e, f, g, and h, respectively, and include a content that is the minimum value. Find whether it is a register. As a result, in SE61, it is determined whether the minimum value is the counters 108, 109, 112, and 113 rather than the registers a, b, c, and d.

Here, when there is a condition on the counters 108, 109, 112, and 113 that is the minimum value, the sequence of Fig. 23 (c) is performed while the flag 3 is reset. Since the conditions of SE63 to SE69 are merely different from those described in FIG. 18B, and the conditions of the conditional branches SE63, SE65, and SE67 are different, the description is omitted. The branch of SE63 replaces the branch of SE17 in Fig. 18B, and in SE17, the smaller value of the value of the counter 108 and the value of the counter 109 is the value of the counter 112 and the counter. It is determined whether the value of (113) is larger than the value of the smaller one, but in SE63, the smaller of the value of the counter 116 and the value of the counter 117 is the smaller of the value of the counter 118 and the value of the counter 119. Determine if greater than In SE17, the number of "010" symbols after each second code conversion of WLn is compared. In SE63, the "1 'bit M1a (?) In the middle of the portion where the symbol" 010 "in WLn-1 occurs. ) And the number of combinations in which the bit M2a (ε) in the WLn adjacent to each other in the WL direction is the write bit " 0 " is replaced by comparing the information bits to be written in each WLn after the second code conversion.

In addition, the substitution of a register shall be converted in correspondence with the register demonstrated by SE59. SE65 and SE67 also replace | separate SE19 and SE21 of FIG. 18 (b) by the said rule, and description is abbreviate | omitted.

Thereafter, in SE69, the code corresponding to the flag 1, the flag 2, and the flag 3 is added to the information bit (k-bit) and output to the error correction code generating circuit at 102.

Next, in the SE61, if there is no condition that the minimum value occurs on the counters 116, 117, 118, and 119, the flag 3 is set in the SE62, and the sequence shown in Fig. 23D is performed.

Since the conditions of the SE70 to SE79 differ only from those described in FIG. 18C and the conditional branches SE70, SE73, and SE75, and the others are the same, other explanations are omitted. In addition, SE70, SE73, SE75 also replaced SE34, SE37, SE39 of FIG. 18 (c) with the rule demonstrated by FIG. 23C, and description is abbreviate | omitted.

In this way, after the second code conversion, WLn is a code that satisfies the symbol string in which " 010 " equal to or less than the threshold value 2 of the embodiment used at the same time, and a portion in which a symbol in which WLn-1 is " 010 " The combination in which the " 1 " bit M1a (?) In the middle of and the bit M2a (?) In the WLn adjacent in the WL direction is the write bit " 0 " can be minimized.

Through the above sequence, the number of "010" in the information bits after each conversion is counted in advance and quantitatively compared to the eight cases in which the code conversion of the third embodiment is performed. The influence of the capacitance interference of the memory cell in the WL direction in Fig. 2 (iv) can be reduced more than in the comparative example, while maintaining the probability of appearance of 3 consecutive bits of "

In addition, with respect to the decoding circuit 105 of the second code, the setting of flags 1, 2, 3 and the method of the second encoding correspond in the same way to the third embodiment, and therefore the same decoding circuit or sequence as described in the third embodiment. (105) may be used.

For example, in any case where WLn-1 is the worst-case input pattern of the third embodiment shown in Fig. 20B, and the input pattern of WLn is replaced by every (k / 3) bits, With respect to the worst "010" location of WLn-1 in Example 3, by applying the fourth embodiment, half of the WLn location can be set to "1" instead of "0", resulting from capacitive coupling in the WLn direction. Threshold rise can be reduced. This means that, for example, the code string of WLn-1 is set to "10101010 .... 1010" of (k / 3) bits, "00000000 .... 0000" of (k / 3) bits, and (k / 3). The code string of WLn is set to "00110011 .... 0011" of the bit, and "00110011 .... 0011" of the (k / 3) bit, "10101010 .... 1010" of the (k / 3) bit, Set the (k / 3) bit "00000000 .... 0000". In this case, the number of points where WLn-1 is "010" and "x0x" of WLn and the number of points where WLn-1 is "010" and "x1x" of WLn are the same, and WLn- One half of the number of "010" may deviate from the worst pattern of FIG. When the number of "010" points of WLn does not change in the whole bit inversion, similarly to the description of the second embodiment, at least half of the points of WLn are " By what can be "1" instead of "0". Further, if the conversion of WLn of the third embodiment is applied, the even-numbered bit conversion is performed so that the code string of WLn is " 01010101 .... 0101 " of (k / 6) bits and " 11111111 of (k / 6) bits. .... 1111 "," 00000000 .... 0000 "of (k / 6) bit," 01010101 .... 0101 "of (k / 6) bit," 00000000 .. of (k / 3) bit ..0000 "bit stream, the number of points where WLn-1 is" 010 "and" x0x "of WLn can be reduced to zero by the sequence of this embodiment.

Further, as a modification of the present embodiment, WLn-1 is " 010 " and " WLn " There is a modification in which the minimum value of α is obtained under a condition that the number (?) of WLn is compared and the number of "010" of WLn is equal to or less than the threshold value 2.

In the case where the WLn-1 is "010" and the worst number at the point where WLn becomes "x0x" is reduced, specifically, there is no shift, 1-bit cyclic shift, 2-bit cyclic shift, and 3-bit cyclic shift. It is sufficient to use the 4-bit circular shift, ..., q-bit circular shift. As q, it is preferable that it is 15 bits or more from the following discussion.

Note that the cyclic shift is, for example, in the page buffer of Fig. 16A, in the case of the 1-bit cyclic shift, the output data of the 2nd bit flip-flop FF2 is converted into the 1-bit flip-flop FF1 data. The input data is held as input data, and the output data of the third bit flip-flop FF3 is input and held as the data of the second bit flip-flop FF2, and the output data of the k-bit flip-flop FF (k) is inputted. The input is held as data of the data of the flip-flop FF (k-1) of the (k-1) -bit, and the output data of the flip-flop of the 1-bit is held as data of the data of the flip-flop of the k-bit. It shows. This can be realized in the output state of Dout2 in which only one pulse of 0 V? Vcc? 0 V is input to the clock? 1 and the clock? 2 in the left diagram of Fig. 17A. Further, when k bits are inputted from the output of the page buffer 114 after only one pulse is inputted into the symbol counter of FIG. 22 described in the fourth embodiment, the information bits of WLn shifted by one bit are WLn. -1 is " 010 " and the number of points to be " x0x " of WLn can be counted. As a matter of course, when a pulse of 0 V? Vcc? 0 V is input in advance to the clock? 1 and the clock? 2 in advance, it is obvious that the p-bit circular shifted state can be easily obtained. In addition, in order to restore the information bits in the unshifted state from the p-bit cyclic shifted state, it is obvious that the (kp) bit cyclic shift may be performed with the information bit length k. It can be easily realized in the configuration of the fourth embodiment. In this code and the code before it, the number including "010" is affected only by the maximum of one bit at the end of the first bit and the k bit, and is combined with the code conversion of the third embodiment. Even if it is used, the information is not lost if the number of traversed bits is recorded.

In this modification, for example, q type is performed including the case where it is not shifted as a cyclic shift, and the minimum value of α under 8xq conditions is calculated | required. In this case, at most one bit present at the end contributes to the increase or decrease of " 010 " at the end of the traversal shift, so that even if " 010 " On the other hand, the location where WLn-1 is "010" and "x0x" of WLn is a location at least two bits apart from each other. This is because the 1-bit shift point of the "010" symbol becomes "10x" or "x01" (x is an arbitrary bit of "0", "1"), and this cannot be "010". Therefore, the worst value of the fourth embodiment is a case where WLn-1 is "010" and "x0x" is the same number as the threshold value 2, and the bit shift and the 2-bit shift are 3, respectively. Assume that the worst-case state number does not decrease by bit shift, 4 bit shift, ... q bit shift. Since the worst-case number does not decrease from 0 bit shift to (0 + 2) bit shift, the 1-bit shift pattern of the WLn bit corresponding to the position of "010" of WLn-1 needs to be "000". In addition, since the worst-case state number does not decrease from 1 bit shift to (1 + 2) bit shift, the 2-bit shift pattern of the WLn bit corresponding to the position of "010" of WLn-1 needs to be "000". have. When threshold 2 is set to {(k / 6) truncated to an integer} -1 of Example 3, since "01010101 .... 01010" is (k / 3) -1 is the minimum value, the worst case number The pattern of the portion facing "010" of "WLn" is a continuous pattern of (k / 3) -1 + (q-2) bits of "00000000 .... 0000". Therefore, in the same manner as in the discussion of the conversion of the first embodiment, when q> = [(k / 6) rounded integer + 8], (k / 2) + 5 bits or more are " 00000000 .... 0000 ", and the number including" 010 "and" 101 "in the remaining bits is equal to or less than the maximum {(k / 4) value rounded up to an integer} -3. Therefore, in the case where the threshold value of the second embodiment is used, even if all bits of the information bits of WLn are inverted, the "010" symbol thereof is suppressed to the maximum {(k / 4) truncated to an integer} -3 or less. In addition, since WLn corresponding to the "010" location of WLn-1 can be changed from "0" to "1" by bit inversion, even if there is a one-state increase of "010" due to the end state. Contradicts the above assumptions. In other words, if the q-bit shift is set to q> = [integer +8 rounded (k / 6)], the upper limit point where WLn-1 is "010" and "x0x" of WLn is not changed. It can be suppressed. In addition, in the case of the conversion of Example 3, if at least q> = 15, the pattern of the part which opposes "010" of "WLn" in the worst-case state number will be (k / of "00000000 .... 0000" 3) -1+ (q-2) / (k / 3) +12, and when carried out similarly to the discussion of Example 3, the upper limit in which WLn-1 is "010" and "x0x" of WLn. It can suppress more than the worst upper limit in the case of not shifting a location.

Of course, as described above, when "010" is distributed and separated from each other in a case where "010" is continuously arranged like "0101010" in WLn-1, it is WLn in a shift of bits of q or less. The upper limit point which becomes "x0x" of can be reduced.

As described above, before performing the sign conversion (even-numbered bit conversion) of the fourth embodiment, in this modification, the first shift is q-bit first, and WLn-1 is "010", and "WLx" of WLn. By determining the minimum number to be used, the number of shifts as a condition is determined, and the data is shifted in a circular direction, whereby the upper limit point where WLn-1 is "010" and "x0x" of WLn can be reduced. In addition, similarly to the third embodiment, a bit corresponding to a flag of [integer rounded log ₂ (q + 1)] may be added to the information bit as the number of shifts q and encoded. When the flag bits are separated in SE44, the recovery shift number q is similarly separated from the sign. In SE50, in (f) of FIG. 17, 0 V? Vcc? By inputting a pulse of 0 V, it can be easily restored.

Of course, even in this modification, it is not necessary to read WLn-1 at the time of restoring WLn, and the bit error of WLn-1 at the time of reading does not directly cause a bit error, and high-speed reading can be realized.

Example 5 (Example of Application to MONOS Type)

Next, the data storage system according to the fifth embodiment will be described with reference to FIGS. 24A and 24B. In the fifth embodiment, the NAND cell array block 49 using the floating gate from the first embodiment to the fourth embodiment is changed to a NAND cell array block using the MONOS type gate. In this description, detailed description of portions overlapping with the above embodiment will be omitted.

24A and 24B are cross-sectional views corresponding to B-B 'and A-A' of the NAND cell array block corresponding to FIGS. 6A and 6B, respectively. In addition, since a top view is the same as that of FIG. 5 (b), it abbreviate | omits.

FIG. 24 shows, for example, a data transfer line in which nonvolatile memory cells M0 to M31 made of MOS transistors having SiN or SiON as charge storage electrodes 26 are connected in series, and one end is written BL through the selection transistor S1. Is connected to. The other end is connected to the common source line written as SL through the selection transistor S2. In addition, each transistor is formed on the same well. In Fig. 24, for example, in the p-type silicon region 23 having a boron impurity concentration between 10 ¹⁴ cm ^-3 and 10 ¹⁹ cm ^-3 , for example, a silicon oxide film or oxynitride having a thickness of 1 to 10 nm. A charge accumulation layer 26 made of, for example, SiN or SiON is formed to have a thickness of 3 nm to 50 nm via a tunnel gate insulating film made of a ride film. For example, polysilicon or WSi, for example, via an interlayer insulating film 50 made of a silicon oxide film having a thickness of 2 nm to 20 nm, Al ₂ O ₃ , HfSiO, ZrSiO, HfSiON, or ZrSiON. (Tungsten silicide) and polysilicon stack structure or NiSi, MoSi, TiSi, CoSi and polysilicon stack structure, TaN, TiN barrier metal and laminated structure control gate 27 having a thickness of 10 nm to 500 nm Formed. The control gate 27 is formed up to the block boundary in the left and right directions of the paper so as to be connected to the adjacent memory cell blocks in Fig. 5B, and forms the data selection lines WL0 to WL31 and the selection gate control lines SSL and GSL. Doing. In addition, the p-type silicon region 23 is capable of applying voltage independently of the p-type semiconductor substrate 21 by the n-type silicon region 22, thereby reducing the load of the booster circuit during erasing to reduce power consumption. In order to suppress, it is preferable. In the gate shape of this embodiment, since the sidewalls of the semiconductor region 23 are covered with the insulating film 24, the semiconductor substrate 23 is not exposed by etching before the charge accumulation layer 26 is formed, so that the charge accumulation layer 26 is a semiconductor. Coming below the area 23 can be prevented. Therefore, parasitic transistors in which the gate electric field concentration and the threshold value are reduced at the boundary between the semiconductor region 23 and the insulating film 24 are less likely to be produced. In addition, since the phenomenon of lowering the write threshold value, so-called sidewalk phenomenon due to electric field concentration is less likely to occur, a more reliable transistor can be formed.

On both sides of these gate electrodes, n-type diffusion layers 28 serving as source or drain electrodes are formed, for example, with an insulating film 43 made of a silicon nitride film or silicon oxide film having a thickness of 5 nm to 200 nm. The diffusion layer 28, the charge accumulation layer 26, and the control gate 27 form an M-ONO-S type nonvolatile EEPROM cell, and the gate length of the charge accumulation layer is 0.5 µm or less and 0.01 µm or more. It is done. Examples of these source and drain n-type diffusion layer 28, such is formed between depth 10㎚ to 500㎚ to the example phosphorus or arsenic, antimony, the surface concentration of 10 ¹⁷ ㎝ ^-3 to 10 ²¹ ㎝ ^-3. These n-type diffusion layers 28 are connected in series with memory cells, and a NAND connection is realized. In the figure, reference numeral 27 _SSL and 27 _GSL are gate electrodes connected to block selection lines corresponding to SSL and GSL, respectively, and are formed on the same layer as the control electrode of the MONOS type EEPROM. These gate electrodes face the p-type wells 23 through the gate insulating films 25 _SSL and 25 _GSL made of, for example, silicon oxide films or oxy nitride films having a thickness of 3 to 15 nm to form MOS transistors. have. Here, the gate lengths of the gate electrodes 27 _SSL and 27 _GSL are longer than the gate lengths of the memory cell gate electrodes, and are formed at, for example, 1 μm or less and 0.02 μm or more, so that the block selection and the non-selection are on and off. Rain can be largely secured, and it is possible to prevent false readings and misreads.

Further, n-type diffusion layer (28 _d) which is a source or drain electrodes and reference numeral 27 on one side of the _SSL in, for example, tungsten or tungsten silicide, titanium, titanium nitride, or the data transfer line (36 made of aluminum (BL )) and is connected via a contact (31 _d). Here, the data transmission line 36 (BL) is formed up to the block boundary in the vertical direction of the page of Fig. 5B so as to be connected to adjacent memory cell blocks. On the other hand, n-type diffusion layer (28 _S) that is the source or drain electrode formed on one side 27 of the _GSL is connected with the source line SL to be through a contact (31 _S). This source line SL is formed to the block boundary in the left-right direction of the paper of FIG. 5B so as to be connected to the adjacent memory cell block. Of course, the n-type diffusion layer 28 _S may be formed as a source line by forming the block boundary in the paper left and right directions. As these BL contacts and SL contacts, for example, polysilicon, tungsten, and tungsten silicide doped with n-type or p-type, tungsten silicide, Al, TiN, Ti, and the like are filled to form a conductor region. Further, between the SL and BL and the transistor, for example, it is filled by an interlayer film 28 made of SiO ₂ or SiN. In addition, the BL upper portion, for example, SiO _2, SiN or the insulating protective layer 37 made of polyimide, or the drawings, though not shown, for example, W, the upper wiring is formed consisting of Al or Cu have.

In this embodiment, since the MON0S cell is used in addition to the effects of Embodiments 1, 2, 3, and 4, the write voltage and the erase voltage are lower than those of the floating gate type EEPROM cells of Embodiments 1, 2, 3, and 4. Even if the device isolation interval is narrowed to reduce the thickness of the gate insulating film, the breakdown voltage can be maintained. Therefore, the area of the circuit to which the high voltage is applied can be reduced, and the chip area can be further reduced.

In addition, compared with Examples 1, 2, 3, and 4, the thickness of the charge storage layer 26 can be reduced to 20 nm or less, and the aspect at the time of gate formation can be further reduced, so as to process the gate electrode. The shape can be improved, and the filling between gates of the interlayer insulating film 28 can be improved, and the breakdown voltage can be further improved. Moreover, the process for forming a floating gate electrode and the slit making process are unnecessary, and a process process can be shortened more.

In addition, since the charge storage layer 26 is an insulator and charges are trapped in one charge trap, it is difficult for the charges to escape to the radiation and can be made to have strong resistance. In addition, even when the sidewall insulating film 43 of the charge storage layer 26 is thinned, good retention characteristics can be maintained without all the charges trapped in the charge storage layer 26 escape. In addition, the charge accumulation layer 26 can be formed without misalignment with the semiconductor region 23, so that the capacitance of the more uniform charge accumulation layer and the semiconductor region 23 can be realized. As a result, the variation in capacity of the memory cells and the variation in capacity between the memory cells can be reduced.

Example 6 (Example of Application to NOR Type)

Next, the data storage system according to the sixth embodiment will be described with reference to FIG. 25. In the sixth embodiment, the NAND cell array block 49 of the first to fifth embodiments is replaced with the NOR cell array block. In this description, the same parts as in the first to fifth embodiments are denoted by the same reference numerals, and detailed description thereof is omitted. In addition, in Example 1-Example 5, description is abbreviate | omitted about the same effect demonstrated in detail without limitation of an Example.

25A, 25B, 25C, 25D are a circuit diagram, a plan view, a row direction memory cell section cross section, and a column direction memory cell cross section of a NOR cell array block, respectively. In Fig. 25A, a plurality of nonvolatile memory cells M0 to M2 made up of MOS transistors having charge storage layer electrodes are connected in parallel to current terminals, and one end is connected to a data transfer line written as BL. The other end is connected to the common source line SL. In a NOR memory cell, a memory cell block 49 is formed of one transistor. In addition, each transistor is formed on the same well. The control electrodes of the respective memory cells M0 to M1 are connected to data selection lines written as WL0 to WL1. 25 (b), 25 (c) and 25 (d) are plan views of the memory cell block 49, a cross sectional view in the direction indicated by the arrow BB ', and a cross sectional view in the direction indicated by the arrow AA'. In particular, in FIG. 25B, only the structure below the gate electrode 27 is shown in order to make the cell structure easier to understand. In FIGS. 25C and 25D, for example, phosphorus is interposed through a tunnel gate insulating film formed of a silicon oxide film or an oxynitride film 25 having a thickness of 3 to 15 nm. Alternatively, the charge storage layer 26 made of polysilicon containing 10 ¹⁸ cm ^-3 to 10 ²¹ cm ^-3 added to arsenic is formed to a thickness of 10 nm to 500 nm. These are formed on the p-type silicon region 23 on the region where the element isolation insulating film 24 made of, for example, a silicon oxide film is not formed.

On this, for example, a block insulating film 50 made of a silicon oxide film or an oxynitride film or a silicon oxide film / silicon nitride film / silicon oxide film having a thickness of 5 nm to 30 nm is formed. These are formed on the p-type silicon region 23 in the region where the element isolation insulating film 24 made of, for example, a silicon oxide film is not formed.

Further, a control gate 27 having a stack structure of polysilicon or WSi (tungsten silicide) and polysilicon or a stack structure of CoSi and polysilicon is formed to a thickness of 10 nm to 500 nm. This control gate 27 is formed up to the block boundary in the left-right direction of the paper so as to be connected to the adjacent memory cell block in Fig. 25B, and forms the data selection lines WL0 to WL2. In addition, the p-type silicon region 23 is capable of applying voltage independently of the p-type semiconductor substrate 21 by the n-type silicon region 22, thereby reducing the load of the boost circuit during erasing to reduce power consumption. In order to suppress, it is preferable.

As shown in Fig. 25D, an interlayer insulating film made of a silicon oxide film or an oxynitride film having a thickness of, for example, 5 nm to 200 nm, beneath these gate electrodes in the AA 'cross section corresponding to the memory cell. An n-type diffusion layer 28 serving as a source or a drain electrode is formed with the 56 interposed therebetween. The diffusion layer 28, the charge accumulation layer 26, and the control gate 27 form a floating gate type EEPROM cell whose information is the amount of charge accumulated in the charge accumulation layer, and the gate length is 0.5um. Below 0.01um or more. As shown in FIGS. 25B and 25D, the n-type diffusion layer 28 paired with the n-type diffusion layer 28d connected to the BL extends in the left-right direction of the paper in FIG. 25B. The source line SL connects adjacent memory cells. Also in such NOR cells, since the charge accumulation layers of memory cells adjacent to each other in the data transmission line direction and the data selection line direction with SL interposed therebetween are formed as insulating films, a threshold value variation occurs due to capacitive coupling between the charge storage layers. do. Thus, for example, as in M1a and M2a in Fig. 25A, two adjacent cells with a source line interposed therebetween are written for each bit and stored or read as a series of information bit streams. In the case of betting, the variation of the threshold value due to the capacitive coupling between the charge storage layers can be suppressed by applying the embodiments described in the first to fourth embodiments to the written and read information bit strings.

As shown in Fig. 25A, two memory cells adjacent to each other in the row direction, like M1a and M1b or M1a and M1b ', are also filled with an insulating film, so that the capacitive coupling between charge storage layers is achieved. Threshold variation by Thus, for example, writing is performed for each bit to two adjacent memory cells adjacent in the row direction as shown in M1a and M1b in FIG. 25A or M1a and M1b ', and a series of In the case of storing or reading as the information bit string, the variation described by the capacitive coupling between the charge accumulation layers can be suppressed by applying the embodiments described in Embodiments 1 to 4 to the written and read information bit strings. .

[Example 7 (Example of Application to MONOS Type of Virtual Ground)]

Next, the data storage system according to the seventh embodiment will be described with reference to FIGS. 26, 27, and 28. In the seventh embodiment, the NAND cell array blocks 49 of the first to fifth embodiments are replaced with the virtual ground cell array block 49 formed in the MONOS structure. In this description, the same parts as in the first to sixth embodiments are denoted by the same reference numerals, and detailed description thereof is omitted. In addition, in Example 1-Example 6, description is abbreviate | omitted about the same effect demonstrated in detail without a restriction | limiting of an Example.

FIG. 26A shows the wiring relationship between the matrix 1 of the NAND cell array and FIG. 26B shows the wiring relationship of the matrix 1 of the NROM cell array. As shown in FIG. 26B, the memory cell blocks 49 in which nonvolatile memory cells are connected in parallel are arranged. In order to sense the data of the data transfer line of the memory cell array 1 or to hold the write data, the sense amplifier circuit 46 is provided via, for example, the data transfer line select transistors Q1a, Q2a ... Q1k, Q2k. It is. This sense amplifier circuit is mainly composed of a flip-flop circuit, for example. In addition, the sense amplifier circuit 46 is connected to the data input / output buffer 45. These connections are controlled by the output of the column decoder 48 which receives the address signal from the address buffer 47, writes the data supplied to the data input / output buffer into the memory cell array 1, and writes the data into the second internal I. It can be read on the / O line. The row decoder 3 is provided to select the memory cells with respect to the memory cell array 1, specifically, to control the data control lines WL0 to WL2 and the data transfer line select transistors sel1 and sel2. have.

27 and 28 are cross-sectional views of memory cell sections in a row direction and a column direction of a virtual ground array block, respectively, and illustrate a structure in which two memory cells are connected. FIG. 27 is a sectional view of the MONOS memory of the seventh embodiment, showing two memory cells in which the gate electrode 8 is connected by a control electrode. 28 illustrates a cross-sectional structure in a cross section perpendicular to FIG. 27 passing through the gate electrode.

In this embodiment, the formation direction of the data control line (corresponding to 11 or 8 ') connected to the gate electrode 8 coincides with the formation direction of the channel. In this embodiment, charges are stored in the vicinity of the source and drain electrodes of the memory cells, and at least 2 bits of information are stored per cell. In this structure, each bit can be read out by the direction of the voltage of the source electrode and the drain electrode, for example, by a method known from US Pat. No. 6,201,282. In this case, since the current terminal of the bit on which the information is not read and the bit on which the information is read is equivalent to being connected in series, the bit on the side not reading the information is subject to read disturb stress similar to that of a NAND memory cell. do. Therefore, the bit on the side which does not read information changes from an erase state to a write state by repeating reading.

Also in this structure, since the charge accumulation region 26 is formed adjacent to each other in the data transfer line direction and the data selection line direction through the insulating film, when the information is simultaneously written to a plurality of adjacent memory cells, the adjacent memory cells are separated by the adjacent memory cells. Threshold variation occurs due to capacitive coupling. The effect of the second encoding from the first embodiment to the fourth embodiment can be obtained. 27 and 28, for example, in the p-type silicon semiconductor region 23 having a boron or indium impurity concentration between 10 ¹⁴ cm ⁻³ and 10 ¹⁹ cm ⁻³ , for example, between 0.5 nm and 10 nm. A first insulating film 25 made of a silicon oxide film or an oxynitride film having a thickness is formed. In addition, a charge accumulation layer 26 made of, for example, a silicon nitride film is formed on the first gate insulating film in a thickness of 3 nm to 50 nm. On this, for example, a block insulating film (second insulating film) made of a silicon oxide film or an oxynitride film, Al ₂ O ₃ , ZrSiO, HfSiO, ZrSiON or HfSiON having a thickness of 5 nm or more and 30 nm or less (50). For example, the polysilicon layers 51 and 27 in which boron, phosphorus, or arsenic are impurity-added in the range of 1 × 10 ¹⁹ cm ^-3 to 1 × 10 ²¹ cm ^-3 are 10 nm to 500 nm. It is formed in the thickness of. Here, the concentration of boron, phosphorus, or arsenic in the polysilicon layers 51 and 27 is 1 × 10 ¹⁹ cm ⁻³ or more, so that the electric field applied to the ONO laminated film becomes smaller due to depletion of the control electrode, It is preferable to prevent the erase time or the write time from increasing.

Further, for example, the metal reinforcement layer 27 'of the control gate made of WSi (tungsten silicide) or NiSi, MoSi, TiSi, CoSi, W, Al, AlCu on the polysilicon 27 is 10 nm to It may be formed with a thickness of 500 nm. These polysilicon layers 51 form a control electrode, and the metal reinforcement layer 27 'makes the control electrode low resistance.

In addition, on this metal reinforcement layer, the insulating film 60 which consists of a silicon nitride film and a silicon oxide film, for example may be formed in the thickness of 5-500 nm. This functions as an insulating film serving as a mask during gate electrode processing. Further, sidewall insulating films 19 made of silicon oxide films or silicon oxynitride films are formed on both sides of these gate electrodes. At least a side surface of the sidewall insulating film 19 that contacts the gate electrode 51 has a lower charge trap density, a higher dielectric breakdown voltage than the insulating film formed of the deposition film, and a gate electrode 51 and the insulating film ( In order to lower the density of the interface state between the layers 19), the gate electrode 51 containing silicon is formed by oxidation or oxynitride. In this manner, it is possible to use a thermal oxide film having a higher quality than the deposition film for the gate sidewall.

In Fig. 27, an example is shown in which the charge accumulation film 26 is partially removed on the source region and the drain region 28, and an element isolation insulating film 12 made of, for example, a silicon oxide film is formed. Since 26 is formed of an insulator, it is not necessary to remove the charge storage film 26 on the source region and the drain region 28, and may be formed continuously.

The shape of FIG. 27 can be formed, for example in the following procedure. For example, without forming the metal reinforcing layer 27 ', the gate electrode material 51 containing silicon is laminated, and patterned in a line shape in which the front and back direction becomes the length until the first insulating film 25 is reached. Then, anisotropic etching is performed to remove the gate electrode material 51, the second insulating film 50, the charge storage layer 26, and the first insulating film 25. Subsequently, the sidewall insulating film 19 is formed by oxidation or oxynitride of the gate electrode 51, and the n-type layer 28 serving as the source region and the drain region is formed by surface concentration of phosphorus, arsenic, and antimony, for example. It is formed by ion implantation at a depth of 10 nm to 500 nm so as to be 10 ¹⁷ cm ^-3 to 10 ²¹ cm ^-3 . Thereafter, a silicon oxide film, silicate glass, or inorganic glass serving as the insulating film 68 is deposited on the entire surface in a thickness range of 10 nm to 1000 nm, and then the insulating film 68 is formed by, for example, CMP (Chemical Mechanical Polishing). ) And the upper surface of the gate electrode 51 is exposed by wet etching, for example, an ammonium fluoride solution. Subsequently, the second gate electrode material 27 made of, for example, polysilicon or SiGe mixed crystal, which serves as a control electrode, is deposited in the range of 10 nm to 300 nm, and further, the metal reinforcing layer 27 'and the mask insulating film. (60) is deposited on the whole surface. Here, the concentration of boron, phosphorus, or arsenic in the second gate electrode material 27 is 1 × 10 ¹⁹ cm ⁻³ or more, so that the electric field applied to the ONO laminated film becomes smaller due to depletion of the control electrode, It is preferable to prevent the erase time or the write time from increasing. Next, in the memory cell, the pattern is linearly patterned in a direction orthogonal to the pattern of FIG. 27, and anisotropic etching is performed to form the mask insulating film 60, the metal reinforcement layer 27 ', the second gate electrode material 27, and Etching is performed to the gate electrode material 51 and the second insulating film 50. Subsequently, in order to reduce the leakage current between the channels of the memory cells represented by the two gate electrodes 51 shown in FIG. 28, for example, boron, BF ₂ , and indium may have a surface concentration of 10 ¹⁶ cm ⁻³ or more. The p-type layer 18 may be formed by ion implantation so as to be between 10 nm and 500 nm so as to have a width of 10 ¹⁸ cm ⁻³ . Moreover, the insulating film 61 which consists of a silicon nitride film, a silicon oxynitride film, or an alumina film is formed in the whole surface in the range of 5 nm-200 nm, for example.

This insulating film 61 is a deposition insulating film formed by, for example, a chemical vapor deposition (CVD) method or a sputtering method. Further, it is preferable that the entire surface is deposited on the memory cell because it can prevent the gas, radicals and ions from the film formed above the insulating film 61 from adversely affecting the memory cell.

Above the insulating film 61, for example, an interlayer insulating film 62 made of silicate glass such as BPSG, PSG, and BSG containing 1 × 10 ²⁰ cm ⁻³ or more of boron or phosphorus is 10 nm to 1000 nm. It is formed in the range of thickness. This silicate glass has a function of gettering alkali ions, and it is preferable to be formed on the entire surface above the memory cell in order to prevent contamination by alkali ions. In Figs. 27 and 28, the interlayer insulating film 62 is formed in direct contact with the insulating film 61. However, the interlayer insulating film 62 is not necessarily formed in contact with the insulating film 61. For example, the interlayer insulating film 62 may be formed as an insulating film between wiring layers or an insulating film on the wiring layer. It does not matter because it has the effect of turing.

In addition, since the silicate glass generally has poor embedding immediately after deposition, it is flattened by viscous flow after annealing, for example, by annealing in the range of 2 to 120 minutes between 750 ° C and 1000 ° C. Moisture or hydronium ions contained in the silicate glass are advantageous during this annealing. However, by forming the insulating film 61, the gate end of the memory cell is oxidized by this moisture, so that the block oxide film at the end of the gate electrode 51 becomes a thick film. The shape can be prevented from changing.

As the interlayer insulating film 62, for example, an inorganic glass formed of cyclopentasilane or polysilazane may be used. In this case, an oxidation process is required to convert cyclopentasilane or polysilazane into inorganic glass, but since the oxidant oxidizes the gate edge portion of the memory cell, the block oxide film at the end of the gate electrode 8 is thickened. The problem that the shape is changed can be prevented by forming the film 61. In addition, the film 62 may use a laminated structure with another interlayer film such as a silicon oxide film formed by TEOS or HDP or HSQ, for example.

In addition, an upper wiring 36 made of, for example, W, Al, AlCu, or Cu is formed above the interlayer insulating film 62. In this example, since only one layer is shown as the wiring layer because it is not important as a constituent requirement of the patent, of course, a multilayer wiring structure may be laminated. In addition, the silicon nitride film layer 37 'deposited by the plasma chemical vapor deposition method through a silicon oxide film formed by TEOS or HDP or an interlayer insulating film 37 called HSQ, for example, has a thickness of 20 nm to 1 um. The whole surface is deposited in the range. This silicon nitride film layer has a function of blocking moisture diffused from the outside of the chip (upper surface).

In this embodiment, in addition to the effects of Examples 1-4, at least the following effects (3) to (4) are obtained.

(3) The control electrode 27 (the left and right directions in the page in FIG. 27) is formed orthogonal to the direction in which the source region and the drain region 28 are formed (in the front and back directions in FIG. 27), and the source of adjacent memory cells is formed. A structure in which electrodes and drain electrodes are connected in parallel, for example, a virtual ground array type is realized.

Therefore, the series resistance of the memory cell block can be made small and constant, which is suitable for stabilizing the threshold value in the case of multiplexing.

In addition, since the device isolation film 12, the source region and the drain region 28, and the charge storage layer 26 can be formed in a self-aligning manner, it is not necessary to secure a margin of misalignment between these layers, thereby providing a higher density. Can realize a memory cell. These array configurations and effects are described, for example, in Japanese Patent Application No. 2001-264754, which is a prior application by the present inventors, and therefore will be omitted here.

(4) In the present embodiment, in addition to the features of the first and second embodiments, since the MONOS cell is used, the write voltage and the erase voltage can be lowered than those of the floating gate type EEPROM cells of the first and second embodiments. Even if the separation interval is narrowed to reduce the thickness of the gate insulating film, the breakdown voltage can be maintained. Therefore, the area of the circuit to which the high voltage is applied can be reduced, and the chip area can be further reduced. In addition, compared with Examples 1 and 2, the thickness of the charge storage layer 26 can be reduced to 20 nm or less, the aspect at the time of gate formation can be reduced, and the processing shape of the gate electrode can be improved. The filling between gates of the interlayer insulating film 62 can also be improved, and the breakdown voltage can be further improved. Moreover, the process for forming a floating gate electrode and the slit making process are unnecessary, and a process process can be shortened more. In addition, since the charge storage layer 26 is an insulator and charges are trapped in one charge trap, it is difficult for the charges to escape to the radiation and can be made to have strong resistance.

Example 8

In the eighth embodiment of the present invention, the "1" bit M1a (?) In the middle of the portion of the WL (n-1) where the continuous symbol of "010" has occurred is further written in the WLn to be written from now on. The example relates to the fact that M2a (ε) of the formed adjacent bits is the write bit " 0 ", for example, can be greatly reduced to the number zero. In addition, although the present embodiment can be performed independently of the first to third embodiments, the same effect as the first to third embodiments, that is, the effect of alleviating the influence of the capacitive interference of adjacent memory cells, is best used in combination. desirable. The same parts as the first embodiment, the second embodiment, and the third embodiment or the same operation part are denoted by the same reference numerals and detailed description thereof will be omitted. Although the present embodiment can be applied to any of the embodiments 1 to 3, the application example of the third embodiment having the highest effect will be described here.

<Configuration example>

Overall configuration example

First, as a whole structural example which concerns on this example, FIG. 30 shows the block diagram of the data storage system of an Example. In this embodiment, as in FIG. 21 of Embodiment 4, the threshold value of the information bit of the word line (data selection line) including the memory cell adjacent to the WL direction with respect to the memory cell to write, in particular, the memory cell already written. It further has a page buffer 115 for storing. In the present embodiment, the page buffer 114 is a page buffer in which information bits are rearranged. This can only be achieved by changing the bit written in the page buffer 114 into the erase bit, and can be easily realized with the page buffer described with reference to FIG. As the page buffers 115 and 114, it is different from the fourth embodiment in that in addition to the information bits, code bits for mitigating the influence of the capacitive interference of the cells are added. For example, in the third embodiment, a code length of 1 + 1 / (6-1) times as well as information bits may be prepared. In the first and second embodiments, in addition to the information bits, a code length of 1 + 1 / (4-1) times may be prepared.

As shown in the figure, the code conversion circuit detects a contiguous bit array of write bits / erase bits / write bits of the information bits of the second page that are physically adjacent to the first page to write, and writes the second page. And a fifth circuit for outputting the bits of the first page adjacent to the erase bits, within a contiguous bit array of bits / erase bits / write bits. When the fifth circuit detects a continuous bit array of write bits / erase bits / write bits, the first page adjacent to the erase bit in the continuous bit array of write bits / erase bits / write bits of this second page. The bits are replaced with erase bits to generate encoded information bits. Code generation means for generating an output of the first page of the fifth circuit as a second code and adding the second code to the encoded information bits of the second page to generate second information bits; When two information bits are input and a contiguous bit array of write bits / erase bits / write bits of information bits of a physically adjacent second page is detected, the write bits / erase bits / write bits of the second page are detected. And decoding means for replacing the bits of the first page adjacent to the erase bits in the continuous bit array with a series of bits of the second code.

In FIG. 30 of the present embodiment, the write bit / erase bit / write bit of the information bits of the second page which are physically adjacent to the first page for writing to the adjacent memory cell disturb reduction second code conversion circuit 104 is further shown. A fifth circuit is included that detects the contiguous bit array and outputs the bits of the first page adjacent to the erase bits that are within the contiguous bit array of write bits / erase bits / write bits of this second page.

Configuration example of the fifth circuit

31, an example of the configuration of a fifth circuit according to the present example will be described. As shown in the drawing, basically, the components of the circuit output to the symbol counters 116 and 117 of Fig. 22 are used as the output circuit of the fifth circuit example, and the same functional parts are denoted by the same reference numerals and description thereof is omitted. do. The fifth circuit is, for example, an output of WL (n-1) = "010" and WLn = "x1x" and an output of WL (n-1) = "010" and WLn = "x0x", As shown in Fig. 31, from the beginning of the information bits of WLn, a series of information bits are sequentially input to a one-unit time delay circuit composed of reference numeral 208 in time series, and the symbols of three consecutive bits of " 010 " By combining a circuit that detects the number at which the bit in the middle becomes " 1 " in WLn, and a circuit that detects the number at which the bit becomes " 0 ", it can be easily realized.

In output 1 in the figure, WLn-1 becomes "010" in the unit time in which WLn-1 is input in order of "010", and when "WLn" becomes "x0x", "010" of WLn-1. In the unit time at which the last " 0 " was inputted, the output is changed from one unit time " L " to " H " In the output 2 in the figure, WLn-1 becomes " 010 " at the unit time in which " 010 " is input in sequence, and " 010 " last of WLn-1 when WLn becomes " x1x " In the unit time in which "0" is inputted, the output becomes "H" from one unit time "L", otherwise it becomes "L". Here, from the page buffer 115 containing the information bits of WLn-1, a series of information bits are sequentially inputted in order from the beginning of the information bits in synchronization with the information bit input of the WLn.

In addition, as an output 3 in the figure, a continuous bit array of write bits / erase bits / write bits of information bits of a page of a second WL (n-1) physically adjacent to a page of a first WLn to write is detected. Outputs a bit of a first WLn page adjacent to an erase bit in a contiguous bit array of write bits / erase bits / write bits of the page of the second WL (n-1). In the circuit outputting this output 3, WLn-1 becomes "010" in the unit time in which "010" is sequentially input, and the WLn bit corresponding to the erase "1" bit in the center of WLn-1 is output. . As shown in the figure, a bilateral gate formed of the inverter 209, the MOS transistor 215, and the PMOS transistor 216 can be easily formed.

In addition, output 4 in FIG. 31 is the unit time in which "010" is input in order, and when the WLn-1 becomes "010", the unit time in which "010" last "0" of WLn-1 is input. The output becomes "H" from "L" for one unit of time, and "L" in other cases.

In addition, in FIG. 30, the bit output from this 5th circuit is made into the arrangement of a 2nd code, and has the buffer 188 which stores a 2nd code. By holding this output 4 as a trigger and holding the output 3 in the buffer 188 in order, the second code can be held.

Here, the adjacent memory cell disturbance reducing second code conversion circuit 104 including the fifth circuit is the same block diagram as the adjacent memory cell disturbance reduction second code conversion circuit of FIG. However, it is characterized by including the fifth circuit as described above.

Configuration and operation example of page buffer memory

32A and 32B show a circuit and an operation example of the page buffer memory. As shown in FIG. 32A, the example of the page buffer 11 which temporarily stores the 2nd code bit of aa bit length is shown. In the present example, the bidirectional switch circuit bi consisting of the n-type transistor 215, the p-type transistor 216, and the inverter 209 is connected in k stages by connecting the D-type flip-flop 208 in series. It is connected by a lateral switching circuit. In addition, as the D flip-flop 208 of this example, the output is determined at the moment when the clock input rises from "L" (here, 0 [V] for convenience) to "H" (here, Vcc for convenience). After that, the output is changed to an edge trigger type flip-flop in which the output does not change even when the clock is in the "H" state or the "L" state. This bidirectional switch circuit is a circuit in which the current terminals of reference numerals 215 and 216 are in a conducting state when the data output control input is " H ", and a cutoff state when " L ".

32B shows the operation of the circuit. As shown in the figure, when data is stored in the D-type flip-flop, the data output control input is first set to "L" so that the output of the flip-flop 208 is not output to the data input / output line. After the digital data Din1 of Vcc ("H") or 0V ("L") is supplied to the data input / output (I / O) line, the clock is changed from "L" to "H". As a result, the data of Din1 is held in the leftmost flip-flop 208 of Fig. 32A. Next, after supplying the digital data Din2 of Vcc ("H") or 0V ("L") to the data input / output (I / O) line, the clock is changed from "L" to "H". As a result, the data of Din1 is transferred to and held in the second flip-flop 201 from the left in FIG. 32A, and Din2 is held in the leftmost flip-flop 208. Subsequently, digital data is supplied to the data input / output (I / O) line up to aa [bit] sequentially, and a clock is supplied so that Din1, Din2 ... Dinaa in order from the flip-flop on the right side of Fig. 32 (a). Data is retained, and data in aa [Bit] can be retained.

Next, the operation of reading data from this page buffer 1 will be described. First, the data output control input is set to "H", and the output of the rightmost flip-flop 208 is output to the data input / output line. As a result, the same data as the data of Din1 (here, referred to as Dout1) is output to the data input / output line. In addition, the clock input is set to "H" from clock "L". As a result, one-bit data is transmitted and held from the left to the right flip-flop. As a result, the same data as the data of Din2 (here, referred to as Dout2) is output to the data input / output line. Subsequently, by setting the clock inputs (a-1) times from clock "L" to "H", Din1, Din2. Din2. In order from the flip-flop on the right side of Fig. 32A on the data input / output (I / O) line. The data of Dinaa is output, and the data of aa [Bit] can be output.

<Code formation flow>

Next, the operation flow of forming the code | symbol which concerns on this eighth Embodiment is demonstrated using FIG. In the following WL (n-1) and WL (n), at least one bit is written in WL (n-1) and WL (n) in order, and n is a natural number in order. It is assumed that writing is performed. In addition, as described in the third embodiment, for example, the one which has already been implemented to reduce the continuous arrangement of the write bits / erase bits / write bits in the information bits of WLn has more write bit / erase bits / write bits. It is preferable because the upper limit of the continuous arrangement of can be reduced.

First, in SE201, the counter kk indicating the bit position in the first information bit is set to one. In addition, the checksum recording counter cs is set to zero. In addition, the buffer 188 is reset to "L" in advance. Next, in SE202, at the position of kk of the first information bit, it is checked whether there is a continuous array of write bits / erase bits / write bits. This may be done by detecting whether the output 4 of the fifth circuit shown in FIG. 31 is "H" or "L".

Next, in SE203, it is determined whether there is a continuous array of write bits / erase bits / write bits. If not, the value of the counter kk is increased by one in SE207. Next, in SE208, it is determined whether the value of the counter kk plus two is greater than the first information bit. If NO in SE208, the flow returns to SE202 to check whether there is a continuous array of write bits / erase bits / write bits for the next bit of the first information bit.

On the other hand, in SE203, in the case of the branch of "Yes", in SE204, the bit of WLn adjacent to the erase bit of the continuous bit array of write bit / erase bit / write bit of WL (n-1) of the first information bit. Is output from the output 3 of the fifth circuit. The second code is formed by sequentially storing this in the buffer 188 in SE205. At this time, the value of (kk + 1) is further added to the counter cs of the checksum. This means that a value indicating the position of the erase bit of the write bit / erase bit / write bit array of WL (n-1), that is, an address value, is added to cs.

Further, in SE206, the bits of WLn adjacent to the erase bits of the continuous bit array of the write bit / erase bit / write bit of WL (n-1) of the first information bit are replaced with erase bits. As a result, the bits of WLn adjacent to the erase bits of the array of write bits / erase bits / write bits of WL (n-1) do not become write bits. The code | symbol after this substitution is made into 1st code | symbol. As a result, generation of a bit pattern with a large amount of memory cell capacity interference can be prevented. Thereafter, the sequence of SE207 is joined.

On the other hand, in the case of the branching of "YES" in SE208, the length of the second code is obtained for the second code recorded in the buffer 188 in SE209. It is obvious that the length of the second code can be obtained by counting the number of "H" of the output of the buffer which stores the second code.

In addition, the value of the checksum counter cs is obtained as a checksum. Next, what added the information of the 2nd code | symbol and the length of the said checksum cs and the 2nd code | word to the said 1st code is created as a 2nd information bit. For example, the first code is recorded in the page buffer 114 for rearranging the information bits, and the output of the buffer 188 for recording the second code, the checksum cs, and the length of the second code, for example. Can be created by inputting the information bits of to be written after the first code into the page buffer 114.

Here, for example, in the case where the implementation for reducing the continuous arrangement of the write bit / erase bit / write bit in the information bits of WLn has already been performed, as shown in Fig. 34, the flag 1 equivalent information and the flag in the first information bit are shown. What added the 2nd code and the information of the length of the said checksum cs and the 2nd code to what added 2 equivalent information should just be created as a 2nd information bit. In addition, what added the information of the 2nd code | symbol and the said checksum cs and the length of a 2nd code is called a 2nd additional code.

In this embodiment, first, as in the fourth embodiment, information bits of WLn adjacent to the "010" portion of WL (n-1) are set to 500_1, 500_2, 500_3, ..., 500_c-2, 500_c-1, Let it be 500_c. The total number of these 500_1, 500_2, 500_3, ...., 500_c-2, 500_c-1, 500_c is {value of truncated ((k / 6)) to the integer} -1 or less in Example 3, and the Example When using 1 or Example 2 simultaneously, it is set as {(k / 4) the value cut out to an integer} -1.

Here, the information bits of 500_1, 500_2, 500_3, ..., 500_c-2, 500_c-1, 500_c are assumed to be arranged in order from left to right of the first information bit, for example. This may be arranged in order from right to left. Next, the information bits of 500_1, 500_2, 500_3, ..., 500_c-2, 500_c-1, 500_c are extracted, and 500a_1, 500a_2, 500a_3, ...., 500a_c-2, 500a_c-1, 500a_c As a part of the 2nd additional code | symbol, it arrange | positions in order on the right side of the flag 2 correspondent information as a figure. Although it may be easy to arrange in order from the left to the right of the first information bit, this may be arranged in the order from the right to the left, and 500_1, 500_2, 500_3, ...., 500_c-2, 500_c-1, 500_c The reordering may be performed with a certain promise using a cyclic code for circulating the c codes of once.

As described above, the length of this portion of the second additional code is {value of truncated ((k / 6)) to an integer} -1 or less in Example 3, and the example 1 or 2 In the case of simultaneous use, {(k / 4) is rounded to an integer} -1. The information bits corresponding to 500_1, 500_2, 500_3, ..., 500_c-2, 500_c-1, 500_c of WLn are replaced with "1" which is an erase bit. This is set to 500b_1, 500b_2, 500b_3, ..., 500b_c-2, 500b_c-1 and 500b_c shown in FIG. Thereby, all the information bits of WLn adjacent to the "010" part of WL (n-1) in a 1st information bit can be set to "1". Therefore, the state of the write bit " 0 " adjacent to the worst " 010 " as shown in Fig. 2 (iv) can be zero among the first information bits of the k-bit in Fig. 34.

Here, in the second additional code, 500a_1, 500a_2, 500a_3, ... in order to the information array of the position facing the "1" of the code string of "010" of the WL (n-1) of the first code. , 500a_c-2, 500a_c-1, and 500a_c. Therefore, in decoding, the information bits of WLn opposed to the part of "1" of "010" of the first information bits of WL (n-1) are counted from the left, for example, 500a_1, 500a_2, 500a_3, .. It is clear that decoding can be performed by substituting for 500a_c-2, 500a_c-1, 500a_c.

Here, the code formation method can shorten the code length than recording all addresses of 500_1, 500_2, 500_3, ...., 500_c-2, 500_c-1, 500_c, but WL (n-1) When one occurrence location of "010" is missing or accidentally generated, an error may occur from the decoding method by the length of this part of the second additional code. Therefore, in particular, it is desirable to be able to correct an error in the " 010 " location of WL (n-1) against 500_1, 500_2, 500_3, ..., 500_c-2, 500_c-1, 500_c.

Therefore, as shown in Fig. 34, for example, information bits corresponding to the information bits of 500_1, 500_2, 500_3, 500_4, ..., 500_c-2, 500_c-1, 500_c, for example, The address counted from the left end, that is, how many bits are obtained, and the sum of the addresses, the so-called checksum 501, is added to the second additional code. The number 502 of information bits of 500_1, 500_2, 500_3, 500_4, ..., 500_c-2, 500_c-1, 500_c is added to the second additional code.

For example, in Fig. 34, 500_1 is counted from the left end, and the third bit is 500_2, 500_2 is counted from the left end, and 500_3 is counted from the left end and corresponds to the seventh bit. As these checksums 501, 3 + 5 + 7 +... + (Position from the left end of the first information bit of 500_c-1) + (position from the left end of the first information bit of 500_c). In addition, when the number of "010" of WL (n-1) of 1st information bits is c, you may use c as the number 502 of information bits.

Compounding sequence

By the number of these checksums and information bits, for example, the "010" code of the opposing WL (n-1) of 500_1, 500_2, 500_3, 500_4, ..., 500_c-2, 500_c-1, 500_c Even if a 1-bit error occurs in the column, error correction can be performed. The code decoding method that may include the one-bit error is decoded by the sequence indicated by SE101 to SE107 in FIG.

Here, for example, first, if a "010" code string of WL (n-1) adjacent to 500_3 of WL (n) is "011", "000", or "110", a 1-bit error has occurred. do. Here, for the sake of simplicity, a 1-bit error is taken as an example, but even when the triple bit of "010" is set to 1 word and the "010" code string is converted to an incorrect word such as "111", it can be correctly restored.

When a one-bit error occurs in the "010" code string, first, a difference of the number of information bits 502 is obtained from the sum of the number of "010" patterns of WL (n-1) of the first information bits. For example, let this car be car A. If the difference A is not 1 or -1, it is determined that there is no sign error, and the information bits of WLn opposed to the part of "1" of "010" of the WL (n-1) of the first information bit, For example, it can decode by counting from the left side and replacing with 500a_1, 500a_2, 500a_3, ..., 500a_c-2, 500a_c-1, 500a_c (SE107). This may, of course, be arranged in the order in which the original information bits can be decoded according to the arrangement method performed at the time of encoding. The arrangement of these information bits can be similarly used in the modification of the present embodiment below.

In addition, when the difference A becomes -1, it becomes a branch of "Yes" in SE101, and WL (n-1 which opposes 500_1, 500_2, 500_4, ...., 500_c-2, 500_c-1, 500_c 1 word error occurs within the "010" code string, indicating that one "010" code string in WL (n-1) is lost. In the case of the "Yes" branch in SE101, that is, (sum of positions from the left end of the information bit of "1" in the code string of "010" of checksum 501- {WL (n-1)}). In this case, the position of the information bit of "1" in the code string "010" of WL (n-1), that is, in this case, the position of the information bit of 500_3 can be obtained (SE102). Since the information bit adjacent to the code string of "010" of WL (n-1) exists at the position of the information bit of 500_3 between the bit and the information bit of 500_4, since decoding has WL (n-1) For example, 500b_1, 500b_2, 500b_3, ....., 500b_c-2, 500b_c-1 by adding the position of the information bit of 500_3 to the information bit of WLn adjacent to the "1" part of "010" of the following. , 500b_c is counted from the left side and 500a_1, 500a_2, 500a_3, ...., 500a_c-2, 500a_c-1, 500a_c can be correctly decoded (SE103).

On the other hand, for example, an error in which a code string other than the "010" code string of WL (n-1) is changed to a word "010" has occurred. As an example, it is assumed that the sign of WL (n-1) between the position of 500_4 and the position of 500_5 is changed from "011" to "010".

When a 1-bit error occurs in a code string other than the "010" code string, first, a difference of the number of information bits 502 from the sum of the number of code sequences of "010" of WL (n-1) in the information bits is obtained. , Car A becomes one. When this difference A becomes 1, that is, in the case of a branch of "Yes" in SE104, the opposing first information bits of 500_1, 500_2, 500_3, ..., 500_c-2, 500_c-1, 500_c An error has occurred in the code string of WL (n-1), and this indicates that one "010" code string in WL (n-1) has been increased by one. In this case, WL (error) is obtained by taking {sum of positions from the left end of the information bit of "1" in the code sequence of "010" of WL (n-1)} (checksum 501). The position a of the information bit of "1" in the code string of "010" of n-1) can be obtained (SE105). Therefore, the bit of WLn corresponding to the position a of the information bit is skipped without changing, that is, the bit of WLn corresponding to the position a of the information bit is "010" of WL (n-1). By subtracting from the information bit string of WLn opposed to " 1 "in the code string, the information bits can be decoded correctly. In this example, for example, it is understood that the WL (n-1) code of the first information bit is incorrectly set to "010" at the position between the 500_4 and the 500_5 information bits. Information bits 500b_1, 500b_2, 500b_3, ...., 500b_c-2, 500b_c-1, 500b_c of WLn facing "1" of "010" of (n-1) are counted from the left, for example, 500a_1 , 500a_2, 500a_3, ...., 500a_c-2, 500a_c-1, 500a_c can be correctly decoded (SE106).

As described above, the decoding method for correcting the error of one bit described above can be corrected by one bit according to the flowchart shown in FIG. 35.

[Modifications According to Example 8]

Next, various modifications concerning the eighth embodiment will be described with reference to FIGS. 36A and 36B to 40. In this description, description of portions substantially overlapping with the eighth embodiment will be omitted.

First, for example, in Figs. 36A and 36B, the code structure of the "010" code string in WL (n-1) shows a code structure that can be corrected when two 1-bit errors occur. For example, the number of information bits corresponding to 500_1, 500_2, 500_3, 500_4, ...., 500_c-2, 500_c-1, 500_c, for example, the address counted from the left end of the information bits, that is, the number of bits And the so-called checksum 501 is added to the second additional code.

The number 502 of information bits of 500_1, 500_2, 500_3, 500_4, ..., 500_c-2, 500_c-1, 500_c is added to the second additional code. For example, an address counted from the left end of the information bit, that is, how many bits is obtained, and the product of the address, the so-called check product 503, is added to the second additional code.

36A and 36B, for example, 500_1 is counted from the left end and is the third bit, 500_2 is counted from the left end and fifth bit, 500_3 is counted from the left end and corresponds to the seventh bit. These check products 503 For example, 3 x 5 x 7 x ... ... (position from the left end of the first information bit of 500_c-1) x (position from the left end of the first information bit of 500_c). In addition, in the case of the information bits of 500_1, 500_2, 500_3, 500_4, ..., 500_c-2, 500_c-1, 500_c, c may be used as the number 502 of information bits.

The number of opposing WL (n-1) of 500_1, 500_2, 500_3, 500_4, ...., 500_c-2, 500_c-1, 500_c is determined by the number of these checksums, check products and information bits. Even if a two-word error occurs in the 010 "code string, error correction can be performed.

Sequence to modify bits in one word and two word error opposite positions

Next, a code that may include this two-word error will be described using a sequence decoded by the sequence indicated by SE100 to SE124 in FIGS. 37 and 38. Here, for example, the "010" code string assumes that a 1-bit error has occurred. In this case, using the sequence of SE100 to SE106 in FIG. 35 as in the eighth embodiment, one-bit error can be corrected.

Next, when the "010" code string in WL (n-1) has two word errors, the "010" code string in WL (n-1) is not "010" in two places. It shows the case where it is changed by information error by heat. In this case, first, the difference A is -2 by obtaining the difference of the number of information bits 502 from the sum of the number of information bits against the "010" pattern of the worst WL (n-1). When the difference A becomes -2, it becomes a branch of "Yes" in SE108 of FIG. 38, and opposes WL (n-) of 500_1, 500_2, 500_4, ..., 500_c-2, 500_c-1, 500_c. A two-word error occurred in the "010" code string of 1), indicating that the "010" code string in WL (n-1) has been lost by two words. In the case of the "Yes" branch in this SE108, that is, (checksum 501)-{sum of positions from the left end of the information bit of "1" in the code sequence of "010" of WL (n-1)} By taking the sum of the positions of the first information bits of " 1 " in the code string of " 010 " of the WL (n-1) where the error occurred, that is, in this case, the first information bits of the WL (n-1). An error of two words occurs within the block, so that the sum aa of the positions of the information bits in which the "010" code string in WL (n-1) is lost by two words can be obtained (SE109). Next, by taking (check product 503) / {multiplication of the position from the left end of the information bit of "1" in the code sequence of "010" of WL (n-1)} to the "010" word portion The product of the positions of the information bits of " 1 " in the code string of " 010 " of the WL (n-1) where an error has occurred, that is, in this case, two words within the " 010 " code string of WL (n-1). An error occurs and the product bb of the information bits in which the "010" code string in WL (n-1) is lost by two words can be obtained (SE110). Next, by using x as a variable and solving for the equation of x * x-aa * x + bb = 0, the "1" in the code sequence of "010" of WL (n-1) where the "010" error occurred is obtained. Two positions of the information bit and error positions 1 and 2 can be obtained (SE111). Next, the above two error positions 1 and 2 are added to the position of the information bit of WLn opposite to "1" in the code string of "010" of WL (n-1). Information bits 500b_1, 500b_2, 500b_3, ...., 500b_c-2, 500b_c-1, 500b_c of WLn facing "1" of "010" of (n-1) are counted from the left, for example, 500a_1 , 500a_2, 500a_3, ...., 500a_c-2, 500a_c-1, 500a_c can be correctly decoded (SE112).

Next, when the "010" code string in WL (n-1) has two 1-bit errors, the code string other than "010" of WL (n-1) is "010" in two places. It shows the case where it is changed by the information error in the column. In this case, first, the difference A is 2 by obtaining the difference of the number of information bits 502 from the sum of the number of information bits adjacent to the "010" pattern of the worst WL (n-1). If the difference A becomes 2, it becomes a branch of " YES " in SE113 in Fig. 38, and the WLs (n-1) opposing 500_1, 500_2, 500_4, ..., 500_c-2, 500_c-1, 500_c Indicates that a two-bit error occurs within the "010" code string and that two "010" code strings in WL (n-1) are increasing. In the case of the "Yes" branch in this SE113, that is, {sum of positions from the left end of the information bit of "1" in the code sequence of "010" of WL (n-1)}-(checksum 501) By taking the sum of the positions of the information bits of " 1 " in the code string of " 010 " An error occurs and the sum aa of the positions of the information bits in which the "010" code string in WL (n-1) is increased by two words can be obtained (SE114). Next, the error to "010" is obtained by taking {product of the position from the left end of the information bit of "1" in the code sequence of "010" of WL (n-1)} / (check product 503). The product of the positions of the information bits of " 1 " in the code string of " 010 " of WL (n-1), that is, in this case, a 2-word error occurs in the " 010 " code string of WL (n-1). Thus, the product bb of the information bits in which the "010" code string in WL (n-1) is increased by two words can be obtained (SE115). Next, using x as a variable and solving for the equation of x * x-aa * x + bb = 0, the WL (n-1) of "WL" where an error from the code string other than the "010" code occurs to "010" is generated. Two positions of the information bit of "1" in the code string of "010" and error positions 1 and 2 can be obtained (SE111). Next, using the information bits of WLn opposed to " 1 " in the code string of " 010 " of WL (n-1), and subtracting two positions of the information bits, that is, error positions 1 and 2, For decoding, the first information bits 500b_1, 500b_2, 500b_3, ..., 500b_c-2, 500b_c-1, 500b_c of WLn opposed to "1" of "010" of WL (n-1) are given as an example. For example, by counting from the left side, 500a_1, 500a_2, 500a_3, ..., 500a_c-2, 500a_c-1, 500a_c can be correctly decoded (SE117).

In addition, when the "010" code string in WL (n-1) generates two single word errors, the code string other than "010" in WL (n-1) is "010" code string in one place. In this case, the code string of "010" in WL (n-1) is changed to a code string other than "010" by an information error.

In this case, first, the difference A is zero by finding the difference of the number of information bits 502 from the sum of the number of information bits against the "010" pattern of the worst WL (n-1). When the difference A is other than -2, -1, 0, 1, and 2, a branch of "no" in SE118 in Fig. 38 is obtained, and the recovery of the information bit is impossible, for example, WL (n-1). Information bits 500b_1, 500b_2, 500b_3, ...., 500b_c-2, 500b_c-1, 500b_c of WLn opposite to "1" in the code string of "010"), 500a_1, 500a_2, 500a_3, ... And 500a_c-2, 500a_c-1 and 500a_c in order (SE124). In the SE118 of FIG. 38, the branch of "Yes" is compared with the product of the position from the left end of the information bit of "1" in the code string of "010" of {WL (n-1)}. In the same case, that is, in the case of a branch of "no" in SE119, the first information of WLn opposed to "1" in the code string of "010" of WL (n-1) is assumed to have no error in the information bit. Replace the bits 500b_1, 500b_2, 500b_3, ...., 500b_c-2, 500b_c-1, 500b_c with 500a_1, 500a_2, 500a_3, ...., 500a_c-2, 500a_c-1, 500a_c in sequence (SE124 ).

In addition, in SE119, in the case of the branch of "Yes", the code string other than "010" of WL (n-1) is changed to the "010" code string by the information error in one place, and one place is used. Indicates that the code string of " 010 " of WL (n-1) is changed by an information error to a code string other than " 010 ". In this case, (the sum of the positions from the left end of the information bit of "1" in the code sequence of "010" of 501- {WL (n-1) where the checksum is recorded) is obtained (SE120). (Equivalent to the position of "1" in the "010" word of the information bits of WL (n-1) lost)-(the position of "1" in the "010" word of the WL (n-1) information bits with increased error) Next, the product of the position from the left end of the information bit of " 1 " in the code sequence of " 010 " bb is (the position of "1" in the "010" word of the information bit of WL (n-1) lost) / ("1" in the "010" word of the WL (n-1) information bit with error increment) From these, error position 1, i.e., the position of "0" in the word "010" of the information bits of the lost WL (n-1) is obtained at aa / (bb-1). The error position 2, i.e., the position of "1" in the word "010" of the information bit of the error increased WL (n-1), is found at aa * bb / (bb-1) (SE122). 1st information bit 500b_1 which added and subtracted the information bit of WLn of the position of error position 1 and 2 from the information bit of WLn which opposes "1" in the code string of "010" of WL (n-1). , 500b_2, 500b_3, ...., 500b_c-2, 500b_c-1, 500b_c are replaced with 500a_1, 500a_2, 500a_3, ...., 500a_c-2, 500a_c-1, 500a_c in sequence (SE123).

In view of the above, even in the case where two " 010 " code strings in WL (n-1) have two word errors, they can be corrected according to the flowchart.

In the above embodiment, as the number 502 of information bits, in the case of the third embodiment, α = {the value obtained by truncating (k / 6) to an integer} -1 and in the case of Examples 1 and 2, α = When {(k / 4) is cut off to an integer} -1, the number of bits corresponding to the value of log ₂ {α} is cut off to an integer may be prepared. As the checksum 501, if the number of bits corresponding to a value obtained by cutting log ₂ {k (k + 1) / 2} into integers is prepared, the sum can be stored without information loss. As the check product 503, if the number of bits corresponding to a value obtained by cutting αxlog ₂ {k} into an integer is prepared, the product can be stored without information loss.

Here, as the checksum 501, two words within k bits may be designated when correcting up to two words as described above. In addition, since the sum of the addresses of the word error positions does not exceed 2k, the checksum 501 may prepare as many bits as the minimum value of log ₂ {2k}. In addition, even if the part of the sum of the addresses exceeding the prepared number of bits is ignored and considered to match, the decoding can be performed correctly.

As the check product 503, when correcting up to two words, two bits within k bits may be designated. In addition, since the product of a word error position does not exceed k * k, the check product 503 should just prepare the number of bits as much as the value which cut off 2log ₂ {k} to an integer. In addition, even if the part of the product of the addresses exceeding the prepared number of bits is considered to be ignored and compared, decoding can be performed correctly.

From the above, the code lengths of 500a_1, 500a_2, 500a_3, ..., 500a_c-2, 500a_c-1 and 500a_c in the second code are approximately α in proportion to k. Therefore, when k is 1 kbit = 2 ^ 10 bits, reference numeral 501 is a value of log ₂ {2k} truncated to an integer of about 11 bits, and the number of information bits 502 is at most log ₂ {α} as an integer. The cut-up value of 10 bits or less and the reference numeral 503 may be prepared by cutting the value of ₂ log ₂ {k} to an integer of 20 bits at most, and the sum of these is 41 bits at most. Therefore, this is less than 25% compared to {(k / 6) truncated to an integer} -1 to 170 bits of α, and 25% compared to the case where error correction is not performed even when two bits are corrected. The degree of extension of the code length of the second additional code can be suppressed.

Of course, for example, if k is larger than 1 kbit, the code length required for the checksum 501, the number of information bits 502, and the check product 503 increases only in proportion to log ₂ (k). Since it does not increase compared to k, the ratio to α becomes small. Therefore, even if the increase rate with respect to the code length of the checksum 501, the number of information bits 502, and the check product 503 is small, error correction can be carried out.

For example, if 64 kbit = 2 ^ 16 bits, the checksum 501 is a value of log ₂ {2k} truncated to an integer of about 17 bits, and the number of information bits 502 is at most log ₂ {α}. It is sufficient to prepare a value of 16 bits or less, truncated to ₂ log ₂ {k} to an integer of 32 bits, and the sum thereof is 65 bits. Thus, this is less than 0.6% compared to {(k / 6) truncated to integer} -1 to 10922 bits of α. Therefore, even when the error correction of two words is performed, it can be suppressed to the extent that the code length of the second additional code is increased by 0.6% compared with the case where the error correction is not performed.

As described above, the length of 500a_1, 500a_2, 500a_3, ...., 500a_c-2, 500a_c-1, 500a_c is obtained by using the encoding that forms the second additional code from the first information bits having k bits. Α is sufficient. Therefore, when k is 1024 bits or more, the second additional code length is 25% longer than α even if the checksum 501, the number of information bits 502, and the check product 503 are added. It becomes less than 211 bits so that code length can be shortened significantly rather than kbit of a 1st information bit. The number of information bits of WLn adjacent to the "010" portion of WL (n-1) described above can be suppressed to be equal to or less than half of the length of the second additional code length.

Example of applying the coding according to the first to third embodiments with respect to the second additional code of WL (n)

Next, with reference to FIG. 39A, FIG. 39A, FIG. 39B, FIG. 39B, FIG. 39B, and FIG. 39B, the second additional code of WL (n) is used in this embodiment. The configuration to which the encoding described in Embodiments 1 to 3 is applied will be described. (A), (b) of FIG. 39A, and (a), (b) of FIG. 39B are an example of the method. FIG. 39A shows a method for reducing the number of information bits of WLn adjacent to the " 010 " portion of WL (n-1) from Embodiments 1 to 3 with respect to the second additional code described above. Is using.

As shown in the drawing, the relationship between the second additional reference code described with reference to Figs. 30 to 38 and WL (n-1) and WL (n) is explained. Further, the flag 1 equivalent information of the second additional code with the WL (n-1), the information of the flag 2 of the second additional code, and the flag 1 equivalent information of the third additional code and the third additional code, and the third The information of the flag 2 of the additional code is added. In order to reduce the number of " 010 ", these flags 1 and 2 are obtained by applying the first to third embodiments to the first information bit, the second additional code, and the third additional code, respectively, and a detailed description thereof will be omitted. .

Here, as shown in Fig. 39A (b), by applying Embodiments 1 to 3 to the second additional code, the flag 1 equivalent information of the second additional code and the flag 2 equivalent information of the second additional code are added. , The code string of "010" included in the second additional code included in WL (n) can be reduced. This means that when the second additional code length is k2, in the case of Example 3, {(k2 / 6) is truncated to an integer}} and in the case of Examples 1 and 2, {(k2 / 4) Can be reduced to a value} -1, which is a code string of " 010 " of WL (n). Thereby, the number of "0" of the information bits of WL (n + 1) adjacent to the "010" portion of WL (n) can be reduced.

In addition, in the case of Example 3, in the case of Example 3, in the case of Example 3, when {(k2 / 6) was cut off to an integer} -1 and Examples 1 and 2, , {(k2 / 4) is an integer}}, and the number in which the code string of "010" of WL (n-1) is included can be reduced.

In addition, as shown in FIG. 39B (a), the second additional code of WL (n) shown is replaced with the first information bit, and the second additional code is replaced with the third additional code, thereby reducing the WL of the second additional code. Information bits of WLn adjacent to the " 010 " portion of n-1) are extracted to form a third code of WL (n). For example, when k is 1024 bits or more, the second additional code length can significantly shorten the code length within 211 bits, and k2 can be 211 bits. Further, in the application of Fig. 39B (a), {(k2 / 6) is rounded down to an integer number of times the information bit of WLn adjacent to the "010" portion of WL (n-1) is "0". It can be reduced to 1 to 35 bits.

39B (b), similarly to Embodiments 1 to 3, by adding the flag 1 equivalent information of the third additional code and the flag 2 of the third additional code, the agent included in WL (n) is added. 3 The code string of "010" included in the additional code can be reduced. This means that when the third additional code length is k3, in the case of Example 3, {(k3 / 6) is truncated to an integer}} and in the case of Examples 1 and 2, {(k3 / 4) The number truncated to an integer}-1 can reduce the number which is the code string of "010" of WL (n). Thereby, the number of "0" of information bits of WL (n + 1) adjacent to the "010" portion of WL (n) can be reduced.

In addition, in the case of Example 3, in the case of Example 3, in the case of Example 3, when {(k2 / 6) was cut off to an integer} -1 and Examples 1 and 2, The number of code strings of "010" of WL (n-1) can be reduced to {{k2 / 4) truncated to an integer} -1.

In addition, although not shown in the figure, by repeating the code conversion for forming the third additional code from the second additional code in this example, the number of "0" s of WLn adjacent to the "010" portion of WL (n-1) is repeated. Clearly enough can be done. If the number of "0" s in WLn adjacent to the "010" portion of WL (n-1) is, for example, 10 or less, this code conversion is repeated a plurality of times, without increasing the code length by 10 bits or more. It is easy to set it to zero. As described in the description of the flags from the first to the third embodiments, a method of allocating flags 1 and 2 by 2 bits is described in terms of "0" of WLn adjacent to the "010" portion of WL (n-1). It can be used for the number. Specifically, "010" portion of WL (n-1) is set to "0110", and "00" is set to "0" when the bit of WLn adjacent to "010 portion is set to" 0 ". This can be done by allocating.

On the other hand, in order to decode this code, first, the second additional code string of WLn opposed to "1" in the code sequence of "010" of WL (n-1) is replaced with the third additional code in order. Of course, at this time, the information error correction using the checksum, the number of codes, and the check product described above may be performed to further reduce the information error of the code string of "010" of the WL (n-1).

In addition, the code string of the information bits of WLn opposed to "1" in the code string "010" of WL (n-1) is replaced with the second additional code in order. As a result, the first information can be decoded. It is clear that by repeating these methods recursively, even if the fourth additional code is formed from the third additional code, it can be decoded.

In addition, although this description showed that the sign of the sum and the product is used to correct an error of 2 words, of course, by using a so-called majority vote, for example, a plurality of error positions can also be corrected. have.

In addition, in the present embodiment, an example in combination with the embodiments of the first to third embodiments has been described. For example, in the code using the code occurrence probability averaging circuit 106 for a code of 8 kbit or more, the first to third embodiments will be described. Even without using the example combined with the Example of 1, the modified example of this embodiment with which an effect is acquired can be comprised. Here, the code appearance frequency of the " 010 " consecutive bit portion of WL (n-1) is (code length) x (1/2) ^ 3-1 = (code length) from the law of algebra as the code length becomes longer. It is distributed in a very narrow range around / 8-1.

Distribution width of frequency of "010" occurrence number

Next, using FIG. 40, the distribution width of the frequency of the "010" appearance number calculated | required by the present inventors is demonstrated. As shown in Fig. 40, the number of " 010 " consecutive bits included in the case where the code length is 8 kbit (= 8192 bit) is the horizontal axis and the vertical axis is a log number whose limit is 10 which is the frequency of occurrence of the code for the number ( In this case, γ is taken.

In this example, it was found that the bit corresponding to (8 kbit) / 8-1 = 1023 bits is the frequency at which "010" occurs most, and gamma is distributed in a nearly normal distribution shape. In addition, in the code length of 8 bits or more, in the range exceeding the code length of 1023 bit +/- 20%, it turns out that (gamma) ^-10 or less of the frequency of appearance of the code of the most frequent value, namely, only 10 ^-10 or less is generated as a code generation frequency. It was. In the code using the coding probability averaging circuit 106 for a code of 8 kbit or more, the probability of occurrence of "0" and "1" is also averaged for the bits of WL (n) adjacent to the bits of WL (n-1). It is possible to.

When this is applied, the most frequent number of "0" s in WLn adjacent to the "010" portion of WL (n-1) is [(code length) x (1/2) ^ 3-1] / 2. Can be reduced to the number rounded to an integer = [(sign length) / 8-1] / 2 to an integer. Therefore, even when the combination of the first to third embodiments is not used together, for example, when the coding probability averaging circuit 106 is used for a code of 8 kbit or more, for example, α of the second encoding is {(k By multiplying / 16 by an integer} * 1.2 times, the number of symbols whose number of information bits " 0 " of WLn adjacent to the information bit " 010 " By recursively repeating the encoding described in 39b, the number of " 0 " s of WLn adjacent to the " 010 " portion of WL (n-1) can be reduced to zero.

Further, the number of the number of information bits " 0 " of WLn adjacent to the information bit " 010 " portion of WL (n-1) is greater than α indicates that the number of symbols of WLn adjacent to the " 010 " Although the number of "0" cannot be reduced to 0, it can be reduced by α. That is, it can fully reduce to the number of codes of 1 ppm or less among all codes. Therefore, in the case where an arbitrary threshold value permits the occurrence of a sign error of the number of " 0 " of WLn adjacent to the " 010 " portion of WL (n-1), it is also possible to form a short second code.

For example, when all code combinations of code length ka and kb code | symbol are comprised, all combinations of the code of code length ka and all the code of kb are considered. The product of the sign length of (ka + kb) is formed by multiplying by. Therefore, if the logarithm is taken for the number of states of the frequency of appearance of the sign, the product is converted into a sum according to the logarithm, so the law of algebra is established.

As mentioned above, for codes longer than 8 kbit, (variation) / (average value) of the occurrence frequency of WL (n-1) "010" can be made small from the logarithmic law, The number of " 0 " s of WLn adjacent to the 010 " portion can be further reduced in the case of 8 kbit in all codes.

In addition, although α of the second coding is set to {(value cut out of k / 16 to an integer} * 1.2 times), for example, by increasing and decreasing this 1.2 times,? Is almost distributed in a normal distribution shape. It is clear that the probability of occurrence of the number of information bits " 0 " of WLn adjacent to the information bit " 010 " portion of the WL (n-1) in the entire code can be made less than or equal to the set value. Is a normal distribution function with N (mean, standard deviation), and a logarithmic value with a limit of 10 as the sign generation frequency is proportional to N (1023, 2100) when the number of "010" is between 800 and 1200. Since it can be approximated well by a distribution function, it is easy to calculate the probability of occurrence of the sign and the cumulative occurrence probability of the code of α or more.

In addition, in the modification of the present embodiment, as described in the present embodiment, of course, the information error correction using the checksum, the number of codes, and the check product described above is combined to the code string of "010" of WL (n-1). Information errors may be further reduced.

Here, in the modified example of the present embodiment, similarly to Fig. 21 of the fourth embodiment, the first encoding circuit 106 which averages the code occurrence probabilities of the input bits, outputs the information bits, and inputs the information bits, The configuration differs in that the first decoding circuit 107 decodes the input bits.

The present invention is not limited to the above embodiment.

That is, in Embodiments 1 through 4, at most 4 bits or 6 bits of flag bits are added to reduce the number of threshold rising bits due to capacitive coupling by write or adjacent memory cells. It has the effect of reducing to 3 or less. Therefore, when the error bit occurs i bits and the code length is increased by f (i) bits due to the threshold value increase due to these write operations or the capacitive coupling by adjacent memory cells, by using the above embodiment, f ( When i)> f (i / 2) +4 [bit] is satisfied, the first and second embodiments have an effect of reducing the area of the NAND memory array cell. In Embodiment 3, when f (i)> f (i / 3) +6 [bit] is satisfied, the area of the NAND memory array cell can be reduced. Here, in the BCH code, the code after the BCH encoding using the information bit length as m, and f (i) = i x (cut off log ₂ m + 1 to an integer) to i-bit correct an error bit The code length is increased by. Therefore, in the case of using the BCH code, it is effective to substitute and use the range where the above inequality holds for f (i). For example, if 2 is used as i, if m is 16 bits or more, the conditions of Embodiments 1 and 2 are sufficiently satisfied, and if 512 bits or more, the conditions of Examples 3 and 4 can be sufficiently satisfied.

In addition, in the RS code, in order to correct an error bit by i byte by making the information bit a code consisting of 1 byte of 2 ^j , i x 2 bytes = i x 2 x j bit code length is increased. Therefore, in the case of using the RS code, it is effective to substitute and use f (i) the range where the above inequality holds. For example, if 2 is used as i, if 2 ^{j is} 8 bits or more, the conditions from Embodiments 1 to 4 can be sufficiently satisfied.

Also in the present embodiment, as in the first to third embodiments, only a calculation amount proportional to the information bit length is required for the second encoding and the decoding of the second code, and the encoding does not depend on the number of error bits. It is. On the other hand, when the number of error correction code error correction bits, such as an RS code or a BCH code, increases, the decoding time of the reference code 103 increases to a power of two or more of the error correction bits. Therefore, when the second coding from the first embodiment to the fourth is applied in combination with the error correction coding of reference numeral 102 or the decoding of the error correction code of reference numeral 103, it is necessary to use a capacitive coupling by writing or adjacent memory cells. The error bits can be reduced due to the increase in the threshold value, so that the sign necessary for error correction can be shortened, and the total amount of calculation and circuit necessary for decoding can be reduced.

Further, the counters 108, 109, 112, 113 described in Embodiments 1 and 2, the registers a, b, c, d described in Embodiment 3, and the counters 116, 117, 118, 119 described in Embodiment 4 , And the number of bits required in registers e, f, g, and h is enough to have a counter and register bit number of at most (log ₂ m + 1 truncated to an integer) with m information bits. In addition, it can be realized on a small circuit scale equivalent to a pointer indicating the position of the error correction point.

Further, the counters 108, 109, 112 and 113 described in the first and second embodiments, the registers a, b, c and d described in the third embodiment and the counters 116, 117, 118 and 119 described in the fourth embodiment And an example of branching SE by comparing the counts between registers e, f, g, and h, for example, when the counts of the counters or registers to be compared are the same, you may branch to the YES side, You may branch to the "no" side.

For example, in SE7, the counter 108> the counter 109 branches to YES. However, in the case of the counter 108 ≥ counter 109, the branching to YES may be performed. In addition, it is not necessary to branch. Similarly, in SE17, when the minimum value of the counter 108 and the counter 109 is larger than the minimum value of the counter 112 and the counter 113, it branches to the YES side, but the counter 108 and the counter 109 When the minimum value is equal to or larger than the minimum value of the counter 112 and the counter 113, it may be branched to the YES side. In addition, in SE19, in the case of the counter 112> counter 113, it branches to YES, but in the case of the counter 112≥counter 113, you may branch to YES. In SE21, the counter 118> the counter 119 branches to YES. However, in the case of the counter 108 ≥ counter 119, the branching to YES may be performed.

Similarly, in SE34, when the minimum value of register a and register b is larger than the minimum value of register c and register d, branching is made to the YES side, but the minimum value of register a and register b is greater than or equal to the minimum value of register c and register d. It may be branched to the YES side. In SE37, when the value of the register c is larger than the value of the register d, the branching is YES. However, when the value of the register c is equal to or higher than the value of the register d, the branching may be YES. In SE39, if the value of the register a is larger than the value of the register b, the branching is YES. However, if the value of the register a is the value of the register b or more, the branching may be YES.

Similarly, in SE63, when the minimum value of the counter 116 and the counter 117 is larger than the minimum value of the counter 118 and the counter 119, it branches to the YES side, but the counter 116 and the counter 117 When the minimum value is equal to or larger than the minimum value of the counter 118 and the counter 119, it may be branched to the YES side. In the SE65, the counter 118> the counter 119 branches to YES. However, the counter 108 ≥ the counter 109 may branch to YES. In SE67, the counter 116> the counter 117 branches to YES. However, the counter 116> the counter 117 may branch to YES.

Similarly, in SE70, when the minimum value of register e and register f is larger than the minimum value of register g and register h, branching is made to the YES side, but the minimum value of register e and register f is equal to or greater than the minimum value of register g and register h. It may be branched to the YES side. In SE75, if the value of the register e is larger than the value of the register f, branching is performed to YES. However, the branching may be branched to YES if the value of the register e is greater than or equal to the value of the register f. In SE73, if the value of the register g is larger than the value of the register h, the branching is YES. However, if the value of the register g is equal to or higher than the value of the register h, the branching may be YES.

Further, the counters 108, 109, 112, 113 described in Embodiments 1 and 2, the registers a, b, c, d described in Embodiment 3, and the counters 116, 117, 118, 119 described in Embodiment 4 , And the example of branching SE by comparing the counts between the registers e, f, g, and h, are described. For example, when the counts of the counters or registers to be compared are the same, the branching may be performed on the YES side. You may branch to "NO" side. For example, in SE7, the counter 108> the counter 109 branches to YES. However, in the case of the counter 108 ≥ counter 109, the branching to YES may be performed. In addition, it is not necessary to branch. Similarly, in SE17, when the minimum value of the counter 108 and the counter 109 is larger than the minimum value of the counter 112 and the counter 113, it branches to the YES side, but the counter 108 and the counter 109 When the minimum value is equal to or larger than the minimum value of the counter 112 and the counter 113, it may be branched to the YES side. In addition, in SE19, in the case of the counter 112> counter 113, it branches to YES, but in the case of the counter 112≥counter 113, you may branch to YES. In the SE21, the counter 108> the counter 109 branches to YES. However, the counter 108> the counter 109 may branch to YES.

Similarly, in SE34, when the minimum value of register a and register b is larger than the minimum value of register c and register d, branching is made to the YES side, but the minimum value of register a and register b is greater than or equal to the minimum value of register c and register d. It may be branched to the YES side. In SE37, when the value of the register c is larger than the value of the register d, the branching is YES. However, when the value of the register c is equal to or higher than the value of the register d, the branching may be YES. In SE39, if the value of the register a is larger than the value of the register b, the branching is YES. However, if the value of the register a is the value of the register b or more, the branching may be YES.

Similarly, in SE63, when the minimum value of the counter 116 and the counter 117 is larger than the minimum value of the counter 118 and the counter 119, it branches to the YES side, but the counter 116 and the counter 117 When the minimum value is equal to or larger than the minimum value of the counter 118 and the counter 119, it may be branched to the YES side. In the SE65, the counter 118> the counter 119 branches to YES. However, the counter 108 ≥ the counter 109 may branch to YES. In SE67, the counter 116> the counter 117 branches to YES. However, the counter 116> the counter 117 may branch to YES.

Similarly, in SE70, when the minimum value of register e and register f is larger than the minimum value of register g and register h, branching is made to the YES side, but the minimum value of register e and register f is equal to or greater than the minimum value of register g and register h. It may be branched to the YES side. In SE75, if the value of the register e is larger than the value of the register f, the branching is YES. However, if the value of the register e is the value of the register f or more, the branching may be YES. In SE73, if the value of the register g is larger than the value of the register h, the branching is YES. However, if the value of the register g is equal to or higher than the value of the register h, the branching may be YES.

In addition, although the embodiment described the method of performing the second encoding before the error correction code, the method of performing the second encoding by including the check bit after forming the error correction code, the order of reference numerals 104 and 102, and reference numeral 105 The order of and 103 may be replaced. In this case, the code corresponding to the flag bit may be added by using a majority decision code such as aaa indicating 3 bits of information of one a bit. Of course, you may create and convert an error correction code with respect to a flag bit separately.

In addition, when the order of the reference numerals 104 and 102 and the order of the reference numerals 105 and 103 are replaced, the second encoding of the first to fourth embodiments is replaced by replacing the information bits with error correction codes for all the error correction codes. The method may be applied, or the information bits included in the error correction code may be extracted to perform second encoding of this portion. It is more preferable that the second encoding is performed on the entirety of the former error correction code, since the number of occurrences of "010" including the check bit and the adjacent word line can be reduced.

In all of the embodiments, the insulating film forming method itself of the element isolation film or the interlayer insulating film is a method other than those for converting silicon into a silicon oxide film or a silicon nitride film, for example, a method of injecting oxygen ions into the deposited silicon, or a deposited film. You may use the method of oxidizing silicon. The charge storage layer 26 may be formed of TiO ₂ , Al ₂ O ₃ , a tantalum oxide film, strontium titanate or barium titanate, lead zirconium titanate, or a laminated film thereof. As an example, a p-type Si substrate is assumed as the semiconductor substrates 1 and 1 ', but instead of an SOI silicon layer of an n-type Si substrate or an SOI substrate, or a single crystal semiconductor substrate containing silicon such as a SiGe mixed crystal or a SiGeC mixed crystal, do. Although the formation of the n-type MONOS-FET on the p-type semiconductor layer 23 has been described, the formation of the p-type MONOS-FET on the n-type semiconductor layer 23 may be substituted, in which case the source of the above-described embodiment The n-type for the drain electrode and the semiconductor region may be replaced with p-type and p-type with n-type, and As, P, and Sb of the doping impurity species may be replaced with any one of In and B. In addition, the gate electrodes 8 and 8 'can use Si semiconductor, SiGe mixed crystal, and SiGeC mixed crystal, polycrystal may be sufficient, and these laminated structures may be sufficient. In addition, amorphous Si, amorphous SiGe mixed crystal, or amorphous SiGeC mixed crystal can be used, and these laminated structures may be used. However, it is preferable that it is a semiconductor, especially a semiconductor containing Si, since the favorable sidewall insulating film 19 can be formed by the oxidation or oxynitride of the gate electrode 51. The charge accumulation layer 5 may be separated from the source drain or may be formed in a dot shape, and of course, the present method can be applied. In this embodiment, the cross section of the metal reinforcing layer 27 'formed by the deposition method on the gate electrode 8 or 8' has been described. For example, Ti, Co, Ni, Mo, Pd, Pt and The same metal may be reacted with the gate electrode 27 to form silicide and the metal reinforcement layer 11 may be formed.

In addition, in the embodiment of the present application, in order to make the description clear, an embodiment of the binary semiconductor memory cell transistors of "0" and "1" has been described. However, in the case of using a semiconductor memory cell transistor that stores two or more multiple values, Since the interval between the plurality of threshold values is narrower than this, the threshold value increase due to the capacitive coupling with the adjacent memory cells and the write-in become a problem, so that it is obvious that a greater effect can be obtained. In this case, the threshold value stored in one memory cell is preferably 2 ⁿ , which is preferable because the decoding of the information data is simplified.

In addition, the said Example includes the following aspects.

(1) a memory cell which stores at least binary data of " 1 " and " 0 " as the charge of the charge storage layer and uses the difference between the two charge amounts of the charge storage layer as write bits and erase bits; A nonvolatile memory cell array (reference numeral 49 in FIG. 5) for collectively erasing pages in which the memory cells of the plurality are formed adjacent to each other; An error correction code generation circuit (reference numeral 104 in Fig. 30) for generating a correction code for correcting at least one bit of error data from the second information bits; An error correction code decoding circuit (reference numeral 105 in Fig. 30) which corrects an error from the correction code and restores the second information bit; A code conversion circuit for outputting to the error correction code generation circuit; The code conversion circuit (reference numeral 104 in Fig. 30) detects a continuous bit array of write bits / erase bits / write bits of information bits of a second page physically adjacent to the first page to write, The fifth circuit (reference numeral 105 in Fig. 30) outputs the bits of the first page adjacent to the erase bits, which are in a contiguous bit array of two pages of write bits / erase bits / write bits; When the fifth circuit detects a continuous bit array of write bits / erase bits / write bits, the first page adjacent to an erase bit in the continuous bit array of write bits / erase bits / write bits of the second page. Replace the bits with erase bits, generate coded information bits, output a series of first pages of the fifth circuit as a second code, add the coded information bits of the second page, and Code generating means for generating information bits; Write bit / erase bit / write bit of the second page when detecting a continuous bit array of write bits / erase bits / write bits of information bits of a physically adjacent second page as input of the second information bit And decoding means for substituting the bits of the first page adjacent to the erase bits in the contiguous bit array of the data with a series of bits of the second code.

(2) In the data storage system of (1), a first counter circuit (WL (n-1) in FIG. 31) for detecting the number of consecutive bit arrays of write bits / erase bits / write bits of the input information bits. An output of " H " A second counter circuit which takes an exclusive logical sum of the inputted information bits and a plurality of bits in which the array of write bit-erase bits is repeated a plurality of times, and detects the number of consecutive bit arrays of write bits / erase bits / write bits; When the number of arrangements of the outputs of the two counter circuits is smaller than the number of arrangements of the outputs of the first counter circuit, exclusively of the plurality of bits in which the information bits selectively input and the arrangement of write bit-erase bits are repeated a plurality of times. And a code conversion circuit which takes a logical sum and outputs it to the error correction code generation circuit.

(3) In the data storage system of (1), information of the sum of the addresses of the consecutive bit arrays of the write bit / erase bit / write bit of the second page and the write bit / erase bit / write bit of the second page. Information of the number of consecutive bits is added to the second information bits (described in FIG. 34).

(4) In the data storage system of (1), the information of the product of the address of the continuous bit array of the write bit / erase bit / write bit of the second page is added to the second information bit (described in FIG. 34). .

(5) In the data storage system of (1), when the second code is input and the continuous bit array of write bits / erase bits / write bits is detected by the fifth circuit, the write bits of the second page. Replace the bits of the first page adjacent to the erase bits in the contiguous bit array of / erase bits / write bits with erase bits, generate an encoded second code, and output the output of the first series of pages of the fifth circuit. Code generating means for generating a third information bit in addition to the encoded second code of the second page as a third code; Write bit / erase bit / write of the second page when the third information bit is input and a continuous bit array of write bits / erase bits / write bits of information bits of a physically adjacent second page is detected. Decoding means for substituting the second code of the first page adjacent to the erase bit in the continuous bit array of bits with the series of bits of the third code is further provided (described in Figs. 39A and 39B).

(6) the data storage system of (1), comprising: a first encoding circuit (reference numeral 106 in Fig. 4) for averaging the code occurrence probability of the input bits and outputting the information bits; A first decoding circuit (reference numeral 107 in Fig. 4) is further provided for inputting an information bit and decoding the input bit.

In addition, various modifications can be made without departing from the spirit of the invention.

Those skilled in the art will readily come up with additional advantages and modifications. Accordingly, the invention in its broadest sense is not limited to the description and representative embodiments illustrated and described herein. Accordingly, various modifications are possible without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 illustrates a NAND cell array structure and a problem of capacitive interference between adjacent cells according to a comparative example of the present invention.

2 illustrates threshold distribution and margin reduction of a NAND cell according to a comparative example.

Fig. 3 is a diagram for explaining a method of creating a shortened code of a comparative example BCH code.

4 is a block diagram of a data storage system according to Embodiment 1 of the present invention.

Fig. 5A is a diagram showing the memory cell structure according to the first embodiment.

Fig. 5B is a diagram showing the memory cell structure according to the first embodiment.

6A is a diagram showing a cross section of a memory cell according to the first embodiment;

6B is a diagram showing the structure of a memory cell according to the first embodiment;

FIG. 7 is a flowchart for explaining a second code conversion according to the first embodiment; FIG.

8 is a flow chart for explaining a second code inverse transform according to the first embodiment.

9A is a view for explaining an example of the second code conversion according to the first embodiment.

9B is a view for explaining an example of the second code conversion according to the first embodiment.

9C is a diagram for explaining an example of the second code conversion according to the first embodiment.

9D is a view for explaining an example of the second code conversion according to the first embodiment.

9E is a view for explaining an example of the second code conversion according to the first embodiment.

10 is an equivalent circuit diagram showing a configuration example of a symbol counter according to the first embodiment.

Fig. 11 is a block diagram of a data storage system according to the second embodiment of the present invention.

12 is a flowchart for explaining a second code conversion according to the second embodiment.

Fig. 13 is an equivalent circuit diagram showing a configuration example of a symbol counter according to the second embodiment.

14 is a diagram for explaining an example of a second code conversion according to the second embodiment.

Fig. 15 is a block diagram of a data storage system according to the third embodiment of the present invention.

Fig. 16A is an equivalent circuit diagram showing an example of the configuration of a page buffer according to the third embodiment.

16B is an equivalent circuit diagram showing an example of the configuration of a page buffer according to the third embodiment.

17A is a timing chart showing an example of formation of a page buffer according to the third embodiment.

17B is a timing chart showing an example of formation of a page buffer according to the third embodiment.

17C is a timing chart showing an example of formation of a page buffer according to the third embodiment.

17D is a timing chart showing an example of formation of a page buffer according to the third embodiment.

17E is a timing chart showing an example of formation of a page buffer according to the third embodiment;

17F is a timing chart showing an example of formation of a page buffer according to the third embodiment.

Fig. 18A is a flowchart for explaining a second code conversion according to the third embodiment.

18B is a flowchart for explaining a second code conversion according to the third embodiment.

18C is a flow chart for explaining a second code conversion according to the third embodiment.

FIG. 19 is a flowchart for explaining a second code inverse transform according to the third embodiment; FIG.

20A is a view for explaining an example of the second code conversion according to the third embodiment.

20B is a view for explaining an example of the second code conversion according to the third embodiment.

20C is a diagram for explaining an example of the second code conversion according to the third embodiment.

Fig. 21 is a block diagram of a data storage system according to the fourth embodiment of the present invention.

Fig. 22 is an equivalent circuit diagram showing a configuration example of a symbol counter according to the fourth embodiment.

Fig. 23A is a flowchart for explaining a second code conversion according to the fourth embodiment.

Fig. 23B is a flowchart for explaining a second code conversion according to the fourth embodiment.

Fig. 23C is a flowchart for explaining a second code conversion according to the fourth embodiment.

Fig. 23D is a flow chart for explaining the second code conversion according to the fourth embodiment.

Fig. 24A is a sectional view of a memory cell array in accordance with embodiment 5 of the present invention.

Fig. 24B is a sectional view of the memory cell array according to the fifth embodiment.

Fig. 25A is an equivalent circuit diagram of a memory cell array according to Embodiment 6 of the present invention.

25B is a plan view of a memory cell array according to the sixth embodiment;

Fig. 25C is a sectional view of the memory cell array according to the sixth embodiment.

Fig. 25D is a cross sectional view of the memory cell array according to the sixth embodiment;

Fig. 26A is a layout diagram of a NAND type memory cell array according to the sixth embodiment.

Fig. 26B is a layout diagram of an NROM type memory cell array according to the sixth embodiment.

Fig. 27 is a sectional view of an NROM type memory cell array in accordance with a seventh embodiment of the present invention.

Fig. 28 is a sectional view of an NROM type memory cell array according to the seventh embodiment.

FIG. 29 shows an example of one effect of rearrangement according to Examples 1 to 3. FIG.

30 is a block diagram of a data storage system according to the eighth embodiment;

FIG. 31 is a circuit diagram illustrating a configuration example of a fifth circuit in FIG. 30.

32 is a circuit diagram showing a configuration example of a page buffer according to the eighth embodiment;

33 is a flowchart of code formation according to the eighth embodiment;

Fig. 34 is a view for explaining an example of the second code according to the eighth embodiment.

35 is a sequence diagram for correcting a corresponding position of a one word error according to the eighth embodiment;

36 is a diagram for explaining an example of a second additional code according to the eighth embodiment;

37 is a sequence diagram for correcting a corresponding position of a one word error according to the eighth embodiment;

38 is a sequence diagram for correcting a corresponding position of a two word error according to the eighth embodiment;

Fig. 39A (a0) A diagram for explaining an example of using the neighbor memory disturb reduction code conversion recursively according to the eighth embodiment.

FIG. 39A (b) is a diagram for explaining an example of using the adjacent memory disturb reduction code conversion recursively according to the eighth embodiment; FIG.

FIG. 39B (a) is a diagram for explaining an example of using the adjacent memory disturb reduction code conversion recursively according to the eighth embodiment; FIG.

39B (b) is a diagram for explaining an example of recursively using the adjacent memory disturb reduction code conversion according to the eighth embodiment;

40 is a diagram showing a distribution of frequencies of code appearances according to the eighth embodiment;

<Explanation of symbols for the main parts of the drawings>

1: memory cell array

2: data control line driver

3: low decoder

40: control circuit

42: substrate potential control circuit

41a: Vpqm generating circuit

41b: Vpass generation circuit

41c: Vread generating circuit

41d: Vref generating circuit

46: sense amplifier / data register

47: address buffer

48: column decoder

45: data input / output buffer

101: data input / output buffer

102: error correction code generation circuit

104: adjacent memory cell disturbance reduced second code conversion circuit

105: adjacent memory cell disturb reduction second code inverse conversion circuit

106: code occurrence probability averaging first coding circuit

107: first code decoding circuit

110: averaging bit mask generation circuit

112: control circuit

Claims (14)

A memory cell which stores at least "1" and "0" binary digital data as the charge of the charge storage layer and uses the difference between the two charge amounts of the charge storage layer as write bits and erase bits; A nonvolatile memory cell array for collectively erasing pages having adjacent cells; An error correction code generation circuit for generating a code for correcting at least one bit of error data from the information bits, and for generating an error correction code for writing in the page; An error correction code decoding circuit for correcting an error from the error correction code and restoring the information bit from the digital data recorded in the page; A code conversion circuit which takes an exclusive logical sum of the inputted information bits or the error correction code and a plurality of bits obtained by repeating an array of "write bit-erase bits" a plurality of times, and outputs them to the error correction code generation circuit. Data memory system comprising a. The method of claim 1, And a code inverse conversion circuit that decodes the error correction code by taking an exclusive OR of the output of the error correction code decoding circuit and a plurality of bits in which a plurality of arrays of "write bit-erase bits" are repeated. The method of claim 1, A continuous bit array of write bits / erase bits / write bits after separating a series of information bits input or the error correction code input into even and odd bits, and rearranging them by collecting them. And a first counter circuit for detecting the number of digits. A memory cell which stores at least "1" and "0" binary digital data as the charge of the charge storage layer and uses the difference between the two charge amounts of the charge storage layer as write bits and erase bits; A nonvolatile memory cell array for collectively erasing pages having adjacent cells; An error correction code generation circuit for generating a code for correcting at least one bit of error data from the information bits, and for generating an error correction code for writing in the page; An error correction code decoding circuit for correcting an error from the error correction code and restoring the information bit from the digital data recorded in the page; A first counter circuit for detecting the number of consecutive bit arrays of write bits / erase bits / write bits of the inputted information bits or the error correction code; The number of consecutive bit arrays of write bits / erase bits / write bits is detected by taking an exclusive OR of a plurality of bits obtained by repeating the inputted information bits or the error correction code and the array of " write bit-erase bits " a plurality of times. The second counter circuit When the number of output arrays of the second counter circuit is smaller than the number of arrays of outputs of the first counter circuit, optionally, the input bits of the information bit or the error correction code and the " write bit-erase bits " A code conversion circuit which takes an exclusive OR of a plurality of bits obtained by repeating the array a plurality of times and outputs the result to the error correction code generation circuit. Data memory system comprising a. The method of claim 4, wherein And a code inverse conversion circuit that decodes the error correction code by taking an exclusive OR of the output of the error correction code decoding circuit and a plurality of bits in which a plurality of arrays of "write bit-erase bits" are repeated. The method of claim 4, wherein And an array of information bits of the write bit / erase bit / write bit correspond to the three physically adjacent memory cells. The method of claim 4, wherein Detecting a contiguous bit array of write bits / erase bits / write bits of an information bit of a second physically contiguous page or an error correction code of the second physically contiguous page on the first page to write; A third counter circuit for respectively detecting the number of write bits and the number of erase bits in the state of the bits of the first page adjacent to the position of the erase bits of the array of the information bits of the second page or the error correction code of the second page; , And a fourth circuit for selectively inverting the inputted information bit or the inputted error correction code and outputting the inputted data to the code conversion circuit by the number of arrangements of the outputs of the third counter circuit. . The method of claim 7, wherein Detecting a contiguous bit array of write bits / erase bits / write bits of an information bit of a second physically contiguous page or an error correction code of the second physically contiguous page in the first page to write to, and The number of first write bits in the state of the bits of the first page adjacent to the position of the erase bits of the array, the information bits of the page or the error correction code of the second page, and the information bits entered or the inputted A fifth counter circuit each detecting a number of second write bits in an error correcting code bit in a state of at least one bit cyclically shifted adjacent first page bit; Selectively shifting the input information bit or the input error correction code if the number of second write bits is less than or less than the number of first write bits in the arrangement of the outputs of the fifth counter circuit. And a sixth circuit output to the code conversion circuit. A memory cell which stores at least "1" and "0" binary digital data as the charge of the charge storage layer and uses the difference between the two charge amounts of the charge storage layer as write bits and erase bits; A nonvolatile memory cell array for collectively erasing pages in which cells are formed adjacent to each other; An error correction code generation circuit for generating a correction code for correcting at least one bit of error data from the information bits; An error correction code decoding circuit for correcting an error from the correction code to restore the information bits; An exclusive logical sum of an error correction code obtained by adding the correction code input from the error correction code generation circuit to the input information bit, and a plurality of bits obtained by repeating an array of " write bit-erase bits " A code conversion circuit for generating data to be written to A code inverse transform circuit that decodes the error correction code by taking an exclusive logical sum of the output of the error correction code decoding circuit and a plurality of bits obtained by repeating an array of "write bit-erase bits" a plurality of times. Data memory system comprising a. 10. The method of claim 9, A continuous bit array of write bits / erase bits / write bits after separating a series of information bits input or the error correction code input into even and odd bits, and rearranging them by collecting them. And a first counter circuit for detecting the number of digits. A memory cell which stores at least "1" and "0" binary digital data as the charge of the charge storage layer and uses the difference between the two charge amounts of the charge storage layer as write bits and erase bits; A nonvolatile memory cell array for collectively erasing pages in which cells are formed adjacent to each other; An error correction code generation circuit for generating a correction code for correcting at least one bit of error data from the information bits; An error correction code decoding circuit for correcting an error from the correction code to restore the information bits; An exclusive logical sum of an error correction code obtained by adding the correction code input from the error correction code generation circuit to the input information bit, and a plurality of bits obtained by repeating an array of " write bit-erase bits " A code conversion circuit for generating data to be written to A code inverse conversion circuit which inputs the digital data recorded in the page, takes an exclusive OR of a plurality of bits obtained by repeating an array of "write bit-erase bits" a plurality of times, and decodes the error correction code. Including, The code conversion circuit, A first counter circuit for detecting the number of consecutive bit arrays of the write bit / erase bit / write bit of the error correcting code input; A second counter circuit which takes an exclusive logical sum of a plurality of bits obtained by repeating the inputted error correction code and the array of " write bit-erase bits " a plurality of times, and detects the number of consecutive bit arrays of write bits / erase bits / write bits. Including; When the number of the arrangements of the outputs of the second counter circuit is smaller than the number of the arrangements of the outputs of the first counter circuit, a plurality of times of repeatedly repeating the input of the error correction code and the " write bit-erase bits " A data memory system that takes an exclusive OR of bits and writes to the page. The method of claim 11, And an array of information bits of the write bit / erase bit / write bit correspond to the three physically adjacent memory cells. The method of claim 11, Detecting a contiguous bit array of write bits / erase bits / write bits of an information bit of a second physically contiguous page or an error correction code of the second physically contiguous page in the first page to write to, and A third counter circuit for detecting the number of write bits and the number of erase bits in the state of the bits of the first page adjacent to the position of the erase bits of the array, either the information bits of the page or the error correction code of the second page; Wow, When the number of write bits of the output of the third counter circuit is less than or less than the number of erase bits, optionally, the inputted information bit or the input error correction code is inverted and outputted to the code conversion circuit. And a fourth circuit. The method of claim 13, Detecting a contiguous bit array of write bits / erase bits / write bits of an information bit of a second physically contiguous page or an error correction code of the second physically contiguous page in the first page to write to, and The number of first write bits in the state of the bits of the first page adjacent to the position of the erase bits of the array, the information bits of the page or the error correction code of the second page, and the information bits entered or the errors entered A fifth counter circuit for respectively detecting the number of second write bits in the state of the bits of the adjacent first page shifted by at least one bit in a corrected code bit; By the number of the arrangement of the outputs of the fifth counter circuit, when the number of the second write bits is less than or less than the number of the first write bits, the input information bits or the input error correction code are shifted in a circular manner, And a sixth circuit output to the code conversion circuit.

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