JP4686520B2 - Data storage system - Google Patents

Description

  The present invention relates to a data storage system and a setting method thereof, and more particularly to a data storage system including a semiconductor memory having an error detection / correction unit.

  As one type of semiconductor memory, a nonvolatile semiconductor memory that stores information according to the amount of charge in the charge storage layer, measures a change in conductance of the MOSFET according to the amount of charge, and reads the information has been developed. This is a so-called EEPROM.

The EEPROM data reading method is a so-called non-destructive reading method that does not cause data destruction, unlike, for example, a DRAM. That is, the EEPROM can read data multiple times without destroying the data. However, if the write and erase operations are repeated,
(1) In the EEPROM cell, for example, the tunnel insulating film is deteriorated, the leakage current is increased, and the charge retention characteristic is deteriorated.
(2) The charge is trapped in the tunnel insulating film, and the threshold value of the EEPROM cell deviates from the preset range.
The data will be destroyed. This is so-called bit destruction. As the storage capacity of the EEPROM increases, the probability that the EEPROM includes bits that have undergone bit destruction (failure bit occurrence rate) increases. Even if the number of times of writing and erasing is constant.

An example of countermeasures against bit destruction is described in Patent Document 1, for example. Patent Document 1 uses a plurality of error detection / correction units (hereinafter referred to as error correction code circuits; referred to as ECC circuits) when there is no need to read data from an external I / O, such as when power is turned on or off. When the memory cluster consisting of the pages is read and a defective bit is detected and an error exceeding the error reference value is detected, all data of the memory cluster subject to ECC is read and written to another storage area. . Thereby, the defective bit generation rate seen from the external interface can be reduced.
Japanese Patent No. 3176019

  An object of the present invention is to provide a data storage system and a setting method thereof that can further reduce the rate of occurrence of defective bits as viewed from an external interface.

The data storage system according to the first aspect of the present invention has a plurality of memory cell blocks, a non-spare area including pages connected to some of these memory cell blocks, and data in a certain value in advance. A spare area including a plurality of spare memory cell blocks, including a page connected to some of the spare memory cell blocks, and a plurality of memory cell blocks connected to some of the memory cell blocks. When data is read from the page in the non-spare area and the file allocation table area for storing the block address of the non-spare area, at least 2-bit data error is detected and A determination circuit for determining the number of error bits for each read page. If the read is more than 2 bits, the content of the read page is error-corrected and written to the page in the spare area, and the block address of the spare area is set so that the write state bit includes more than the erase state bit If the logical value of the write state is defined as “1” and the logical value of the erase state is defined as “0”, the logical inversion of the block address of the non-spare area and the block address of the spare area are taken. , if the 1-bit to a logical value of results does not include "0", the File Allocatio
n The block of the spare area is added to the block address of the non-spare area recorded in the Table area.
The bit of "0" by adding write Kkuadoresu "1" was changed to, characterized in that it does not require erasure.

The data storage system according to the second aspect of the present invention has a plurality of memory cell blocks, a non-spare area including pages connected to some of these memory cell blocks, and data in a certain value in advance. A spare area including a plurality of spare memory cell blocks, including a page connected to some of the spare memory cell blocks, and a plurality of memory cell blocks connected to some of the memory cell blocks. When data is read from the page in the non-spare area and the file allocation table area for storing the block address of the non-spare area, at least 2-bit data error is detected and A determination circuit for determining the number of error bits for each read page. If the read is more than 2 bits, the content of the read page is error-corrected and written to the page in the spare area, and the block address of the spare area is set so that the write state bit includes more than the erase state bit If the logical value of the write state is defined as “1” and the logical value of the erase state is defined as “0”, the logical inversion of the block address of the non-spare area and the block address of the spare area are taken. , if the 1-bit to a logical value of results does not include "0", the File Allocatio
n The block of the spare area is added to the block address of the non-spare area recorded in the Table area.
In this data storage system, the bit of “ 0” is changed to “1” by additionally writing the data address, and no erasure is required.
The maximum number of bits that can be corrected in the page is t, and m is {2 ^m−1 −t × (m−1) −1.
} <N ≦ (2 ^m −t × m−1), where the number of memory cells in one page is (n + t × m) or more.

The data storage system according to the third aspect of the present invention has a plurality of memory cell blocks, and a non-spare area including pages connected to some of these memory cell blocks, and data is pre-arranged to a certain value in advance. A spare area including a plurality of spare memory cell blocks, including a page connected to some of the spare memory cell blocks, and a plurality of memory cell blocks connected to some of the memory cell blocks. When data is read from the page in the non-spare area and the file allocation table area for storing the block address of the non-spare area, at least 2-bit data error is detected and A determination circuit for determining the number of error bits for each read page. If the read is more than 2 bits, the content of the read page is error-corrected and written to the page in the spare area, and the block address of the spare area is set so that the write state bit includes more than the erase state bit If the logical value of the write state is defined as “1” and the logical value of the erase state is defined as “0”, the logical inversion of the block address of the non-spare area and the block address of the spare area are taken. , if the 1-bit to a logical value of results does not include "0", the File Allocatio
n The block of the spare area is added to the block address of the non-spare area recorded in the Table area.
A data storage system in which the bit of “ 0” is changed to “1” by additionally writing a lock address and does not require erasing, and the non-spare area and the spare area are simultaneously erased on a plurality of pages. Is performed.

  ADVANTAGE OF THE INVENTION According to this invention, the data storage system which can further reduce the bad bit generation rate seen from the external interface can be provided.

  Patent Document 1 does not specifically describe how to select the error reference value. Here, if the number of bits that can be relieved by the ECC circuit is significantly increased, the defective bit generation rate viewed from the external interface is reduced. However, when the number of bits that can be relieved by the ECC circuit, that is, the number k of errors that can be corrected, is increased, for example, a k-th order error position polynomial (on the Galois field) is used to calculate the position of the bit that caused the failure. It is necessary to find a solution of For this reason, the calculation circuit becomes complicated, and the calculation time and the area of the calculation circuit increase rapidly.

Further, in the case of a BCH (Bose-Chaudhuri-Hocquenghem) code, the code length including the ECC bits is assumed to be “n”, and the ECC bits need to include information on where n bits are error bits. Therefore, when the number of bits that can be relieved by ECC increases by one bit, at least
log ₂ (n) The number of check bits used by the ECC increases by the number of bits rounded up. Therefore, the code length becomes long, and as a result, the chip area increases or the number of data bits that can be used by the user decreases.

  Further, Patent Document 1 discloses a specific configuration of a system, for example, a configuration of a free storage area, and how much storage area is prepared, and suppresses the generation rate of defective bits as viewed from an external interface while suppressing an increase in chip area. There is no disclosure about how it can be done or how effective.

  Furthermore, Patent Document 1 does not disclose how to prepare a free storage area and replace it at a high speed.

  The free storage area is the same area as the data storage area, and the initial capacity including both is guaranteed as a data storage area usable by the user. For this reason, when a defect exceeding the number of bits that can be relieved by the ECC circuit occurs, the data storage area that can be used by the user is substantially reduced, and it is difficult to guarantee how much it is reduced.

  In general, the nonvolatile semiconductor memory device disclosed in the embodiment of the present invention analyzes an error correcting code (ECC) and replaces a page in which a defective bit of a specified number greater than 1 bit is generated with a spare page. In this way, even when the number of defective bits exceeds the specified number without increasing the number of inspection bits of the ECC circuit, the defective bit generation rate viewed from the external interface is reduced. Furthermore, the processing time required to replace the spare page is reduced.

  In particular, a certain number or more of spare areas are prepared in advance as spare areas. This guarantees the data storage area that can be used by the user to the end of the life, while creating criticality that can control the rate of defective bits seen from the external interface, and data including semiconductor memory that enables high-speed replacement. A storage system is realized.

  Several embodiments of the present invention will be described below with reference to the drawings. In the description, common parts are denoted by common reference symbols throughout the drawings.

(First embodiment)
FIG. 1 is a block diagram showing a configuration example of a data storage system according to the first embodiment of the present invention. FIG. 2 shows a configuration example of a cell array unit and a sense amplifier unit of the data storage system according to the first embodiment of the present invention. FIG. In FIG. 1, the data selection lines (WL) and the block selection lines (SSL, GSL) are omitted.

  Note that in this specification, a memory cell block indicates a unit of a memory cell including a single page or a plurality of pages and simultaneously performing an erase operation. Here, for example, when the erase time of one page of memory cells is longer than the write time of one page of memory cells, such as a flash memory cell having a charge storage layer, the memory cell block includes a plurality of pages. In addition, an erasing operation may be performed on a plurality of pages at once. With this configuration, the writing time per block and the erasing time per block can be made comparable, and the performance of the writing data transfer rate and the erasing rate seen from the system can be improved. A specific configuration example of the memory cell block 49 will be described below.

  FIG. 3 is an equivalent circuit diagram showing an example of an equivalent circuit of the NAND cell block 49, and FIG. 4 is a plan view showing an example of a plane pattern of the NAND cell block 49. FIG. 4 shows a structure in which three cell blocks 49 shown in FIG. 3 are arranged in parallel. Further, in FIG. 4, only the structure below the control gate electrode 27 is shown for easy understanding of the cell structure.

As shown in FIG. 3, nonvolatile memory cells M0 to M15 made of MOS transistors each having a charge storage layer 26 are connected in series, and one end thereof is connected to a data transfer line denoted by “BL” via a selection transistor S1. The other end is connected to a common source line labeled “SL” via a selection transistor S2. The memory cells M0 to M15 and the select transistors S1 and S2 are each formed on the same p-type well 23. The control electrodes of the memory cells M0 to M15 are connected to the data selection lines indicated as “WL0 to WL15”. In order to select one memory cell block 49 from the plurality of memory cell blocks 49 along the data transfer line BL and connect the selected memory cell block to the data transfer line BL, the control electrode of the selection transistor S1 is the block selection line SSL. The control electrode of the selection transistor S2 is connected to the block selection line GSL. As a result, a so-called NAND type memory cell block 49 (dotted line region) is formed. In the first embodiment, the control wirings (block selection lines) SSL and GSL of the selection transistors S1 and S2 are formed in the vertical direction in FIG. 3 by the conductor in the same layer as the charge storage layer 26 of the memory cells M0 to M15. Is formed while connecting the gates of the select transistors S1 and S2 adjacent to each other. There may be at least one block selection line SSL, GSL in the memory cell block 49. The block selection lines SSL and GSL are preferably formed in the same direction as the data selection lines WL0 to WL15, but are not limited thereto. This is because the density can be increased. FIG. 3 shows an example in which 16 = 2 ⁴ memory cells are connected to the memory cell block 49, but the number of memory cells connected to the data transfer line and the data selection line may be plural, Although it is not necessarily limited to 2 ⁿ (n is a positive integer), it is desirable. This is because address decoding becomes easy.

  5 is a cross-sectional view taken along line VV in FIG. 4, and FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. The cross section shown in FIG. 5 corresponds to a cross section showing a structural example of the memory cell, and the cross section shown in FIG. 6 corresponds to a cross section showing a structural example of the memory cell block.

As shown in FIGS. 5 and 6, the p-type silicon region 23 includes, for example, boron having an impurity concentration of about 10 ¹⁴ cm ⁻³ to 10 ¹⁹ cm ⁻³ . On the p-type silicon region 23, tunnel insulating films 25, 25 _SSL and 25 _GSL are formed. An example of the tunnel insulating film 25 is a silicon oxide film or a silicon oxynitride film having a thickness of about 3 nm to 15 nm, for example. On the tunnel insulating films 25, 25 _SSL , 25 _GSL , charge storage layers 26, 26 _SSL , 26 _GSL are formed. An example of the charge storage layers 26, 26 _SSL , 26 _GSL is polysilicon having a thickness of about 10 nm to 500 nm including, for example, about 10 ¹⁸ cm ⁻³ to 10 ²¹ cm ^{−3 of} phosphorus or arsenic. The tunnel insulating film 25 (25, 25 _SSL , 25 _GSL ) and the charge storage layer 26 (26, 26 _SSL , 26 _GSL ) are formed on a region where the element isolation insulating film 24 made of, for example, a silicon oxide film is not formed. The p-type silicon region 23 is formed in a self-aligned manner. In this structure, for example, the tunnel insulating film 25 and the charge storage layer 26 are deposited, the deposited tunnel insulating film 25 and the charge storage layer 26 are patterned, and etching is further advanced into the p-type silicon region 23, so that the p-type silicon region is formed. A shallow trench having a depth of, for example, about 0.05 μm to 0.5 μm is formed in 23. Next, the shallow trench can be formed by filling with an insulator (element isolation insulating film 24). The advantage of this structure is that, for example, the tunnel insulating film 25 and the charge storage layer 26 can be formed on a flat surface without a step, that is, on the p-type silicon region 23 in which no shallow trench is formed. A film having good uniformity and uniform characteristics can be obtained with respect to the layer 26.

Block insulating films 50, 50 _SSL , 50 _GSL are formed on the charge storage layers 26, 26 _SSL , 26 _GSL . Examples of the block insulating films 50, 50 _SSL , and 50 _GSL are, for example, three layers of silicon oxide film, oxynitride film, or silicon oxide film / silicon nitride film / silicon oxide film having a thickness of about 5 nm to 30 nm. It is a membrane. A control gate 27 is formed on the block insulating films (intergate insulating films) 50, 50 _SSL , 50 _GSL . An example of the control gate 27 is, for example, polysilicon having a thickness of about 10 nm to 500 nm and containing phosphorus, arsenic, or boron of about 10 ¹⁷ cm ⁻³ to 10 ²¹ cm ⁻³ , or a metal silicide and polysilicon. Stack structure. Examples of the metal silicide are, for example, WSi (tungsten silicide), NiSi (nickel silicide), MoSi (molybdenum silicide), TiSi (titanium silicide), and CoSi (cobalt silicide). The control gate 27 constitutes data selection lines WL0 to WL15, for example, as shown in FIG. The data selection lines WL0 to WL15 connect adjacent memory cell blocks 49 and are formed from one end to the other end of the memory cell array 1 along the row direction. For example, the p-type silicon region 23 is separated from the p-type silicon substrate 21 by the n-type silicon region 22. Thereby, the p-type silicon region 23 can apply a voltage independently from the p-type silicon substrate 21. If the p-type silicon region 23 is formed so that a voltage can be applied independently of the p-type silicon substrate 21, it is possible to reduce the booster circuit load at the time of erasing and to obtain the advantage of suppressing power consumption.

  Further, in the memory cell shown in FIG. 5, the side wall (side wall of the shallow groove) of the p-type silicon region 23 is not exposed to the outside in the etching process when the charge storage layer 26 is separated for each memory cell. This is because the side walls of the charge storage layer 26 and the side walls of the p-type silicon region 23 and the like are covered with the element isolation insulating film 24. According to this gate structure, it is possible to suppress the charge storage layer 26 from being formed even below the p-type silicon region 23. An advantage of this is that, for example, at the boundary between the p-type silicon region 23 and the element isolation insulating film 24, the concentration of the gate electric field can be suppressed and the occurrence of a parasitic transistor having a low threshold can be suppressed. Furthermore, for example, the gate electric field concentration can be suppressed at the boundary between the p-type silicon region 23 and the element isolation insulating film 24, and a phenomenon of lowering the write threshold value due to the gate electric field concentration, a so-called sidewalk phenomenon occurs. It can be difficult. Due to these advantages, the memory cell shown in FIG. 5 has high reliability.

As shown in FIG. 6, tunnel insulating film 25 (25, 25 _SSL , 25 _GSL ), charge storage layer 26 (26, 26 _SSL , 26 _GSL ), block insulating film 50 (50, 50 _SSL , 50 _GSL ), control Side wall insulating films 43 are respectively formed on both side walls of the stacked gate structure including the gate 27. An example of the sidewall insulating film 43 is, for example, a silicon nitride film or a silicon oxide film having a thickness of 5 nm to 200 nm. An n-type diffusion layer 28 is formed in a portion of the p-type silicon region 23 located between the stacked gate structures. The n-type diffusion layer 28 is a source electrode or a drain electrode of a memory cell or a select transistor. The memory cell includes an n-type diffusion layer 28, a tunnel insulating film 25, a charge storage layer 26, a block insulating film 50, and a control gate 27. This is a so-called floating gate type EEPROM cell, and its gate length is, for example, 0.5 μm or less and 0.01 or more. The n-type diffusion layer 28 includes, for example, phosphorus, arsenic, and antimony in a surface concentration range of 10 ¹⁷ cm ⁻³ to 10 ²¹ cm ⁻³ and is formed to a depth of about 10 nm to 500 nm. Further, the n-type diffusion layer 28 is shared by adjacent memory cells, and so-called NAND connection is realized.

“26 _SSL ” and “26 _GSL ” shown in FIG. 6 are gate electrodes connected to a block selection line corresponding to “SSL” and a block selection line corresponding to “ _GSL ”, respectively. It is formed using the same conductor layer as the floating gate (charge storage layer 26). In this specification, for convenience, “26 _SSL ” and “26 _GSL ” are referred to as charge storage layers, but actually “26 _SSL ” and “26 _GSL ” are not charge storage layers but gate electrodes. . Hereinafter, it will be read as the gate electrodes 26 _SSL and 26 _GSL . The gate lengths of the gate electrodes 26 _SSL and 26 _GSL , that is, the gate length of the selection transistor is longer than the gate length of the memory cell. For example, it is 1 μm or less and 0.02 μm or more. By making the gate length of the selection transistor longer than the gate length of the memory cell, a large on / off ratio between when the block is selected and when the block is not selected can be secured. The ability to increase the on / off ratio is advantageous in preventing erroneous writing and erroneous reading.

The n-type diffusion layer 28 _d formed on the opposite side of the n-type diffusion layer 28 across the gate electrode 26 _SSL is connected to the data transfer line 36 (BL through the contact 31 _d , the intermediate wiring 33 _d , and the contact 34 _d. )It is connected to the. The n-type diffusion layer 28 _d is a source electrode or a drain electrode similarly to the n-type diffusion layer 28. The material example of the data transfer line 36 (BL) is, for example, tungsten, tungsten silicide, titanium, titanium nitride, or aluminum. The material of the intermediate wiring 33d may be the same as that of the data transfer line 36 (BL), for example. The data transfer line 36 (BL) is formed, for example, to the boundary of the memory cell array in the left-right direction in FIG. 4 so as to connect the memory cell blocks adjacent in the column direction. The n-type diffusion layer 28 _s formed on the opposite side of the n-type diffusion layer 28 across the gate electrode 26 _GSL is connected to the source line 33 (SL) via a contact 31 _s . The n-type diffusion layer 28 _s is a source electrode or a drain electrode similarly to the n-type diffusion layer 28. The source line 33 _s is formed of, for example, the same conductor layer as the intermediate wiring 33 _d . The source line 33 _s is formed, for example, up to the boundary of the memory cell array in the vertical direction in FIG. 4 so as to connect the memory cell blocks adjacent in the row direction. In this example, an example having the source line 33 (SL) is shown. However, the n-type diffusion layer 28 _s may be formed in the vertical direction in FIG. 4 to the boundary of the memory cell array, for example, as the source line. . The contacts 31 _d and 31 _s are conductive regions, and are formed of a conductive material filled in the openings 30 _d and 30 _s formed in the interlayer insulating film 68, for example. Examples of the material of the conductive material are polysilicon doped with n-type or p-type, tungsten, tungsten silicide, aluminum, titanium nitride, and titanium. Contact 34d is also similar to the contact 31 _d, 31 _s. The interlayer insulating film 68 is an insulating film that insulates the source line 33 (SL), the data transfer line 36 (BL), the selection transistor, and the memory cell. Examples of the material of the interlayer insulating film 68 are, for example, silicon dioxide and silicon nitride. In the upper layer of the interlayer insulating film 68 and the data transfer line 36 (BL), an upper wiring (not shown) existing above the data transfer line 36 (BL) and an insulating film protective layer 37 are formed. Examples of the material of the upper wiring are tungsten, aluminum, and copper, for example. Examples of the material of the insulating film protective layer 37 are, for example, silicon dioxide, silicon nitride, and polyimide.

  As shown in FIGS. 1 and 2, a memory cell block 49 is arranged in the memory cell array 1. Memory cell block 49 includes nonvolatile memory cells connected in series. Or, as will be described later, it includes nonvolatile memory cells connected in parallel.

  The sense amplifier circuits 46a,..., 46k sense-amplify read data read to the data transfer lines BL1a, BL2a,..., BL1k, BL2k at the time of data reading. The sense amplifier circuits 46a,..., 46k also serve as data registers, and hold write data when data is written. For this reason, the sense amplifier circuits 46a,..., 46k are composed of, for example, a circuit mainly including a flip-flop circuit.

  The sense amplifier circuit 46a is connected to the data transfer lines BL1a and BL2a via data transfer line selection transistors Q1a and Q2a, respectively. Similarly, the sense amplifier circuit 46k is connected to the data transfer lines BL1k and BL2k via the data transfer line selection transistors Q1k and Q2k, respectively.

  The sense amplifier circuits 46 a to 46 k are connected to the data input / output buffer 45. The connection between the sense amplifier circuits 46a to 46k and the data input / output buffer 45 is controlled by the output of the column decoder 48, for example.

  The column decoder 48 receives an address signal from the address buffer 47 and outputs a decoding result obtained by decoding the address signal. As a result, the write data given to the data input / output buffer 45 can be written to the memory cell array 1, and the read data read from the memory cell array 1 is stored in the data input / output buffer 45 in the third state shown in FIG. Can be read out via the internal I / O line.

  The row decoder 3 selects a memory cell in the memory cell array 1. Specifically, the row decoder 3 controls the data selection lines WL0 to WL15 and the block selection gates SSL and GSL to select a memory cell in the memory cell array 1. The row decoder 3 is divided into a row decoder 3s in the spare area and a row decoder 3n in the non-spare area. The block address designated by the row decoder 3s in the spare area is not limited, but may be formed so that the number including the “0” bit for erasure is reduced (for example, see FIG. 12). The reason for this will be described later.

  The memory cell array 1 of the present embodiment includes a non-spare area 1n and a spare area 1s. Each of the non-spare area 1n and the spare area 1s includes a plurality of memory cell blocks 49. In the non-spare area 1n, the plurality of memory cell blocks 49 are arranged in a matrix. Similarly, in the spare area 1s (however, FIG. 2 shows only rows in the matrix), a plurality of memory cell blocks 49 are arranged in a matrix. In the non-spare area 1n and the spare area 1s, the memory cell blocks 49 arranged in the row direction are commonly connected to the data selection line WL to form a so-called page.

  The spare area 1s is a memory cell that copies and replaces the data of the memory cell block 49 in the non-spare area 1n that needs to be replaced when the memory cell block 49 in the non-spare area 1n needs to be replaced. Block 49 is included. For example, the total number of memory cell blocks 49 in the spare area 1s is formed to be smaller than the total number of memory cell blocks 49 in the non-spare area 1n. Here, in a memory in which data of a block including a plurality of pages is flash erased (all erased) and data is written only when there is data to be written, the data in the spare area 1s is set in an erased state in advance and needs to be replaced. In this case, the spare area 1s is used. In this way, by setting the data in the spare area 1s in the erased state in advance, the time for erasing the data from the spare area 1s can be shortened when it is necessary to replace the data.

  The substrate potential control circuit 42 controls the potential of the p-type silicon region 23 (or the p-type silicon substrate 21) where the memory cell array 1 is formed. The substrate potential control circuit 42 is not limited, but it is desirable that an erase voltage of, for example, 10 V or more can be generated at the time of erasing.

  For example, the Vpgm generation circuit 41a generates a write voltage Vpgm obtained by boosting the power supply voltage. The write voltage Vpgm is used for the selected memory cell when writing data. The write voltage Vpgm is applied to, for example, the control gate (data selection line WL) of the selected memory cell. A voltage example of the write voltage Vpgm is 6 V or more and 30 V or less.

  The Vpass generation circuit 41b generates a write intermediate voltage Vpass. The write intermediate voltage Vpass is used for non-selected memory cells when writing data. The write intermediate voltage Vpass is applied to, for example, a control gate (data selection line WL) of a non-selected memory cell at the time of data writing. A voltage example of the write intermediate voltage Vpass is 3 V or more and 15 V or less.

  The Vread generation circuit 41c generates a read intermediate voltage Vread. The read intermediate voltage Vread is used for non-selected memory cells when reading data. The read intermediate voltage Vread is applied to, for example, a control gate (data selection line WL) of a non-selected memory cell at the time of data reading. A voltage example of the read intermediate voltage Vread is 1 V or more and 9 V or less. When the memory cell array 1 is a NAND type memory cell array, it is not limited, but the voltage may be higher by, for example, about 1V than the upper limit of the write threshold voltage of the memory cell. This is from the viewpoint of satisfying both of ensuring a sufficient read current and suppressing read-disturb.

Vref generation circuit 41d generates threshold determination voltage Vref. The threshold determination voltage Vref is used for a selected memory cell when reading data. The threshold determination voltage Vref is applied to, for example, a control gate (data selection line WL) of the selected memory cell at the time of data reading. An example of the threshold determination voltage Vref is an intermediate voltage between threshold voltage distributions of logically separated and logically adjacent memory cells. For example, in the case of a binary memory, the voltage is set between a threshold voltage distribution corresponding to data “1” and a threshold voltage distribution corresponding to data “0”. In the case of a multi-value memory, in which multi-value data determination is performed using the threshold determination voltage Vref, a plurality of threshold determination voltages Vref are set. For example, in the case of a quaternary memory, for example, three threshold determination voltages Vref1 to Vref3 are respectively
A voltage between a threshold voltage distribution corresponding to data “11” and a threshold voltage distribution corresponding to data “10”;
The voltage between the threshold voltage distribution corresponding to the data “10” and the threshold voltage distribution corresponding to the data “00” and the threshold voltage distribution corresponding to the data “00” and the data “01” Is set to each of the voltages between the threshold voltage distributions corresponding to "".

  The voltage generation circuits 41a, 41b, 41c, 41d, and 42 that generate these voltages are controlled by the control circuit 40, respectively. As a result, the generation circuits 41a, 41b, 41c, 41d, and 42 generate necessary voltage outputs in the “data write”, “data read”, and “data erase” states, respectively, Alternatively, it is applied to the p-type silicon region 23 (or the p-type silicon substrate 21).

  In accordance with the output of the row decoder 3, the data line control driver 2 controls the voltage output of the voltage generation circuits 41a, 41b, 41c, 41d, and the control gates (data selection lines WL0 to WL15) of the memory cells that need to be written or read. And a switch circuit applied to the control gates (block selection lines SSL, GSL) of the selected selection transistor.

In all the embodiments of the present specification, the number of data bits read in a series of sequences is such that the number of data bits “n” read in a series of sequences where “t” is a natural number larger than “1” is {2 ^m− If it is larger than ¹⁻ t × (m−1) −1} and equal to or smaller than (2 ^m −t × m−1), at least (n + t × m) or more memory cell blocks 49 are arranged as shown in FIG. They are prepared in parallel along the left and right, that is, the direction (row direction) in which the data selection line WL extends. This is one page.

  In the example shown in FIG. 2, at least (n + t × m) or more sense amplifier circuits 46 may be prepared as in the number of parallel connections for one page of the memory cell block 49. By preparing the sense amplifier circuit 46 and the memory cell in this way, for example, two bits or more of one page read in a series of sequences of the memory cell array 1 using a BCH (Bose-Chaudhuri-Hocquenghem) code. Bit errors below bits can be detected and their positions can be obtained. For example, when a plurality of memory cells belonging to one page are commonly connected to one data selection line WL, a plurality of memory cells can be simultaneously selected by one data selection.

  Further, the input / output of the sense amplifier circuit 46 is connected to a control circuit 40 that controls reading, writing, and erasing of memory cells. The control circuit 40 uses, for example, data supplied to the data buffer as a command input, and controls reading, writing, and erasing of the memory cell.

  Although not shown in FIG. 1 for simplification, the sense amplifier circuit 46 includes a control signal for controlling the operation of the sense amplifier circuit 46 from the control circuit 40, an odd number data transfer line (BL1), or an even number. A control signal (sel1, sel2 in FIG. 2) for selecting the data transfer line (BL2) is input. In FIG. 1, a portion surrounded by a broken line frame 7 indicates a storage device typically formed on one semiconductor substrate as, for example, a NAND flash memory. For the broken line frame 7, for example, a circuit block described in Japanese Patent Application Laid-Open No. 2002-150783 may be used. Therefore, the detailed description is abbreviate | omitted.

  Next, the ECC circuit 100 will be described. In the following description, according to the convention, the data string before encoding is an information bit, the bit added at the time of encoding is a check bit, the decoded data string is a bit string indicating an error position following the information bit, A code that may contain an error obtained by reading from the storage device is called a received code.

  The data input / output buffer 45 is connected to the ECC circuit 100 via an internal I / O line. The ECC circuit 100 includes an error bit detection circuit 5 and an error bit number determination circuit 6. The error bit detection circuit 5 may output an error detection signal including error information to the error bit number determination circuit 6. Further, the error detection signal may be substituted by a syndrome output from the error bit detection circuit 5 through the first I / O line. The error bit number determination circuit 6 exchanges data between the data storage system according to the embodiment and the outside via an external input / output terminal (external I / O). The error bit number determination circuit 6 determines that the number of error bits is equal to or greater than a predetermined reference value exceeding 1. The reference value may be equal to the number of bits that can be relieved by ECC. If the reference value is made equal to the number of bits that can be relieved by ECC, the number of blocks to be replaced without generating error bits after relieving by ECC can be reduced and the number of necessary spare blocks can be reduced. If the number of error bits exceeds a predetermined reference value exceeding 1, a signal notifying the outside that this condition has occurred is output via the external I / O, and the block in which the error bits are generated The data may be copied by an external circuit connected to the external I / O and replaced with a spare block.

  FIG. 7 is a block diagram illustrating a configuration example of the ECC circuit 100.

As shown in FIG. 7, the error bit number determination circuit 6 includes a CPU 108, a page buffer 11, a ROM 111 that stores an error bit number reference value, and I / O ports 106 and 107. The ECC circuit 100 may include a page counter 10 made of, for example, a flip-flop or a volatile memory. The page counter 10 is provided in the CPU 108, for example. The page counter 10 stores an index of the number of pages in a block to which block contents are transferred. The page counter 10 may be a counter having a number of bits equal to or greater than log ₂ (i), where the number of pages is “i”. Further, the page counter 10 has a reset function that sets at least all the bits of the counter to a constant initial value and a function that increases the number of pages so that all pages in one block are accessed once. In the following description, it is assumed that the page counter 10 has a reset function that uses the index of the first page as an initial value and a function that increases the page by “1” as the simplest functional example.

  The error bit number determination circuit 6 may further include a page buffer 11 made of a volatile memory such as SRAM or DRAM. If the page buffer 11 is included, data correction and writing of correction data to the spare area can be performed in the data storage system shown in FIG. 1, data is output to the external I / O line, and data is exchanged with an external device (for example, external memory). There is an advantage that the operation can be speeded up. Of course, if the page buffer 11 is outside the data storage system of FIG. 1 and can be stored and read by the external I / O, the replacement operation to the spare block shown in this example can be realized. The number of bits required for the page buffer 11 may be equal to or greater than the number of bits equal to the number of sign bits.

  The error bit detection circuit 5 is a circuit that outputs a syndrome. The syndrome includes a bit error of a series of data output from the data input / output buffer 45. As in this example, when error correction of 2 bits or more is required, it is necessary to perform multiplication / division on the Galois field to obtain the defective bit position from the syndrome. In this example, it is assumed that the error bit number determination circuit 6 specifies the defective bit position and outputs the position information to the error detection signal line or the first internal I / O line. As the error bit detection circuit 5, in this example, a code capable of correcting an error of 2 bits or more is used. For this purpose, the error bit detection circuit 5 may be used, for example, a cyclic code decoder. The reason why the code can correct errors of 2 bits or more will be described in detail later. The code capable of correcting errors of 2 bits or more is effective in suppressing the increase in the area of spare pages that replace pages including defective bits at a sufficiently small ratio of, for example, 5% or less with respect to the number of non-spare pages. It is also useful for obtaining. Further, in a code for correcting a 1-bit error, even if there is an error bit that can be corrected, the error bit that can be corrected is naturally 1 bit. Needless to say, it is not included in the constituent elements of the error bit number determination circuit 6 having a reference value larger than 1 as in this example.

8 is a circuit diagram showing a circuit example of the encoder 14 provided in the error bit detection circuit 5, and FIGS. 9 and 10 are decoders (syndrome calculators) 15 provided in the error bit detection circuit 5, respectively. It is a circuit diagram which shows the example of. The encoder 14 shown in FIG. 8 is a specific example of a data cyclic BCH code encoder. 9 and 10 are specific examples of the data cyclic BCH code decoder. These data cyclic BCH code encoders / decoders, for example, form a 15-bit code that can be 2-bit error corrected with 7 data bits. The following description shows an example in which, when a 2-bit error occurs, the contents of the page where the error occurred are copied to a spare block and block replacement is performed. Further, in the following description, a cyclic BCH code using an element on a Galois field GF (2 ⁴ ) is shown for simplicity of explanation, but of course, a cyclic BCH code or a Reed-Solomon code on an arbitrary Galois field It is obvious that the circuit can be similarly configured and used. Further, in the conventional case, the logical value of the erased state is “1” and the logical value of the written state is “0”. In this example, the logical value of the erased state is “0” and the logical value of the written state is “1”. Define it in reverse. This is because, in this example, the use of a circuit that performs linear error correction is described as an embodiment, so that all the syndromes are logical values “0” corresponds to the “no error” state, and the syndrome This is for the purpose of forming an error-free initial value without writing a code to the syndrome again when one block including all is erased. Of course, the logic value of the memory cell is set as usual, and the logic value is reversed to that of the memory cell in the error bit detection circuit 5 by interposing a logic inversion circuit on the first internal I / O line. May be set.

  As shown in FIG. 8, it is assumed that the information bit input is given 7 bits as a time series for each unit time. The circuit denoted by reference numeral 8 is a circuit that delays by one unit time, and may be constituted by a known flip-flop such as a D-type flip-flop or a latch circuit, for example. In the case of the D-type flip-flop, it is assumed that the logic value is set to “0” before the clock is supplied. The clock may be given to all the plurality of circuits 8 in synchronization. This is because the clock wiring can be simplified. Reference numeral S1 (S1a, S1b) is a switch circuit. The switch circuit S1 is connected to the “S1a” side during information bit input, that is, from 1 to 7 bits, and is in the test bit output after the information bit input is completed, that is, from 8 to 15 bits on the “S1b” side. Connected to. Reference numeral S2 is also a switch circuit. The switch circuit S2 is in a connected state during input of information bits, that is, from 1 to 8 bits, and is in a test bit output after completion of input of information bits, that is, a logical value “0” from 8 to 15 bits. Output in the circle (white circle) direction in 8. By applying such an operation to the clock 15 times until the 15-bit output is completed, it is possible to create a cyclic BCH code that can be corrected by 2 bits.

FIG. 13 shows the element α ⁱ of the Galois field GF (2 ⁴ ) in this example. As is well known, the addition on the Galois field is an exclusive OR of each factor of each vector display shown in FIG. For example,
α ⁰ + α ⁴ = (0001) + (0011) = (0010) = α ¹
It becomes.

Since multiplication and division are “2 ⁴ −1 = 15”, α ⁱ × α ^j = α ^{(i + j) mod 15}
α ⁱ / α ^j = α ^{(ij) mod15}
And calculate.

Inverse element α ^-i of the original α ⁱ is,
α ^-i = α ⁰ / α ⁱ
Can be obtained.

The primitive generator polynomial G _s (x) of a double error correcting binary BCH code having a code length of 15 bits is defined as M _i (x) as a minimum polynomial of α ⁱ ,
G _s (x) = M ₁ (x) × M ₃ (x)
= (X ⁴ + x + 1) × (x ⁴ + x ³ + x ² + x + 1)
^{= X 8 + x 7 + x} 6 + x 4 +1
Given in. The circuit shown in FIG. 8 represents G _s (x) in a circuit form. Therefore, in encoding, the code output is electrically connected to the I / O line 1, and the external I / O is electrically connected to the information bit input through the data input / output control circuit including the error bit number determination circuit 6. Connecting. As a result, a code capable of 2-bit correction can be written in the memory cell.

  Specifically, the external I / O is, for example, an input / output portion connected through a connector or a wireless communication means outside an input / output terminal of a memory card or a package containing the data storage system of this example. Indicates.

A specific example of the data cyclic BCH code decoder shown in FIG. 9 and FIG. 10 is a syndrome calculator for calculating a binary 4 bits from the cyclic BCH code, that is, a syndrome on the Galois field GF (2 ⁴ ). 15 circuit examples.

The syndrome calculator 15 obtains the outputs of the syndromes s1 and s3 indicating the error position information after a delay of 15 unit time from the received code input. The syndromes s1 and s3 are syndromes corresponding to the aforementioned M ₁ (x) and M ₃ (x), respectively. Although details of error correction will be described later, when all of the syndromes s1 and s3 are “0”, it can be determined that there is no error.

In addition to the above, when “s1 ³ + s3” is (0000), it can be determined that a 1-bit error has occurred, and when “s1 ³ + s3” is not (0000), an error of 2 bits or more. Can be determined to have occurred.

“S1 ³ + s3” is a primitive polynomial,
M ₁ (x) = x ⁴ + x + 1
It shall be calculated on the Galois field.

From the above, by calculating “s1 ³ + s3” using the CPU shown in FIG. 7, a circuit that detects an error of 2 bits or more in the memory cell and outputs the position information can be specifically configured. In decoding, the code input is electrically connected to the I / O line 1, and the code and the syndromes s1 and s3 are electrically connected to the error bit number determination circuit 6 as shown in FIG.

The primitive generator polynomial of a single error correction binary BCH code having a code length of 15 bits is
M ₁ (x) = x ⁴ + x + 1
Given in. Therefore, as shown in FIG. 9, the four outputs of the circuit delayed by one unit time are passed through the α multiplier circuit 200 that multiplies the unit element on the Galois field GF (2 ⁴ ) by a plurality of circuits 8. Sequential feedback. Thereby, a syndrome s1 having α as a unit element can be obtained. Similarly, as shown in FIG. 10, three α multiplication circuits 200 are connected in series and then fed back sequentially to a plurality of circuits 8. As a result, a syndrome s3 having α ³ as a unit element can be obtained. Similarly, a syndrome sk having α ^k as a unit element can be obtained by sequentially feeding back k to the plurality of circuits 8 after connecting k α multiplication circuits 200 in series.

  Next, an operation example of the error bit number determination circuit 6 will be described with reference to the flowchart shown in FIG. In the description of this operation example, a case where 2-bit error correction is performed is illustrated.

  In the operation example shown in FIG. 11, the number of error determination bits larger than “1” at the time of reading, in this case, a page in which an error of 2 bits is selectively corrected to an empty spare block, and page data is corrected by ECC. This is an example of replacement. In the present embodiment, a page in which an error having a larger number of bits than 1 bit, which is 2 bits, is selected and selectively replaced.

  First, in SE1, the syndromes s1 and s3 are transferred from the error bit detection circuit 5 to the error bit number determination circuit 6 through the I / O port 106. The received code is transferred from the error bit detection circuit 5 to the page buffer 11 in the error bit number determination circuit 6 through the I / O port 106.

Next, in SE2, it is determined whether or not any of the syndromes s1 and s3 includes at least one “1”. When neither of the syndromes s1 and s3 includes “1”, it is “no error bit” (N: No). In this case, the first 7 bits of the sign bit are output as information bits. Further, when any of the syndromes s1 and s3 includes at least one “1”, “there is an error bit” (Y: Yes). In this case, the process proceeds to SE3 and the CPU 108 determines the determinant of the Peterson method,
sp = s1 ³ + s3
Calculate At this time, the multiplication table and the inverse element table on the Galois field GF (2 ⁴ ) are incorporated in the error bit number determination circuit 6, for example, the ROM 111 (multiplication table ROM and inverse element table ROM). Thereby, multiplication / division calculation can be performed at high speed. Incidentally, in this example, since the syndromes s1 and s3 are 4 bits in the multiplication table ROM, it is sufficient to output 4 bits by inputting “4 bits + 4 bits = 8 bits”. For example, 2 ⁸ × 2 ⁴ = Achievable with a 4096-bit memory element. Similarly, the inverse table ROM may be a 4-bit input and a 4-bit output, and can be realized by, for example, a storage element of 2 ⁴ × 2 ⁴ = 256 bits. As will be described later, when an error correction of 2 bits or more is handled by creating a correspondence table with the syndrome as an address input and the error position locator as an output, the number of bits is much larger than the above (4096 + 256) bits. Correspondence table with is required. On the other hand, even if there is an error of 2 bits or more, a method for obtaining an error position locator by calculation may be a storage element having the above-mentioned number of bits. Thus, the method using the multiplication table ROM and the inverse element table ROM has an advantage that the number of storage elements can be reduced even if the number of error correction bits is greatly increased, and the circuit area can be reduced. Of course, the multiplication table ROM and the inverse element table ROM may be formed not by so-called ROM mapping but by a logic circuit having a syndrome as an address input and an error position locator as an output.

  Next, in SE4, it is determined whether or not the determinant sp includes at least one “1”. When the determinant sp does not include any “1”, the process proceeds to SE5 (N), and in SE5, it is determined whether or not the syndrome s1 includes at least one “1”.

In SE5, when the syndrome s1 includes at least one “1”, the error bit is 1 bit. In this case, the process proceeds to SE6 (Y). In SE6, the inverse element of the syndrome s1 is first calculated using the CPU. When the inverse element of the syndrome s1 is “α ^k ” with reference to the element shown in FIG. 13, it may be considered that “the (k + 1) -th bit is an error as counted from the last input bit of 15 bits”. it can. Therefore, in SE6, the (k + 1) th bit counted from the last input bit may be corrected by bit inversion. Thereafter, the first 7 bits of the correction code bit are output as information bits.

  On the other hand, in SE5, when the syndrome s1 does not include any “1”, a bit error of 3 bits or more has occurred. In this case, the process proceeds to SE14 (N). In SE14, a signal indicating that the ECC cannot be relieved is output to the external I / O, and the process ends.

  In SE4, if the determinant sp includes at least one “1”, the process proceeds to SE7 (Y). In SE7, it is determined whether the syndrome s1 includes at least one “1”.

  In SE7, when the syndrome s1 does not include any “1”, a bit error of 3 bits or more has occurred. Therefore, the process proceeds to SE14 (N), and in SE14, a signal indicating that the ECC cannot be repaired is output to the external I / O, and the process ends.

  On the other hand, if at least one syndrome s1 includes “1” in SE7, a bit defect of 2 bits or more has occurred. In this case, the process proceeds to SE8 (Y).

In SE8, the coefficients σ ₁ and σ ₂ of the error locator polynomial σ (z) are calculated on the Galois field,
σ1 = s1
σ2 = sp / s1
Calculate as

Next, in SE9, an error locator polynomial,
σ (z) = 1 + z × σ ₁ + z ² × σ ₂
Substituting the element of Galois field GF (2 ⁴ ) into “z” of
σ (z) = 0
Find a solution that becomes At this time, as described above, by multiplying the multiplication table ROM on the Galois field GF (2 ⁴ ) in the error bit number determination circuit 6, for example, the ROM 111, the multiplication calculation can be performed at high speed.

Next, in SE10, “i” and “j” are set as “α ⁱ ” and “α ^j ” as {(original number of Galois field) −1} to 0 or more different integers (i ≠ j), respectively. It is determined whether or not the solution “can be obtained.

  If no solution is obtained, it means that a bit error of 3 bits or more has occurred, and the process proceeds to SE14 (N). In SE14, a signal indicating that the ECC cannot be relieved is output to the external I / O, and the process ends.

When the solution is obtained, referring to the element shown in FIG. 13 and assuming that “α ⁱ ” and “α ^j ”, the “(i + 1) th bit counted from the last input bit in 15 bits, and (j + 1)” ) The bit is an error ”. Therefore, in SE11, the (i + 1) -th bit and the (j + 1) -th bit may be corrected by bit inversion, counting from the last input bit.

  Next, in SE12, it is confirmed whether there are still spare blocks that are not used. For example, a block address information storage area for storing an address of a spare block that can be used in advance is prepared in a FAT (File Allocation Table) area. For example, the address of the used spare block is stored in the block address information storage area. In SE12, by checking the address of the spare block stored in the block address information storage area, it can be confirmed whether there is still a spare block that is not used. The block replacement method will be described in detail later. If it is determined in SE12 that “an empty spare block area exists”, the process proceeds to SE13 (Y). In SE13, the page content is error-corrected and transferred to an empty spare block. Subsequent to this operation, the work of replacing the block address of the page described in the FAT area with the address of the free spare block may be performed.

  On the other hand, if it is determined in SE12 that “no spare spare block area is present”, the process proceeds to SE15 (N). In SE15, a signal indicating that there is no empty spare block is output from the external I / O. Subsequent to this operation, the page content may be written back to the original memory block address.

  As described above, the operation example shown in FIG. 11 is a method for obtaining the error bit position by calculation using the Peterson method. According to this method, since the error position locator is obtained by calculation rather than by drawing a correspondence table, the large ROM area 111 necessary for the correspondence table is not required, and can be realized with a circuit having a smaller ROM capacity. Therefore, it is advantageous for reducing the area of the ROM circuit, and the power consumed by the ROM circuit can be kept small.

  Furthermore, in this embodiment, in particular, a device is also devised for the allocation of the block address of the non-spare area and the block address of the spare area.

  FIG. 12 shows an example of assignment of block addresses of non-spare areas and block addresses of spare areas.

In the allocation example shown in FIG. 12, a flag address bit for discriminating between the non-spare area and the spare area is added to the real address of the non-spare area. Further, the flag address bit is set to “0” in the non-spare area, and the flag address bit is set to “1” in the spare area. In the example of allocation shown in FIG. 12, for the block address of the non-spare area, for example, “y” is set to either “0” or “1”, and the most significant bit is discriminated from the non-spare area and the spare area. Flag address bits to be used. In other words, the block address of the non-spare area is
(0yyyyyyyyyy)
And the block address of the spare area is
(1yyyyyyyyyy)
And Of course, the flag address bit for discriminating between the non-spare area and the spare area does not need to be the most significant bit, and a bit at an arbitrary position such as the least significant bit can be used.

Furthermore, in this embodiment, the block address is assigned so as to reduce the number of “0” bits included in the block address of the spare area as much as possible. For this purpose, first, for example, it is necessary to assign a block address so that the number of “0” bits is smaller than the number of “1” bits. For this, a block address in which the address is all “1” bits in the block address of the spare area, for example,
(11111111111)
To be included. Furthermore, an example of a method for assigning block addresses more appropriately will be described below.

When all the address bits other than the flag address bits are “1”, in the example shown in FIG.
(11111111111)
Is class 0. Further, in class i, it is assumed that i bits that are arbitrary “1” of class 0 are replaced with “0”. For example, class 1 is obtained by replacing one bit from class 0 with “0”, class 2 is obtained by replacing two bits from class 0 with “0”, and so on. In this way, block addresses with fewer classes, such as class 0, class 1, class 2, and class 3, are selectively assigned to block addresses in the spare area. For this reason, the block address of the spare area becomes non-consecutive as a result. By doing so, rewriting of an area for storing a block address accompanying data transfer to the spare block shown in SE13, for example, the FAT area can be rewritten at high speed without the need to erase the FAT area. This is because, in order to set “1” data to “0”, it is necessary to save and erase data of the entire block including the FAT, whereas “0” data is changed to “1” data in the flash memory. This is because writing to be performed can be realized at higher speed than erasing by performing additional writing on each page.

On the other hand, in the typical method of assigning consecutive addresses as non-spare areas, even if block addresses are properly assigned,
Class 0 (11111111111)
Class 1 (11111111110)
Class 1 (11111111101)
Class 2 (11111111100)
Class 1 (11111111011)
Class 2 (11111111010)
Class 2 (11111111001),
Class 3 (11111111000)
As shown, class 3 appears seven times after class 0. Similarly, class n appears after (2 ⁿ −1) class 0.

On the other hand, in the address assignment of this embodiment, the number of addresses of class 0, class 1, and class 2 is set to “k” as the number of data bits excluding the flag indicating the spare area.
1 + k + k × (k−1) / 2
In the example shown in FIG. 12 in which k = 10, for example, up to 56 block addresses far more than the typical example of 8-1 = 6 can be kept below class 2. Spare block address selection may be performed, for example, in accordance with the sequence shown in FIG. 14 for any address in the non-spare area.

  The example shown in FIG. 14 is a replacement example when spare blocks up to class 2 are prepared. The number of classes can be expanded by creating a flow similar to SE31 to SE33 for each class and arranging them as a sequence between SE30 and SE31 in descending order of class. FIG. 14 shows an example of an address selection sequence for a spare block corresponding to SE13 shown in FIG. 11 or SE25 shown in FIG.

First, in SE30, a block address including the original page to be replaced is acquired, and a logical inversion a1 of the acquired block address is created. At this time, generally, it is necessary to invert without including the flag area indicating the spare area, but as described above, the block address of the non-spare area is
(0yyyyyyyyyy)
And the block address of the spare area
(1yyyyyyyyyy)
In such a case, it may be reversed including the spare area.

  Next, in SE31, the logical inversion a1 and the vacant spare block address (a2) of class 2 are ORed to determine whether or not “0” is included in each bit. When “0” is included, the address bit of the spare area is “0”, that is, in the erased state, and at the same time, the address bit of the original data page area is “1”, that is, in the written state. It becomes. In other cases, in response to a change in the address of the data page area included in the FAT area, each bit changes from “0” erase state to “0” erase state or write state “1”. It becomes only. Therefore, in SE32, the page is error-corrected and transferred to the spare block of the address obtained in SE31, and the change of the address of the data page area in the FAT area may be performed without erasing.

  Next, in SE33, it is determined whether or not all spare spare addresses that are not already used are examined for class 2 data replacement. All class 2 blocks are examined by the sequence of SE31 and SE33.

  Next, in SE34, a logical sum of the logical inversion a1 and the empty spare block address (a2) of class 1 is calculated, and it is determined whether or not “0” is included in each bit. When “0” is included, the address bit of the spare area is “0”, that is, in the erased state, and at the same time, the address bit of the original data page area is “1”, that is, in the written state. It becomes. In other cases, in response to a change in the address of the data page area included in the FAT area, each bit changes from an erased state of “0” to an erased state of “0” or a written state “1”. Only changes. Therefore, in SE35, the page is error-corrected and transferred to the spare block of the address obtained in SE34, and the change of the address of the data page area in the FAT area may be performed without additional erasure.

  Next, in SE36, it is determined whether or not all free spare addresses that have not been used for class 1 data replacement have been examined. All the class 1 blocks are examined by the sequence of SE34 and SE36.

  Next, in SE37, it is checked whether or not an empty spare block of class 0 has already been used. Since all address bits of class 0 are “1”, the FAT address can be replaced with a spare address only by additional writing. If it is not used, the page is error-corrected and transferred to the spare block obtained in SE37 in SE38, and the address of the data page area in the FAT area is changed without additional erasing. Just do it. If it is used in SE37, an empty spare block address having a class as large as possible is searched for in SE39, and the page is error-corrected and transferred to the spare block obtained in SE37. At this time, the change of the address of the data page area in the FAT area includes a bit for shifting from the “1” write state to the “0” erase state. Therefore, it is necessary to temporarily save the data in the FAT area, erase the FAT area, and then write back the data in the FAT area that has been replaced with the spare area.

  As described above, the FAT area is changed by additional writing, the deterioration due to repeated writing and erasing of the FAT area can be prevented, and a more reliable semiconductor memory device can be realized. Furthermore, since the probability of erasing the FAT area can be reduced, a page replacement operation can be realized at a higher speed.

  Next, the inventor's knowledge regarding the effect of determining that the number of error bits is equal to or greater than a predetermined reference value exceeding “1” and replacing it with a spare block as in this embodiment will be described.

The probability P _i that an i-bit bit error is included in each page having a page length of m bits, where the non-defective product rate per bit is “p”, is such that the page length bit number m is sufficiently larger than the error bit number i. It is given by the following Poisson distribution.

In a highly reliable semiconductor memory device, it is naturally necessary to suppress bit defects to be small, so that “mp <1” is satisfied. That is, the probability P _i is a function that rapidly decreases as the number of error bits i increases.

Next, when the total number of pages in the semiconductor memory device is “n” and the number of pages including i-bit bit errors is “k _i ”, the number of pages including 1, 2,. The probability (expected value) P _ex of k ₁ , k ₂ ,..., k _s is as follows.

By calculating the sum of the expected value _Pex by the combination of k ₁ , k ₂ ,..., K _{s that} can cause a bit failure, it is possible to calculate the failure rate as viewed from the external I / O. Next, the logarithm of the expected value P _ex is taken and partial differentiation is performed with “ki”. Thus, the points expected value P _ex is maximum, "n" is sufficiently larger than the "k _i", in each case "k _i" is 1 or more, the following the following error 8% ± become.

Therefore, when the expected value of the "k _i" is, "k _i" is sufficiently greater than 1,
nP _i / P ₀
Is equal to The expected value of “k _i ” when “k _i ≧ 1” is
The range is 0.6 × nP _i / P ₀ or more and nP _i / P ₀ or less. Here, “P _i ” is a function that rapidly decreases as “i” increases. Therefore, the expected value k _{i of the} number of pages including i error bits increases as “i” increases.
(Mp) ⁱ / i!
Decreases rapidly in proportion to. Therefore, in this embodiment in which it is determined that the number of error bits has reached the determination reference value of 2 or more and is replaced with a spare block, the number of spare blocks necessary for replacement can be drastically reduced by increasing the determination reference value.

  In addition, if the judgment reference value is within the number of bits that can be relieved by ECC, even if bit errors below the judgment reference value occur, all can be relieved by ECC, and the data output from the external I / O is: Information bits with all errors corrected can be output. Therefore, the determination reference value is set to the maximum number of bits that can be relieved by ECC. By setting the determination reference value to the maximum number of bits that can be relieved by ECC, it is possible to obtain the advantage that the number of spare blocks required for replacement can be reduced.

  The inventors have also found the following matters.

When the total number n of pages is sufficiently larger than the number of pages k _i including bit errors of i bits, from the format of “P _ex ”, when “P _i ” is sufficiently smaller than 1, the distribution of “k _i ” is Almost Poisson distribution,
(NP _i ) ^ki / (k _i )! Xexp (-nP _i )
Follow. Thus, the dispersion of the "k _i" may be considered to be equal to the expected value of "k _i". Accordingly, the number distribution of the number of pages including 1, 2,..., S bit errors can be obtained, and k ₁ , k ₂ ,..., K _s expected values and variances can be obtained. Therefore, it is possible to statistically calculate the number of spare blocks to be replaced with pages including error bits that are equal to or greater than the criterion value. For example, the number of pages including t bit errors can be considered to approximate a normal distribution due to the Poisson distribution property when the expected value of “k _t ” is 5 or more. Thus, for a page containing t bit errors,
k _t + 3 × (k _t ) If ^0.5 spare blocks are prepared, all pages including t bit errors can be replaced with a reliability of 99.7% or more.

  Furthermore, the present inventor statistically estimates spare blocks that can replace all the pages that are equal to or higher than the criterion value, and prepares them in advance to increase the probability of generating error bits as viewed from the external I / O. I found that it can be reduced.

  Here, it is assumed that the bit error of the storage device according to the present embodiment increases irreversibly from the time of shipment, for example, by repeating writing and erasing, and a bit once having a bit error does not return to normal. In this case, for example, in a configuration including an ECC circuit that can correct a t-bit error with a page length of m bits, if a page replacement can be performed up to n times when a t-bit error occurs, the page replacement is performed. The defective rate remedy equivalent to the configuration provided with the ECC circuit capable of performing error correction up to (n + 1) × t bits can be performed on the performed data unit.

Here, as described in the calculation of “P _i ”, in the case of a random bit failure, a good bit probability per bit is set to “p”, and an i-bit bit error is generated for each page having a page length of m bits. If “mp” is sufficiently smaller than 1, the probability P _i containing “i” increases as “i” increases.
(Mp) ⁱ / i!
Decreases rapidly in proportion to. Therefore, the probability that the data of the page that has been subjected to page replacement n times will cause an error that exceeds the number of bits that cannot be corrected at least than the data of the page that is not replaced,
(Mp) Decreases rapidly more than ^nt times.

As described above, when it is determined that the determination reference value t is equal to or greater than 2 and all pages including t or more bit errors are replaced, the failure rate causing an error bit viewed from the external I / O. Can be rapidly reduced to (mp) ^nt times or more.

From the above discussion, when a spare block that has been replaced once becomes defective, it may be replaced with a spare block. If a spare block that can be replaced up to n times is prepared for each page, the defect rate remedy equivalent to a configuration including an ECC circuit capable of correcting errors up to (n + 1) × t bits can be achieved. Moreover, the defect rate is (mp) ^nt / (nt)!
Decreases rapidly in proportion to.

Further, as a result of detailed examination, if the number of spare blocks that can replace a page that exceeds the number of bits that can be corrected by ECC is “bk”, at least the replacement is not performed when the block replacement of this embodiment is used. The allowable error total number of bits exceeding ECC is relaxed to the allowable error bit number obtained by adding (bk × t) to the allowable error total bit number ak exceeding the ECC of (bk × t). I found. Therefore, the number of spare blocks bk is further added so that the total number of allowable errors exceeding the ECC when no replacement is performed is ak ′, and bk> ak ′ / t. In this way, the defect rate is
(Mp) ^nt / (nt)!
Since the number of error bits viewed from the external I / O is almost zero, it can be realized.

Furthermore, the expected value of the number of spare blocks required for the second replacement is “k _2s ”, and the expected value of the number of spare blocks required for the first replacement is “k _s ”.
k _2s ≧ 1 and k _s ≧ 1
In this case, since (k _2s / k _s ) is proportional to (P _2s / P _s ), it rapidly decreases in proportion to (mp) ^s . Therefore, the increase in the chip area due to the number of spare blocks required for replacement twice or more can be suppressed to a sufficiently smaller range than the increase in the chip area due to the number of spare blocks required for replacement once or more. Of course, by using the address configuration of the spare area shown in FIG. 12, even when the spare block once replaced becomes defective, even when the spare block is further replaced, the smaller class address shown in FIG. By using it for replacement twice or more, the address of the data page area in the FAT area can be changed by performing additional writing without the need for erasing, and a replacement operation can be realized at high speed. This is a great advantage.

On the other hand, when the number of spare blocks to be replaced is less than the expected value, for example, when the number of pages exceeds the determination reference value, there is a data page including an error of t bits or more that cannot be replaced with a spare block. And a probability element P _ex exists. For this reason, in this case, the probability of including a defective bit is increased at least (mp) ^−nt times than the page where all replacements have been performed, and the probability of generating an error bit viewed from the external I / O is greatly increased. Will increase.

For example, the maximum guaranteed value of the number of bad blocks after the maximum number of writing and erasing specified by “n _block ” is “n _bad ”, and the number of ECC error-correctable bits is “ECC” bits and error bits. When the number of determination reference value bits is “id” bits, the following equation is statistically established as an average error bit state when block replacement is not performed.

Therefore, the upper limit mp _max of “mp” can be obtained from the case where the above equation is placed with an equal sign. Thereby, the upper limit n _replace of the average value of the number of blocks to be replaced required in the present embodiment is given by the following equation.

When considering up to the variation of the number of blocks, the distribution of as in the above discussion "n _block P _i", considered "n _block P _i", may be calculated by setting the reliability. Naturally, in the present embodiment, if the reliability is high, a larger number of replacement blocks than “n _replace ” is required. In addition, the expressions n _block , n _bad , and n _replace are regarded as the number of pages and the number of divided pages, respectively, when one block is divided and replaced with each page or replaced with divided pages. Just calculate. The total probability of occurrence of bit failures that cannot be remedied by ECC can be calculated by adding the probability P _ex by the number in each case.

  As described above, the external I / O can be obtained by statistically estimating and preparing in advance the spare block that can replace all pages that are equal to or greater than the error bit determination reference value in the ECC according to the present embodiment. As a result, the probability of generating an error bit seen from the above can be reduced.

  Here, the ROM 111 stores a reference value of an error bit for page replacement, but may be stored as a judgment value of a program of a flowchart as shown in FIG. 11, for example. Of course, the error bit number determination circuit 6 may be configured by hardware such as a sequencer.

  In the example shown in FIG. 11, the method of calculating the error position locator using the Peterson method is shown. Of course, the error position locator is calculated using another method, for example, the Euclidean method or the Berlekamp-Massey method. May be.

  Furthermore, as can be said with respect to all the embodiments other than the present embodiment, the Reed-Solomon (RS) code also uses the Peterson method, the Euclidean method, or the Berlekamp-Massey method in the same manner as the BCH code. From this, an error position locator can be obtained. Therefore, the configuration and effects described in the present embodiment can be realized.

  FIG. 15 shows an example in which an error in the contents of the first memory cell block is corrected, data is written to the second memory cell block, and data including error bits is replaced. Here, the second memory cell block formed of the spare area has substantially the same structure as the first memory cell block. Thereby, the area of the memory cell array can be reduced, and an advantage that a cheaper chip can be configured can be obtained. Further, the total number of pages in one block of the second memory cell block of this example needs to be at least equal to or greater than the total number of pages in one block of the first memory cell block.

  First, in SE40, the page counter 10 is reset to indicate the first page.

  Next, in SE41, the page indicated by the page counter 10 is read out, corrected for error, and stored in the page buffer 11 for the first memory cell block including a page equal to or greater than the error bit determination reference value. At this time, if necessary, for example, when a read operation of this block is instructed from outside the system, the content of the main read may be output from the external I / O.

  Next, in SE42, the contents of the page buffer 11 are encoded and written to the second memory cell block in the spare area indicated by the page counter 10 so as to become an error detection code. In addition to the write information bits, a data write end flag may be written to other bits of the second memory cell block after the write ends. In this way, it is possible to detect a writing failure due to power interruption during writing and perform a return sequence.

  Next, in SE43, the count value of the page counter 10 is increased by, for example, “1”.

  Next, in SE44, it is determined whether or not the page counter 10 refers to the indexes of all pages). This is because, when the sequence of SE43 that increments the count value of the page counter 10 by “1” is used, whether or not the index is lower than the total number of pages included in the first memory cell block. Is equivalent to determining In this example, the replacement method for each memory cell block is shown, but of course, replacement may be performed for each page. In this case, the page counter 10 is not necessary. The page address of the page to be replaced in the spare block area corresponds to the “0” or “1” bit for the page address of the original page that is equal to or higher than the error bit determination reference value, and the “1” bit. Selects the page address of the spare block area so as to correspond to the “1” bit. As a result, the FAT change for the page address can be dealt with by additional writing, eliminating the need for erasing and realizing high-speed rewriting.

  FIG. 16 shows a circuit example of the page buffer. The circuit example shown in FIG. 16 is an example of the page buffer 11 that temporarily stores k-bit data that is the number of information bits.

  In this example, D-type flip-flops 201 are connected in series in k stages, and the output of the final stage is a bi-lateral switching circuit composed of an n-channel transistor 202, a p-channel transistor 203, and an inverter 204. Connected by. The D-type flip-flop 201 of this example outputs an output at the moment when the clock input rises from “L” (for convenience, 0 V here) to “H” (for convenience, Vcc here). After that, an edge trigger type flip-flop in which the output does not change even if the clock remains “H”, “L”, or changes from “H” to “L”. . Further, the bidirectional switch circuit is a circuit in which the current terminals of the transistors 202 and 203 are turned on when the data output control input is “H” and turned off when the data output control input is “L”. FIG. 17 shows the operation of the circuit.

  As shown in FIG. 17, when data is stored in the D-type flip-flop 201, first, the data output control input is set to “L” so that the output of the flip-flop 201 is not output to the data input / output line. Further, after Vcc (“H”) or 0 V (“L”) digital data Din1 is applied to the data input / output (I / O) line, the clock is changed from “L” to “H”. As a result, the data Din1 is held in the flip-flop 201 shown on the leftmost side in FIG. Next, Vcc (“H”) or 0 V (“L”) digital data Din2 is applied to the data input / output (I / O) line, and then the clock is changed from “L” to “H”. Thereby, the data Din1 is transferred and held in the flip-flop 201 shown second from the left in FIG. 16, and the data Din2 is held in the flip-flop 201 shown on the leftmost side. Thereafter, digital data is sequentially applied to the data input / output (I / O) line up to k bits, and a clock is applied, so that “Din1, Din2,... In order from the rightmost flip-flop 201 shown in FIG. Data of “Dink” is held. In this way, the page buffer 11 holds k-bit data.

  When reading data from the page buffer 11 according to this example, first, the data output control input is set to “H”, and the output of the flip-flop 201 shown on the rightmost side in FIG. 16 is used as the data input / output (I / O) line. Output. As a result, the same data as the data Din1 (here, Dout1) is output to the data input / output (I / O) line. Further, the clock input is changed from “L” to “H”. As a result, 1-bit data is transferred to and held in the flip-flop 202 shown on the rightmost side in FIG. As a result, the same data as the data Din2 (here, Dout2) is output to the data input / output (I / O) line. Thereafter, by changing the clock input from “L” to “H” a total of (k−1) times, the flip-flop 201 shown on the rightmost side in FIG. 16 is connected to the data input / output (I / O) line. The data of “Din1, Din2,..., Dink” are output in order. In this way, the page buffer 11 outputs k-bit data.

  The present embodiment further has the following requirements and effects.

(1) All embodiments disclosed in this specification can reduce the defect rate as viewed from the external I / O without increasing the number of bits that can be relieved by ECC. Therefore, it is possible to reduce the calculation time for calculating the position of the ECC error bit and the circuit area, which are generated when the number of bits that can be relieved by ECC is increased. When the number of bits that can be relieved by ECC increases by one, the number of bits used by ECC increases by at least the number of bits obtained by rounding up log ₂ (n) decimal points. Therefore, the situation that the code length becomes long, and as a result, the chip area increases or the number of data bits that can be used by the user can be solved, and a highly reliable storage device is realized with a smaller memory cell array area. it can.

  By preparing the spare spare area in the amount described in the specific configuration of the system, the memory area viewed from the external I / O can be guaranteed based on the reliability up to the life of the memory by replacing the spare area. .

Also, for pages that exceed the number of bits that can be corrected by ECC, the number of replacement spare blocks that can be replaced is set to “bk”, the error bit determination reference value is set to “t”, and the allowable error exceeds the ECC when replacement is not performed. If the number of spare blocks bk is further added so that the total number of bits is “ak ′” and “bk> ak ′ / t”, the number of error bits viewed from the external I / O is almost equal. A state in which there is no one bit can be realized, and a semiconductor memory device with higher reliability than ever can be realized. Further, by using an error bit reference value larger than 1 bit, the number of replacement spare blocks can be reduced as compared with the conventional case, and an integrated circuit with a smaller area can be realized. In particular, the number of blocks is “n _block ”, the maximum guaranteed value of the number of blocks required to be replaced after the specified maximum number of writes and erasures or at the end of the product warranty life is “n _bad ”, and ECC error correction bits When the number is ECC bits and the number of error bit determination reference value bits is id bits, the defect rate reduction effect in the embodiment is further enhanced by forming a replacement block number n _replace that is at least equal to or greater than the following expression.

Note that “a” in the above equation is a variable that can be deleted by simultaneous equations. In addition, the expressions n _block , n _bad , and n _replace are regarded as the number of pages and the number of divided pages, respectively, when one block is divided and replaced with each page or replaced with divided pages. To calculate.

Further, since id ≦ ECC, the following expression is established.

(2) Furthermore, the probability of performing block replacement with a replacement spare block is:
1- (total sum of P _{ex under} the condition that the error location is smaller than the criterion value in all pages)
Can be calculated quantitatively. Therefore, the probability of occurrence of the time required for block replacement can be obtained, and the system performance can be quantitatively guaranteed. For example, when n1 and n2 are natural numbers satisfying n1 <n2, the spare block replacement probability is 0% and the system cannot be accessed from the external I / O until the number of times of writing and erasing is n1. In addition to guarantee, for example, from n1 to n2 times, if the replacement probability of the spare block is r and the time for rewriting is tk, the product that the system cannot access from the external I / O by tk × r occurs You can make a guarantee. Thereby, it is possible to realize a highly reliable semiconductor memory device in which reliability is quantitatively guaranteed as compared with the conventional device.

  (3) In the semiconductor memory device 7 of the data storage system, a plurality of semiconductor memories including error correction bits are formed, and the data destruction is performed only by the difference in the number of rows in the memory cell array and the memory circuit not including the error correction bits. No special circuit or means such as a detection dedicated cell is required for the semiconductor memory device 7. Therefore, in particular, since the error correction bit and the information storage bit can be repeatedly formed in the same pattern adjacent to each other, an inexpensive data storage system having a small chip area can be realized by using the same semiconductor memory device 7 as the conventional one. . Furthermore, in the present embodiment, when data is actually read, the number of bits in which an error has occurred is detected for each page. For example, there is no need to read data for refresh when there is no need to read data from an external I / O, such as when power is turned on and off, as in conventional devices. Therefore, it is possible to reduce the processing time and power required for refreshing data, and it is possible to detect a large number of errors for a page with a larger number of actual reads. In particular, this configuration can detect the occurrence of error bits due to writing and erasure when it includes a read-out operation to check whether the threshold value is within the setting at the time of erasing and writing. A semiconductor memory device having a high level can be realized. Further, error detection is always performed after the time point when information bits requiring error correction are generated. Therefore, even if the statistical behavior of so-called “bottom bits” that generate error bits changes between chips or changes with time, error detection can be performed correctly.

  (4) The ECC circuit 100 has a circuit that can perform error bit correction. Even when a data error occurs from “1” to “0” in the process of outputting data to the external I / O, “0” to “1”. Any error in the data can be corrected. Therefore, with this configuration, data correction of read-disturb of erased bits due to read stress, data correction of write data retention failure, excessive threshold value exceeding the setting that is a problem in NAND structure Data correction for overwriting and erroneous data correction by writing to memory cells connected to non-selected data lines can also be performed.

  (5) For example, as shown in FIG. 3, memory cells M0 to M15 corresponding to a plurality of pages are formed between the select gate transistors S1 and S2, and these are used as one block. In a memory that simultaneously erases data, the write time for one page can be made very small compared to the erase time for one block. Therefore, by forming a spare block that has been erased in advance, the replacement time for the spare area can be reduced. Can be shortened.

  (6) In the present embodiment, unlike the conventional apparatus, actual error bits are directly detected from the data subjected to error correction coding. Therefore, even if any of the encoded bits is a cell that is very weak against write stress or read stress, that is, “bottom bit”, it can be correctly detected when a data error occurs. Therefore, the data replacement interval can be set in accordance with the characteristics of the “base bit” of the actual memory cell, and the time spent for data replacement can be shortened by increasing the data replacement interval.

  (7) In this embodiment, error bit detection is performed by reading data once per page. Therefore, the time required for reading does not change as compared with the case where conventional error correction is not detected, and reading can be performed at high speed.

  (8) In the data storage system according to the present embodiment, the block replacement operation can be performed when a series of operations of turning off the power, turning on the power, and reading one page of data from the external data output terminal are repeated a plurality of times. The number of times that the same information data as the information data written to the page can be read is the number of times that the same information data as the information data written to the page can be read because the block replacement operation can be performed. Can do more. Therefore, when viewed from the outside of the system, the data storage system is improved in reliability with respect to the read-disturb transition of the erase bit due to the read stress as compared with the semiconductor memory circuit 7 alone. In addition, the number of repetitions of write / erase can be substantially increased by replacing the present embodiment even for defective bits (over-program) that exceed the write set value, which increases in frequency due to repeated write / erase. And more reliable.

  (9) In this embodiment, the second memory cell block, which is a spare area, may be erased in advance before shipment, and the erase time can be shortened with respect to data rewriting to the spare area.

(10) Although a coding circuit and a decoding circuit of a 2-bit error-correctable cyclic BCH code are shown here, of course, other code systems, for example, a general BCH code, an M-sequence code, a convolutional code (convolutional code) ), A difference set cyclic code, or a combination thereof. However, in order to reduce the number of second internal I / O lines and the number of first internal I / O lines, information bits are given in time series, and encoding and decoding are performed with a small circuit scale. It is preferable that the cyclic code can be converted into a cyclic code. Further, for example, a so-called byte code having 2 ^r elements obtained by collecting r bits of a code word may be used. For example, a Reed-Solomon code which is a byte code in the BCH code system may be used. In the case of a byte code, first, a byte error that one of the originals has an error is detected, and then the byte before error correction and the byte after error correction are compared one bit at a time. What is necessary is just to discriminate | determine whether the bit which produced the error in each bit of this data is "1" or "0". After this, for example, when the determination result is erroneous in at least one bit, the replacement operation may be performed. Also, as the convolutional code, for example, a 1-bit error-correctable Wiener-Ash code, a burst error-correctable Iwadare code, or a Hagelbarger code may be used. it can.

  (11) In the sequence shown in FIG. 15, the sense amplifier / data register circuit 46 can realize the main copy only by storing information for one page, read data from the external I / O to the outside, There is no need to provide a temporary memory. Therefore, there is no time for data transfer through the external I / O, the sequence can be executed at high speed, and the power for driving the external I / O circuit can be reduced.

(Second Embodiment)
The second embodiment is almost the same as the first embodiment, but the sequence and circuit configuration for the case of repair by ECC are different from the first embodiment. In the second embodiment, the same portions and the same voltage relationship as those in the first embodiment are denoted by the same reference numerals or omitted in the drawings, and redundant description will be omitted.

  FIG. 18 is a block diagram illustrating a block example of the ECC circuit 100 included in the apparatus according to the second embodiment.

As shown in FIG. 18, the ECC circuit 100 included in the apparatus according to the second embodiment uses the outputs (syndrome) s1, s3,..., S _2t-1 (syndrome input) of the syndrome calculator 15 for the error position locator. Input to the ROM 112. The error position locator corresponding ROM 112 outputs error position locators α ^-i , α ^-j ,... Α ^-n (error position locator input) and information bits indicating the number of error bits. These outputs are input to the I / O port 106. The error bit number determination circuit 6 can obtain an error-corrected code output by inverting the bit at the error position indicated by the error position locator by the number of error bits. In this example, the ROM of the error bit number reference value storage unit 111 stores an error bit reference value for page replacement. This is the same as the ROM 111 of the first embodiment, for example, as shown in FIG. The judgment value of the program of the flowchart shown in FIG. Of course, for example, the error bit number determination circuit 6 may be configured by hardware such as a sequencer.

  FIG. 19 is a flowchart showing an operation example of the apparatus according to the second embodiment.

FIG. 19 shows an example in which page data is selectively replaced with an empty spare block and replaced by ECC in the case of an error determination bit number larger than 1 bit, in this case t-bit error, at the time of reading. ing. In this example, a method is described in which a correspondence table of syndromes s1, s3, and s2t _-1 and an error position locator is created in advance on the ROM 111 to obtain an error bit position at high speed.

First, in SE 1 ′, the syndromes s ₁ , s 3,..., S _2t−1 are transferred from the error bit detection circuit 5 to the error bit number determination circuit 6 through the I / O port 106. The received code is transferred from the error bit detection circuit 5 to the page buffer 11 in the bit number determination circuit 6 through the I / O port 106.

Next, in SE16, the syndromes s1, s3,..., S2t _-1 are given to the address input of the “syndrome → error position locator correspondence table” on the ROM 111, and the error position locator and the number of errors are obtained as data. FIG. 20 shows an example of a correspondence table for obtaining an error position locator from a syndrome. In this example, given as an address input, t sets the syndrome is the root of the Galois field GF (2 ^4), respectively, i.e., syndromes s1, s3, ..., a s _2t-1. Therefore, the number of input address bits is 4 × t bits in this example. On the other hand, error position locators α- ⁱ , α- ^j ,... Α- ⁿ , which are roots on the Galois field GF (2 ⁴ ), and information bits for outputting the number of error bits are output. For example, if the number of information bits for outputting the number of error bits is equal to the number obtained by rounding up the decimal point of log ₂ (t + 1) (hereinafter referred to as cn), the number of error bits can be output by the binary system. Since BCH is a linear code, there is no error bit when all syndromes are “0”.

As the number of 1-bit error addresses, if (original number of Galois field) is q (16 in the case of GF (2 ⁴ )),
_q-1 C ₁ = q-1 addresses correspond to each other, and an error position locator α ^-i is output. Further, since the inverse element of the syndrome s1 is α- ⁱ , the calculation may be performed directly from the syndrome s1 using the inverse element table ROM. Here, i, j,..., N in FIG. 20 are integers of 0 or more and (q-1) or less, and are mutually different integers. In addition, (e1, f1, g1, h1), (e2, f2, g2, h2), ..., (et, ft, gt, ht) are vector displays of the syndromes s1, s3, ..., _s2t-1. Yes, (a, b, c, d) may be an arbitrary value of the error position locator output displayed in vector.

Similarly, the number of 2-bit error addresses is
_q-1 C ₂ = (q-1) (q-2) / 2 addresses correspond to each other, and two error position locators α ^-i and α ^-j are output. As an alternative to this, if the first bit error position locator α- ⁱ is known, the second bit error position locator is
α ^-j = 1 / (s1 + 1 / α ^-i )
Therefore, the error position locator α ^-j of the second bit can be easily calculated if there is an inverse table ROM. Therefore, one locator may be used. The inverse element table ROM may be incorporated in the error bit number determination circuit 6. By incorporating the inverse table ROM in the error bit number determination circuit 6, the operation speed can be increased. In this case, the inverse element table ROM is formed on the ROM 111, for example.

Similarly, if “k” is an integer between 1 and t, the number of addresses with k-bit errors is
_q-1 C _k addresses correspond to each other, and k error position locators α ^-i , α ^-j ,..., α ^-k are output. As an alternative to this, if the error position locators α ^-i , α ^-j , ..., α- ^(k-1) from the 1st bit to the (k-1) th bit are known, the error position locator of the kth bit is
α- ^k = 1 / (s1 + 1 / α- ⁱ + ... + 1 / α- ^(k-1) )
Therefore, the error position locator α ^-j of the second bit can be easily calculated if there is an inverse table ROM. Similarly, as a correspondence table up to t bits, as shown in FIG. 20, (0 bit error output), (1 bit error output), (2 bit error output), ..., (t bit error output) It is only necessary to set the output of the error position locator for 1, _q-1 C ₁ , _q-1 C ₂ ,..., _Q-1 C _t addresses, respectively. May exceed “t bits”. The number of output data bits is (0 bit error output), (1 bit error output), (2 bit error output),..., (T bit error output) in this example of Galois field GF (2 ⁴ ). ), (4 × 1 + cn), (4 × 2 + cn),..., (4 × t + cn) may be prepared. For example, when ECC is relieved up to 2 bits, t = 2, and in the example of the defect relieving condition similar to FIG. 11 where q = 16,
May be set the output of the error position locator with respect to _{(1+ 16-1 C 1 + 16-1 C} 2) = 1 + 15 + 105 = 121 amino address, 0 bit defect, 1 bit failure, the output of each of 2-bit failure The number of data bits may be 2, 6, 10 bits. In this case, the number of data in the ROM 111 is at least
A ROM data area of 1 × 2 + 15 × 6 + 105 × 10 = 1114 bits may be prepared. When the inverse table ROM is used, in this example of the Galois field GF (2 ⁴ ), (0 bit error output), (1 bit error output), (2 bit error output), (t Bit error output), cn, cn, {4 × (2-1) + cn},..., {4 × (t−1) + cn} may be prepared. In this case, if the output of the error position locator is set for 121 addresses, the number of output data bits of 0-bit failure, 1-bit failure, and 2-bit failure will be 2, 2, and 6 bits, respectively. good. In this case, the number of data in the ROM 111 is at least
A ROM data area of 1 × 2 + 15 × 2 + 105 × 6 = 662 bits may be prepared. The method using the inverse table ROM and the conversion table ROM 111 can keep the necessary ROM area as small as 678 bits even if the necessary number of data 16 bits is added to the inverse table ROM.

  Based on the error position locator thus obtained and the number of errors, it is determined in SE17 whether or not there are one or more bit errors. Specifically, this is the data bit shown in the error number output example in FIG. 20, for example, it may be determined that it is “001” or more in binary number. If it is smaller than “001”, that is, “000”, there is no error bit, so the first 7 bits of the sign bit are output as information bits. When there are one or more bit errors (Y), the process proceeds to SE18.

  In SE18, it is determined whether or not there are t or more bit errors. Specifically, this is a data bit shown in the error number output example in FIG. 20, and it is only necessary to determine that it is a binary representation of t-bit binary number, for example, “110” or more. When it is smaller than “110”, the bit error is 1 bit or more and (t−1) bits or less (N). In this case, the process proceeds to SE19. In SE19, for example, the bit at the position indicated by the error position locator is inverted on the page buffer 11 to perform error correction, and correct data is output from the external I / O. If it is “110” or more, the bit error is t bits or more (Y). In this case, the process proceeds to SE20.

  In SE20, it is determined whether or not the bit error is t bits. Specifically, this is a data bit shown in the output example of the number of errors in FIG. 20, and it may be determined that it is equal to, for example, binary representation of t-bit binary number, for example, “110”. If there are more bit errors than t, error correction cannot be performed (N). Therefore, in this case, in SE21, for example, it is output to the external I / O that a bit failure exceeding t bits has occurred, that is, that a bit failure that cannot be corrected for errors has occurred. On the other hand, when the bit error is t bits, in SE22, the (i + 1) th bit, the (j + 1) th bit,..., And the (n + 1) th bit counted from the last input bit in 15 bits are considered to be errors. , T bit error locator position bits are inverted and corrected.

  Next, in SE23, it is confirmed whether there is a spare block area that is not used. For example, a storage area for storing a spare block address that can be used in advance is prepared in the FAT area, and a spare block address is stored in the storage area for the used spare block. That is, in SE23, it is possible to confirm whether there is a spare block area that is not used by checking the address stored in the storage area. As the block replacement method, the method described in the first embodiment may be used. Next, when it is determined in SE23 that “there is an empty spare block area” (Y), in SE25, the page content is error-corrected and transferred to the empty spare block area. Subsequent to this operation, the FAT area address may be replaced with an empty spare block.

  If it is determined in SE23 that “there is no free spare block area” (N), in SE24, a signal indicating that there is no free spare block area is output from the external I / O. Subsequent to this operation, the page content may be written back to the original memory block address.

  As described above, since the operation shown in FIG. 19 uses the method of drawing the correspondence table of the error position locator as compared with the first embodiment, the error position can be obtained at high speed, and data conversion is performed at higher speed. be able to. Of course, as shown in this embodiment, a method of keeping the capacity of the correspondence table of the error position locator small in combination with the inverse element table ROM or the like may be used. In this case, a memory having a small ROM capacity necessary for ECC correction can be realized at a relatively high speed.

(Modification of the second embodiment)
Next, a modification of the second embodiment will be described.

FIG. 21 is a block diagram illustrating a block example of the ECC circuit 100 included in the apparatus according to the modification of the second embodiment. FIG. 22 shows an output example of the error position locator of the ROM provided in the syndrome input used in the apparatus according to the modification of the second embodiment. The ROM of this modification is basically the same as the ROM of the second embodiment, but the outputs (syndromes) s1, s3, and s2t _-1 of the syndrome calculator 15 are input to the error position locator corresponding ROM 112. , Error position locators β ⁱ , β ^j ,..., Β ⁿ and information bits for outputting the number of error bits are output. Further, (abcd) in FIG. 22 is an address expression that is larger than the maximum value of the binary expression value of the code length or becomes (0000). Here, β is not an element on the Galois field, for example, but may be an address representation of error position bits in a normal binary number, for example. That is, the locator β ⁱ indicating the error position of the i-th bit and the locator β ^{i + 1} indicating the error position of the (i + 1) -th bit are address expressions such that the code becomes a binary increment or decrement by one. To do. For example, when it is the i-th bit from the first input error position, “β ⁱ ” may be an address representation of the error position bit in the binary number “i”. For example, if the second bit is incorrect and “i = 2”, it may be (0010), and if “i = 1”, it may be (0001). In this modification, for example, this output is used as an initial value setting input of t counters 116, and by giving a clock input CLK, the value of the counter 116 is decreased by 1 bit so that it does not become (0000) or less. It shall be. Here, when the value of one of the t counters 116 becomes (0001), a circuit (corresponds to an OR circuit connected to the counter output in FIG. 21) that outputs “1”. If the output of the buffer is inverted (in FIG. 21, the exclusive OR circuit corresponds), the error bit is corrected in the output range of the sign bit. Can be obtained. In this modification, the error bit number determination circuit 6 of the second embodiment can be configured only by hardware. Therefore, it is possible to obtain a high-speed error-corrected code output by inverting the bit at the error position according to the number of error bits without requiring a software program including repetition. For example, all the codes are stored in the page buffer 11 when the syndrome calculation is completed by the syndrome calculator 15. Therefore, in this modification, the error-corrected code can be obtained instantaneously by giving the clock input CLK to the page buffer 11 and the counter 116 after the output delay time of the error position locator compatible ROM 112. Further, the ROM 111 stores a reference value of an error bit for performing page replacement. This is, for example, similar to the circuit shown in FIG. 7 of the first embodiment of the program of the flowchart of FIG. It may be stored as a judgment value.

  Also in the apparatus according to the second embodiment and the apparatus according to the modification of the second embodiment, the same requirements and effects as the first embodiment, for example, the requirements described in (1) to (11) , And have an effect.

(Third embodiment)
23 and 24 are cross-sectional views illustrating a cross-sectional example of a memory cell included in the device according to the third embodiment. The cross section shown in FIG. 23 corresponds to the cross section shown in FIG. 5 of the first embodiment, and the cross section shown in FIG. 24 corresponds to the cross section shown in FIG. Note that the planar pattern is the same as the planar pattern shown in FIG. 4 of the first embodiment, and is omitted in this embodiment.

  In the third embodiment, the NAND cell array block 49 using the floating gate type MOS transistor described in the first embodiment is changed to a NAND cell array block 49 using an M-NO-S transistor or an M-ONO-S transistor. It is a thing.

As shown in FIGS. 23 and 24, the nonvolatile memory cells are connected in series as in the first embodiment. The nonvolatile memory cell of the present embodiment is, for example, a so-called M-NO-S type EEPROM cell or M-ONO-S type EEPROM cell using SiN or SiON as the charge storage layer 26 (hereinafter referred to as M-ONO). -S type cell). One end of the M-ONO-S type cells connected in series is connected to the data transfer line 36 (BL) via the selection transistor, and the other end is connected to the common source line 33 (SL) via the selection transistor. Is done. The M-ONO-S type cell and the selection transistor are each formed on the same p-type silicon region 23. The impurity concentration of the p-type silicon region 23, for example, the boron concentration is in the range of 10 ¹⁴ cm ⁻³ to 10 ¹⁹ cm ⁻³ as in the first embodiment. For example, the p-type silicon region 23 is separated from the p-type silicon substrate 21 by the n-type silicon region 22. As a result, the p-type silicon region 23 can be applied with a potential independently of the p-type silicon substrate 21, and, similarly to the first embodiment, the load on the booster circuit at the time of erasing is reduced and the power consumption can be suppressed. can get. A tunnel insulating film 25 is formed on the portion where the memory cell on the p-type silicon region 23 is formed, and gate insulating films 25 _SSL and 25 _GSL are formed on the portion where the selection transistor is also formed. An example of the tunnel insulating film 25 in the present embodiment is, for example, a silicon oxide film or a silicon oxynitride film having a thickness in the range of 1 nm to 10 nm. An example of the gate insulating films 25 _SSL and 25 _GSL is, for example, a silicon oxide film or a silicon oxynitride film that is thicker than the tunnel insulating film 25. An example of the thickness of the gate insulating films 25 _SSL and 25 _GSL is, for example, in the range of 3 nm to 15 nm. A charge storage layer 26 is formed on the tunnel insulating film 25. An example of the charge storage layer 26 in the present embodiment is, for example, a silicon nitride film or a silicon oxynitride film having a thickness in the range of 3 nm to 50 nm. A block insulating film (intergate insulating film) 50 is formed on the charge storage layer 26. Examples of the block insulating film 50 in the present embodiment are, for example, a silicon oxide film having a thickness of 2 nm to 10 nm, Al ₂ O ₃ , HfSiO, ZrSiO, HfSiON, and ZrSiON. A polysilicon layer 51 is formed on the block insulating film 50 and polysilicon layers 51 _SSL and 51 _GSL are formed on the gate insulating films 25 _SSL and 25 _GSL . The polysilicon layers 51, 51 _SSL and 51 _GSL have a thickness in the range of 10 nm to 500 nm, for example, and contain phosphorus, arsenic, or boron in the range of 10 ¹⁹ cm ⁻³ to 10 ²¹ cm ⁻³ . The polysilicon layers 51, 51 _SSL , and 51 _GSL may be provided as necessary. A control gate 27 (WL0 to WL15) is formed on the polysilicon layer 51, a control gate 27 (SSL) is formed on the polysilicon layer 51 _SSL , and a control gate 27 ( _GSL ) is formed on the polysilicon layer 51 GSL. ) Is formed. An example of the control gate 27 has a thickness in the range of 10 nm to 500 nm, for example, and includes phosphorus, arsenic, or boron in the range of 10 ¹⁷ cm ⁻³ to 10 ²¹ cm ⁻³ , as in the first embodiment. It is a stack structure of polysilicon or metal silicide and polysilicon. Examples of the metal silicide are, for example, WSi, NiSi, MoSi, TiSi, and CoSi. Note that if the concentration of phosphorus, arsenic, or boron in the polysilicon layers 51, 51 _SSL , 51 _GSL , and / or the control gate 27 (WL0 to WL15) is set to 10 ¹⁹ cm ⁻³ or more, the polysilicon layer 51, and / Or depletion of the control gate 27 (WL0 to WL15) can be prevented, and an electric field applied to the ONO stacked film (block insulating film 50 or charge storage layer 26) is increased, thereby suppressing an increase in erase time or write time. You can get the benefits you can.

  Each of the control gates 27 (WL0 to WL15) constitutes data selection lines WL0 to WL15 shown in FIG. 2, for example. Each of the data selection lines WL0 to WL15, for example, connects adjacent memory cell blocks 49 and is formed from one end of the memory cell array 1 to the other end along the row direction.

  The control gates 27 (SSL, GSL) constitute, for example, block selection lines SSL, GSL shown in FIG. Each of the block selection lines SSL and GSL, for example, connects adjacent memory cell blocks 49 and is formed from one end to the other end of the memory cell array 1 along the row direction.

  Also in the gate structure of this embodiment, the side walls of the charge storage layer 26 and the side walls of the p-type silicon region 23 and the like are covered with the insulating film 24 as in the first embodiment. For this reason, the side wall of the p-type silicon region 23 (the side wall of the shallow groove) is not exposed to the outside, and the charge storage layer 26 can be suppressed from being formed even below the p-type silicon region 23. Therefore, also in the present embodiment, similar to the first embodiment, there are advantages that the gate electric field concentration can be suppressed, the generation of parasitic transistors can be suppressed, and the sidewalk phenomenon can be suppressed.

Side wall insulating films 43 are formed on both side walls of the gate structure. An example of the sidewall insulating film 43 is a silicon nitride film or a silicon oxide film having a thickness of 5 nm to 200 nm, for example, as in the first embodiment. N-type diffusion layers 28, 28 _d , and 28 _s are formed in the portion of the p-type silicon region 23 located between the gate structures. The n-type diffusion layers 28, 28 _d and 28 _s are a source electrode or a drain electrode of a memory cell or a select transistor. The n-type diffusion layers 28, 28 _d , and 28 _s contain, for example, phosphorus, arsenic, or antimony at a surface concentration of 10 ¹⁷ cm ⁻³ to 10 ²¹ cm ⁻³ and a depth of 10 nm to 500 nm. Formed.

  The memory cell according to the present embodiment, for example, an M-ONO-S type cell, includes an n-type diffusion layer 28, a tunnel insulating film 25, a charge storage layer 26, a block insulating film 50, and a control gate 27. The conductor layer, for example, the polysilicon layer 51 is provided between the block insulating film 50 and the control gate 27 as necessary. An example of the gate length of the M-ONO-S type EEPROM cell is, for example, 0.01 μm or more and 0.5 μm or less.

The selection transistor includes n-type diffusion layers 28, 28 _s , 28 _d , gate insulating films 25 _SSL , 25 _GSL , and control gate 27 (SSL, GSL). The conductor layer, for example, the polysilicon layer 51 is formed between the gate insulating film 25 _SSL and the control gate 27 (SSL) and between the gate insulating film 25 _GSL and the control gate 27 (GSL) as necessary. Provided. An example of the gate length of the selection transistor is longer than the gate length of the M-ONO-S type EEPROM cell, and is, for example, 0.02 μm or more and 1 μm or less. If the gate length of the selection transistor is longer than the gate length of the M-ONO-S type EEPROM cell, a large ON / OFF ratio between when the block is selected and when the block is not selected can be secured. This is effective in suppressing erroneous writing and erroneous reading.

This embodiment shows a NAND type, and the M-ONO-S type cell and the selection transistor are connected in series with each other. For this reason, the n-type diffusion layers 28, 28 _d , and 28 _s are shared by adjacent M-ONO-S cells, adjacent selection transistors with adjacent M-ONO-S cells, and adjacent selection transistors. Is done.

The n-type diffusion layer 28 _d is connected to the data transfer line 36 (BL) via a contact 31 _d , an intermediate wiring 33 _d , and a contact 34 _d . The data transfer line 36 (BL) constitutes, for example, the data transfer lines BL1a to BL2k shown in FIG. For example, the data transfer lines BL1a to BL2k connect adjacent memory cell blocks 49 and are formed from one end to the other end of the memory cell array 1 along the column direction. A material example of the data transfer line 36 (BL) is, for example, tungsten, tungsten silicide, titanium, titanium nitride, or aluminum.

The n-type diffusion layer 28 _s is connected to the source line 33 (SL) via the contact 31 _s . The source line 33 (SL) constitutes, for example, the source line SL shown in FIG. The source line SL is formed from one end to the other end of the memory cell array 1 along the row direction, for example, connecting adjacent memory cell blocks 49. The source line SL, the n-type diffusion layer 28 _s, connect to what adjacent memory cell blocks 49, formed from one end of the memory cell array 1 to the other along the row direction, the source of n-type diffusion layer 28 _s per se The line SL may be used.

The contacts 31 _s , 31 _d , and 34 _d are formed in the openings 30 _s , 30 _{d, and} 35 _d formed in the interlayer insulating film 68. Examples of the material of the contacts 31 _s , 31 _d , and 34 _d are, for example, n-type or p-type doped polysilicon, tungsten, tungsten silicide, aluminum, titanium nitride, or titanium, or a laminated structure of these conductive materials. is there. An example of the material of the interlayer insulating film 68 is a silicon oxide film or a silicon nitride film. An insulating film protective layer 37 and an upper wiring layer (not shown) are formed on the interlayer insulating film 68 and the data transfer line 36 (BL). A material example of the insulating protective layer 37 is, for example, a silicon oxide film, a silicon nitride film, or polyimide. An example of the material of the upper wiring layer is tungsten, aluminum, or copper.

  According to the third embodiment, in addition to the advantages obtained from the first embodiment, since the M-ONO-S type cell is used, the write voltage, and the floating gate type cell according to the first embodiment, and The erase voltage can be lowered. As a result of the reduction in voltage, the isolation voltage can be sufficiently maintained even when the element separation interval is narrowed and the gate insulating film is thinned. Therefore, the area of the circuit to which the high voltage is applied can be reduced, and the chip area can be easily reduced.

  Furthermore, compared with the floating gate type cell, the thickness of the charge storage layer 26 can be reduced, for example, 20 nm or less, and the aspect ratio of the gate structure can be reduced. As a result of the reduced aspect ratio of the gate structure, the workability of the gate structure is improved. Furthermore, the burying property of the interlayer insulating film 68 between the gate structures is improved, and the withstand voltage is also improved.

  Further, compared to the floating gate type cell, a process for forming the floating gate and a process for forming a slit for separating the floating gate along the row direction are unnecessary. Therefore, the manufacturing process time is shortened.

  Further, as compared with the floating gate type cell, the charge storage layer 26 is an insulator, and the charge is trapped in the charge trap. For this reason, electric charges are difficult to escape and, for example, strong resistance to radiation can be obtained. In addition, even if the sidewall insulating film 43 is thinned, all charges trapped in the charge trap are not lost, and good charge retention characteristics can be maintained.

  Furthermore, since the charge storage layer 26 can be formed without misalignment with the p-type silicon region 23, the capacitance between the charge storage layer 26 and the p-type silicon region 23 can be made more uniform. Therefore, capacity variation between memory cells is reduced.

(Fourth embodiment)
FIG. 25 is a block diagram showing a configuration example of a cell array portion and a sense amplifier portion of a data storage system according to the fourth embodiment of the present invention. The block diagram shown in FIG. 25 corresponds to the block diagram shown in FIG.

  In the fourth embodiment, for example, the NAND cell array block 49 described in the first embodiment is changed to a Virtual Ground cell array block 49 ′. The memory cell is the M-NO-S type EEPROM cell or the M-ONO-S type EEPROM cell described in the third embodiment.

  As shown in FIG. 25, a virtual ground cell array block 49 ′ is arranged in the memory cell array 1. The cell array block 49 ′ includes nonvolatile memories connected in parallel between the first data transfer lines BL (BL1a, BL2a,..., BL1k, BL2k) and the second data transfer lines BL (BL1a ′,..., BL1k ′). Contains cells. The second data transfer lines BL (BL1a ′,..., BL1k ′) function as source lines, for example.

  Other circuit configurations and circuit connections are the same as those in the configuration example of the cell array unit and the sense amplifier unit shown in FIG. 2, respectively, and thus the same reference numerals as those in FIG. See FIG. 2 and its description.

  FIG. 26 and FIG. 27 are cross-sectional views showing cross-sectional examples of the memory cell of the device according to the fourth embodiment. The cross section shown in FIG. 26 is, for example, a cross section along the row direction, similarly to the cross section shown in FIG. 5 of the first embodiment, and the cross section shown in FIG. 27 is the same as the cross section shown in FIG. It is a cross section that intersects the direction, for example, along the orthogonal column direction. Each of FIGS. 26 and 27 includes a cross section of two memory cells.

  As shown in FIGS. 26 and 27, the nonvolatile memory cell of the present embodiment is an M-NO-S type EEPROM cell or an M-ONO-S type EEPROM cell (hereinafter referred to as M-ONO-S type). Cell). The basic structure is the same as the memory cell described in the third embodiment. In particular, the difference is that the channel formation direction (corresponding to the channel length direction) of the memory cell coincides with the direction (row direction) in which the data selection lines 27 and 27 'extend.

  Furthermore, the memory cell of the present embodiment accumulates charges in the vicinity of the source electrode 28 and the vicinity of the drain electrode 28 and stores at least 2 bits of information per cell. Each of these 2-bit information can be read according to the direction of the voltage applied to the source electrode 28 and the drain electrode 28. Known examples of this method include, for example, US Pat. No. 6,201,202. When reading information by this method, the current terminal of the bit from which information is not read and the current terminal of the bit from which information is read are equivalent to being connected in series. Therefore, a read disturb stress similar to that of the NAND cell is applied to the bit on the side from which information is not read. Therefore, the bit on the side from which information is not read changes from the erased state to the written state when reading is repeated.

As shown in FIGS. 26 and 28, a first insulating film 25 is formed on the p-type silicon region 23. The p-type silicon region 23 contains boron or indium having an impurity concentration in the range of 10 ¹⁴ cm ⁻³ to 10 ¹⁹ cm ⁻³ . An example of the first insulating film 25 in the present embodiment is, for example, a silicon oxide film or a silicon oxynitride film having a thickness in the range of 0.5 nm to 10 nm. A charge storage layer 26 is formed on the first insulating film 25. An example of the charge storage layer 26 in the present embodiment is a silicon nitride film having a thickness of 3 nm to 50 nm, for example. A second insulating film (block insulating film) 50 is formed on the charge storage layer 26. An example of the second insulating film 50 in the present embodiment is a silicon oxide film, oxynitride film, Al ₂ O ₃ , ZrSiO, HfSiO, ZrSiON, or HfSiON having a thickness of 5 nm to 30 nm. Conductor layers 51 and 27 are formed on the second insulating film 50. Examples of the conductor layers 51 and 27 in the present embodiment are, for example, polysilicon layers. Specific examples of the polysilicon layer have a thickness in the range of, for example, 10 nm to 500 nm, and include, for example, boron, phosphorus, or arsenic in the range of 10 ¹⁹ cm ⁻³ to 10 ²¹ cm ⁻³ . The conductor layer 51 may be provided as necessary. Note that when the conductor layers 51 and 27 are polysilicon layers, the concentration of boron, phosphorus, or arsenic included in the polysilicon layer is preferably 10 ¹⁹ cm ⁻³ or more. Since the depletion of the control electrode can be prevented, the electric field applied to the ONO laminated film (second insulating film 50, charge storage layer 26, first insulating film 25) is increased, and the erasing time or writing time is increased. The advantage that it can be suppressed is obtained. On the conductor layer 27, a low resistance conductor layer 27 'is formed. Examples of the low resistance conductor layer 27 'are, for example, WSi, NiSi, MoSi, TiSi, CoSi, W, Al, or AlCu having a thickness in the range of 10 nm to 500 nm. The low resistance conductor layer 27 ′ may be provided as necessary. In the present embodiment, the conductor layers 51 and 27 constitute a control gate electrode, and the low resistance conductor layer 27 ′ lowers the resistance of the control gate electrode, that is, the data selection line. An insulating film 60 is formed on the low resistance conductor layer 27 '. An example of the insulating film 60 is, for example, a silicon nitride film or a silicon oxide film having a thickness in the range of 5 nm to 500 nm. The insulating film 60 functions as a mask when processing the gate electrode. The insulating film 60 may be provided as necessary.

  Side wall insulating films 19 are formed on both side walls of the gate electrode. The sidewall insulating film 19 in this embodiment is formed from both side walls of the conductor layer 51 along the row direction to the inside of the conductor layer 27. An example of the sidewall insulating film 19 is, for example, a silicon oxide film or a silicon oxynitride film. Further, when the conductor layer 51 is, for example, a conductor containing silicon, at least the surface in contact with the conductor layer 51 of the sidewall insulating film 19 in the present embodiment oxidizes or oxynitrides the conductor layer 51. It is formed by doing. Examples of the oxidation method and the oxynitridation method are thermal oxidation and thermal oxynitridation, respectively. The advantages of this are that the charge trap density is lower and the dielectric breakdown voltage is higher than that of a deposited film formed using a deposition method, for example, a CVD method. This is because the interface state density between them is lowered. As the sidewall insulating film 19, it is possible to use a thermal oxide film or a thermal oxynitride film having a higher quality than a deposited film formed by using a deposition method.

  As shown in FIG. 26, an example is shown in which the charge storage layer 26 in this embodiment is partially removed above the n-type source / drain region 28, and an interlayer insulating film 68 is formed in the removed portion. ing. In this embodiment, the charge storage layer 26 is an insulator. Therefore, it is not always necessary to partially remove the charge storage layer 26 above the n-type source / drain region 28. The charge storage layer 26 may be formed continuously.

  The memory cell according to the fourth embodiment can be formed by the following procedure, for example.

  First, for example, the n-type silicon region 22 is formed in the p-type silicon substrate 21, and the p-type silicon region 23 is formed in the n-type silicon region 22.

  Next, the first insulating film 25 is formed on the p-type silicon region 23, the charge storage layer 26 is formed on the first insulating film 25, and the second insulating film 50 is formed on the charge storage layer 26. The conductor layer 51, for example, the conductor layer 51 containing silicon is formed on the second insulating film 50.

  Next, the conductor layer 51, the second insulating film 50, the charge storage layer 26, and the first insulating film 25 are etched, for example, anisotropically etched, so that the conductor layer 51, the second insulating film 50, the charge The accumulation layer 26 and the first insulating film 25 are partially removed. As a result, a plurality of first linear structures each including the conductor layer 51, the second insulating film 50, the charge storage layer 26, and the first insulating film 25, which are longitudinal along the column direction (the front and back direction in the drawing). Is obtained on the p-type silicon region 23.

  Next, the surface of the conductor layer 51 is oxidized or oxynitrided, for example, thermally oxidized or thermally oxynitrided to obtain the sidewall insulating film 19 on the surface of the conductor layer 51.

Next, using the first linear structure as a mask, an n-type impurity such as phosphorus, arsenic, or antimony is in the p-type silicon region 23 and has a surface concentration in the range of 10 ¹⁷ cm ⁻³ to 10 ²¹ cm ⁻³ . Ion implantation is performed at a depth of 10 nm to 500 nm. Thereby, the n-type diffusion layer 28 is obtained in the p-type silicon region 23. The n-type diffusion layer 28 is a source region and a drain region of the memory cell.

  Next, an insulator such as silicon oxide, silicate glass, or inorganic glass is formed on the exposed surfaces of the first linear structure and the p-type silicon region 23 (n-type diffusion layer 28) to a thickness of 10 nm to 1000 nm. The interlayer insulating film 68 is obtained by depositing in the range.

  Next, the upper surface of the interlayer insulating film 68 is etched back, for example, CMP (Chemical Mechanical Polishing), and the upper surface of the interlayer insulating film 68 is planarized.

  Next, the sidewall insulating film 19 existing on the upper surface of the conductor layer 51 is removed, for example, wet etching is performed using an ammonium fluoride solution or the like, and the upper surface of the conductor layer 51 is exposed.

Next, a conductor, for example, conductive polysilicon or SiGe mixed crystal is deposited on the conductor layer 51 and the interlayer insulating film 68 in a thickness range of 10 nm to 300 nm to obtain the conductor layer 27. When the conductive layer 27 contains a conductive impurity such as boron, phosphorus, or arsenic, if the concentration is 1 × 10 ¹⁹ cm ⁻³ or more, as described above, the ONO laminated film (second insulating film) The electric field applied to the film 50, the charge storage layer 26, and the first insulating film 25) is increased, and an increase in erasing time or writing time can be suppressed.

  Next, a conductor having a lower resistance than that of the conductor layer 27, for example, WSi, NiSi, MoSi, TiSi, CoSi, W, Al, or AlCu is deposited on the conductor layer 27, and a low resistance conductor layer 27 ′ is formed. obtain.

  Next, a mask material, for example, silicon nitride or silicon oxide is deposited on the low-resistance conductor layer 27 ′ to obtain the insulating film 60.

  Next, the insulating film 60, the low-resistance conductor layer 27 ', the conductor layer 27, the conductor layer 51, the sidewall insulating film 19, the second insulating film 50, the charge storage layer 26, and the first insulating film 25 are etched. For example, anisotropic etching is performed, and these are partially removed. As a result, the insulating film 60, the low-resistance conductor layer 27 ′, the conductor layer 27, the conductor layer 51, the sidewall insulating film 19, and the second insulating film 50, which are long in the row direction (left and right direction on the paper surface), are formed. A plurality of second linear structures each including the charge storage layer 26 and the first insulating film 25 are obtained on the p-type silicon region 23. In this step, the memory cells are separated one by one along the row direction and the column direction.

Next, using the second linear structure as a mask, a p-type impurity such as boron, boron fluoride (BF ₂ ), or indium is introduced into the p-type silicon region 23 from a surface concentration of 10 ¹⁶ cm ^−3. Ion implantation is performed at a depth of 10 nm to 500 nm so as to be in the range of 10 ¹⁸ cm ⁻³ . As a result, a high-concentration p-type diffusion layer 18 having a higher concentration than the p-type silicon region 23 is obtained in the p-type silicon region 23. The high-concentration p-type diffusion layer 18 is a layer that reduces a leak current flowing between the channels of memory cells adjacent in the column direction. The high concentration p-type diffusion layer 18 may be provided as necessary.

  Next, an insulator such as silicon nitride, silicon oxynitride, or alumina is applied to the exposed surfaces of the second linear structure and the p-type silicon region 23 (n-type diffusion layer 28, high-concentration p-type diffusion layer 18). The insulating film 61 is obtained by depositing in a thickness range of 5 nm to 200 nm. The insulating film 61 is a deposited insulating film formed by using, for example, a CVD (Chemical Vapor Deposition) method or a sputtering method. When such an insulating film 61 is deposited on the memory cell, for example, on all the memory cells or on the entire surface of the memory cell array, gas, radicals or ions from the film formed above the insulating film 61 are deposited. However, there is an advantage that the adverse effect on the memory cell can be suppressed.

Next, silicate glass, for example, BPSG, PSG, or BSG is deposited on the insulating film 61 in a thickness range of 10 nm to 1000 nm to obtain an interlayer insulating film 62. BPSG, PSG, and BSG contain, for example, boron and phosphorus in an amount of 1 × 10 ²⁰ cm ⁻³ or more. Silicate glass has a function of gettering alkali ions. Therefore, when the interlayer insulating film 62 is formed and deposited on a memory cell, for example, on all memory cells or the entire surface of the memory cell array, there is an advantage that contamination by alkali ions can be suppressed.

  In the present embodiment, the interlayer insulating film 62 is formed in direct contact with the insulating film 61, but it is not necessarily formed in contact therewith. For example, even if the interlayer insulating film 62 is formed as an insulating film between wiring layers or an insulating film on the wiring layer, there is no problem because it has a gettering effect.

  Silicate glass generally has poor embedding properties immediately after deposition. For this reason, after deposition, for example, when annealing is performed in the range of 750 to 1000 ° C. for 2 to 120 minutes, viscous flow occurs and the surface becomes flat. During annealing, moisture or hydronium ions contained in the silicate glass are released. For example, moisture oxidizes the gate end of the memory cell. For this reason, for example, the film thickness of the second insulating film 50 increases, and the gate shape changes. However, when the insulating film 61 is formed, for example, moisture is shielded, so that an advantage that the change in the gate shape can be suppressed can be obtained.

  As the interlayer insulating film 62, for example, an inorganic glass formed using cyclopentasilane or polysilazane may be used. In this case, an oxidation step is required to convert cyclopentasilane or polysilazane into inorganic glass. The oxidant changes the gate shape like moisture. However, when the insulating film 61 is formed, for example, since the oxidant is shielded, there is an advantage that the change in the gate shape can be suppressed. As described above, forming the insulating film 61 is advantageous, for example, when fine memory cells are integrated.

  For the interlayer insulating film 62, for example, a silicon oxide film formed using TEOS or HDP, or a laminated structure with another insulating film such as HSQ may be used.

  Next, the upper wiring 36 is formed on the interlayer insulating film 62. The upper wiring 36 is various wiring provided in the semiconductor integrated circuit device. The upper wiring 36 varies in various ways, for example, depending on the application of the semiconductor integrated circuit device. Therefore, in the present embodiment, a specific shape of the upper wiring 36 is omitted, and only the upper wiring 36 is formed on the interlayer insulating film 62 is illustrated. For example, in FIG. 26 and FIG. 27, the upper wiring 36 is shown as if "one plate". Although the upper wiring 36 shows only one layer, it is of course possible to have a multilayer wiring structure of two or more layers.

  Next, an insulator, for example, silicon oxide formed using TEOS or HDP, or HSQ is deposited, and an interlayer insulating film 37 is obtained on the upper wiring 36 and the interlayer insulating film 62.

  Next, silicon nitride is deposited on the interlayer insulating film 37 in a thickness range of 20 nm to 1 μm using, for example, plasma chemical vapor deposition to obtain a silicon nitride film layer 37 ′. The silicon nitride film layer 37 ′ has a function of blocking moisture diffused from the outside of the chip (the upper surface of the semiconductor integrated circuit device).

  According to the fourth embodiment, there are the following requirements and effects in addition to the requirements and effects of the above embodiment.

  (12) The conductor layer (control gate) 27 intersects, for example, a direction orthogonal to the direction in which the n-type diffusion layer (source region and drain region) 28 is formed (column direction, front and back direction in FIG. 26) ( It is formed in the row direction (left and right direction in FIG. 26). The memory cells are connected in parallel between the n-type diffusion layers (source region and drain region) 28. As an EEPROM having such a connection state, for example, there is a virtual ground array type. In a semiconductor memory in which memory cells are connected in parallel between n-type diffusion layers 28, the series resistance of the memory cell block can be made small and constant. Therefore, it is advantageous for stabilizing the threshold value of the memory cell, and is useful for, for example, a multi-value storage memory having a narrow threshold distribution width.

  Further, the interlayer insulating film (element isolation region) 68 and the n-type diffusion layer 28 are each formed in a self-aligned manner with respect to the charge storage layer 26. The interlayer insulating film 68 and the n-type diffusion layer 28 do not need to ensure a misalignment margin with respect to the charge storage layer 26, respectively. The interlayer insulating film 68 is formed on the n-type diffusion layer 28. Therefore, the memory cells can be integrated at a higher density than a semiconductor memory in which element isolation regions are provided between memory cells and a semiconductor memory in which the charge storage layer 26 is provided on the element isolation regions.

  Note that requirements and effects of a memory cell array of a semiconductor memory in which memory cells are connected in parallel between n-type diffusion layers are described in, for example, Japanese Patent Application Laid-Open No. 2002-150783, which is a prior application by the present inventor.

  (13) The memory cell is an M-ONO-S type cell. Therefore, similarly to the third embodiment, the writing voltage and the erasing voltage can be made lower than those of the floating gate type cell, the element isolation interval can be narrowed, and a sufficient withstand voltage can be maintained even if the gate insulating film is thinned. For this reason, the area of the circuit to which the high voltage is applied can be reduced, and the chip area can be easily reduced.

  Similar to the third embodiment, since the thickness of the charge storage layer 26 can be reduced, the aspect ratio of the gate structure can be reduced as compared with the floating gate type cell, and the workability of the gate structure is good. Interlayer insulating film 68 has good embeddability between gate structures and good withstand voltage.

  As in the third embodiment, the process for forming the floating gate can be omitted or simplified as compared with the floating gate type cell, so that the manufacturing process time is shortened.

  Similar to the third embodiment, since charges are trapped in the charge trap, the charge retention characteristic is better than that of the floating gate type cell. For example, strong resistance to radiation can be obtained.

  As mentioned above, although this invention was demonstrated by some embodiment, this invention is not limited to some embodiment, In the implementation, it can change variously in the range which does not deviate from the summary of invention. It is.

  For example, as a method of forming an element isolation region and an insulating film such as an interlayer insulating film, for example, a method other than converting silicon into a silicon oxide film or a silicon nitride film can be used. For example, a method of injecting oxygen ions into the deposited silicon or a method of oxidizing the deposited silicon may be used.

The charge storage layer 26 may use TiO ₂ , Al ₂ O ₃ , a tantalum oxide film, strontium titanate, barium titanate, and lead zirconium titanate. Alternatively, a stacked film in which these materials are stacked may be used.

  The semiconductor substrate is not limited to p-type silicon, and may be any substrate including silicon, for example, a single crystal substrate, such as n-type silicon, an SOI silicon layer on an SOI substrate, a SiGe mixed crystal, or a SiGeC mixed crystal. Of course, it is possible to use other than silicon as the semiconductor.

  As a memory cell, an n-channel MOSFET (n-channel floating gate cell, n-channel M-NO-S cell, n-channel M-ONO-S cell) is used, but a p-channel MOSFET (p A channel type floating gate cell, a p channel type M-NO-S type cell, a p channel type M-ONO-S type cell) may be used. In this case, the conductivity type of each semiconductor region in the above embodiment may be read from n-type to p-type and from p-type to n-type. Furthermore, any of arsenic, phosphorus, and antimony may be read as either indium or boron as the conductive impurity.

  The conductor layers (control gates) 27 and 51 can use Si semiconductor, SiGe mixed crystal and SiGeC mixed crystal, and may have a stacked structure in which these materials are stacked. These materials may be polycrystalline, amorphous, or single crystal. It is also possible to stack layers having different crystallinity of polycrystalline, amorphous and single crystal. When the conductor layers (control gates) 27 and 51 are semiconductors, particularly when they are semiconductors containing silicon, for example, as described in the fourth embodiment, a favorable sidewall insulating film 19 can be obtained. . This is because the sidewall insulating film 19 can be formed by oxidizing or oxynitriding a semiconductor containing silicon.

  The charge storage layer 26 may be separated between the source region side and the drain region, or may be formed in a dot shape.

  The low-resistance conductor layer 27 'reacts with, for example, a metal such as Ti, Co, Ni, Mo, Pd, and Pt and a conductor layer 27, for example, a conductor layer 27 containing silicon, to form silicide. May be used as the low-resistance conductor layer 27 '.

In the above-described embodiment, an example in which a memory cell that stores two values is used is shown. However, a memory cell that stores three or more digital values as a plurality of threshold values may be used. This is a so-called multilevel memory. Compared to a binary memory, a multi-value memory has a narrow threshold distribution width corresponding to each information, and a separation interval between threshold distributions is also narrow. For this reason, a multi-level memory is more likely to generate defective bits than a binary memory. That is, the advantage of the above embodiment can be obtained more effectively in a multi-level memory. Therefore, the above embodiment is useful for a multi-level memory. Further, if the number of information stored in one memory cell is 2 ⁿ values, there is an advantage that decoding of information data can be simplified.

  In the above embodiment, an example of a nonvolatile semiconductor memory has been described. However, a memory cell block having a data selection line shared by memory cells, in which data is read in parallel by the data selection line, and data read in parallel The above embodiment can be applied to any semiconductor memory having a circuit for correcting error bits by ECC and a spare memory cell block having a data selection line shared by memory cells. In this case, it is sufficient to consider the case where error bits are caused by, for example, aging, electro-migration, corrosion, etc., and it is clear that the error bit rate can be greatly improved. Thus, for example, any memory cell such as a DRAM cell, SRAM cell, FeRAM cell, or MRAM cell can be used as the memory cell.

  Moreover, although each embodiment can be implemented independently, it can also be implemented in combination as appropriate.

  Each embodiment includes inventions at various stages, and inventions at various stages can be extracted by appropriately combining a plurality of constituent elements disclosed in each embodiment.

  Each embodiment has been described based on an example in which the present invention is applied to a semiconductor memory. However, the present invention is not limited to a semiconductor memory, and a semiconductor integrated circuit device incorporating a semiconductor memory, such as a processor or a system LSI. Etc. are also within the scope of this invention.

  As described above, according to the embodiment, the defect rate viewed from the external interface can be significantly reduced without increasing the number of inspection bits of the ECC circuit. In particular, by preparing a certain number or more of spare areas in advance as spare storage areas, it is possible to drastically suppress the defect rate viewed from the external interface while guaranteeing a data storage area that can be used by the user to the life end. .

FIG. 1 is a block diagram showing a configuration example of a data storage system according to the first embodiment of the present invention. FIG. 2 is a block diagram showing a configuration example of the cell array unit and the sense amplifier unit of the data storage system according to the first embodiment of the present invention. FIG. 3 is an equivalent circuit diagram showing an example of an equivalent circuit of the memory cell block 49 shown in FIG. 4 is a plan view showing a plane pattern example of the memory cell block 49 shown in FIG. 5 is a cross-sectional view taken along the line VV in FIG. 6 is a sectional view taken along line VI-VI in FIG. FIG. 7 is a block diagram showing a configuration example of the ECC circuit 100 shown in FIG. FIG. 8 is a circuit diagram showing a circuit example of the encoder 14 shown in FIG. FIG. 9 is a circuit diagram showing a circuit example of the decoder (syndrome calculator) 15 shown in FIG. FIG. 10 is a circuit diagram showing a circuit example of the decoder (syndrome calculator) 15 shown in FIG. FIG. 11 is a flowchart showing an example of replacement operation of the data storage system according to the first embodiment of the present invention. FIG. 12 is a diagram showing an example of block address assignment in the data storage system according to the first embodiment of the present invention. FIG. 13 is a diagram showing the elements of the Galois field FIG. 14 is a flowchart showing an example of block selection operation of the data storage system according to the first embodiment of the present invention. FIG. 15 is a flowchart showing an example of replacement operation of the data storage system according to the first embodiment of the present invention. 16 is a circuit diagram showing a circuit example of the page buffer 11 shown in FIG. FIG. 17 is an operation waveform diagram showing an operation example of the page buffer 11 shown in FIG. FIG. 18 is a block diagram showing a configuration example of the ECC circuit 100 provided in the data storage system according to the second embodiment of the present invention. FIG. 19 is a flowchart showing a replacement operation example of the data storage system according to the second embodiment of the present invention. FIG. 20 is a diagram showing an example of a correspondence table between syndrome inputs and error position locator outputs used in the data storage system according to the second embodiment of the present invention. FIG. 21 is a block diagram showing a configuration example of the ECC circuit 100 included in the data storage system according to the modification of the second embodiment of the present invention. FIG. 22 is a diagram showing an example of a correspondence table between syndrome inputs and error position locator outputs used in the data storage system according to the modification of the second embodiment of the present invention. FIG. 23 is a cross-sectional view showing a cross-sectional example along the row direction of the memory cell included in the data storage system according to the third embodiment of the present invention. FIG. 24 is a cross-sectional view showing a cross-sectional example along the column direction of the memory cell included in the data storage system according to the third embodiment of the present invention. FIG. 25 is a block diagram showing a configuration example of a cell array unit and a sense amplifier unit of a data storage system according to the fourth embodiment of the present invention. FIG. 26 is a cross-sectional view showing a cross-sectional example along the row direction of the memory cell included in the data storage system according to the fourth embodiment of the present invention. FIG. 27 is a cross-sectional view showing a cross-sectional example along the column direction of the memory cell included in the data storage system according to the fourth embodiment of the present invention.

Explanation of symbols

  1n ... Non-spare area, 1s ... Spare area, 5 ... Error bit detection circuit, 6 ... Error bit number determination circuit, 49, 49 '... Memory cell block, 100 ... ECC circuit

Claims (4)

A non-spare area having a plurality of memory cell blocks and including pages connected to some of the memory cell blocks;
A spare area including a plurality of spare memory cell blocks in which data is pre-arranged to a certain value and including pages connected to some of these spare memory cell blocks;
File Allocation Tabl that has a plurality of memory cell blocks, includes pages connected to some of these memory cell blocks, and stores the block address of the non-spare area
e region,
A determination circuit that detects a data error of at least 2 bits when data is read from a page in the non-spare area and determines the number of error bits in the read page for each read page;
When the determination result by the determination circuit is 2 bits or more, the content of the read page is error-corrected and written to the page in the spare area. The block address of the spare area has a write status bit greater than an erase status bit. If the logical value of the write state is defined as “1” and the logical value of the erase state is defined as “0”, the logical inversion of the block address of the non-spare area and the block address of the spare area are defined. When the logical value of the result does not include any “0”, the block address of the spare area is added to the block address of the non-spare area recorded in the File Allocation Table area.
The data storage system is characterized in that the bit of “ 0” is changed to “1” by additionally writing to the memory and no erasure is required.
A non-spare area having a plurality of memory cell blocks and including pages connected to some of the memory cell blocks;
A spare area including a plurality of spare memory cell blocks in which data is pre-arranged to a certain value and including pages connected to some of these spare memory cell blocks;
File Allocation Tabl that has a plurality of memory cell blocks, includes pages connected to some of these memory cell blocks, and stores the block address of the non-spare area
e region,
A determination circuit that detects a data error of at least 2 bits when data is read from a page in the non-spare area and determines the number of error bits in the read page for each read page;
When the determination result by the determination circuit is 2 bits or more, the content of the read page is error-corrected and written to the page in the spare area. The block address of the spare area has a write status bit greater than an erase status bit. If the logical value of the write state is defined as “1” and the logical value of the erase state is defined as “0”, the logical inversion of the block address of the non-spare area and the block address of the spare area are defined. When the logical value of the result does not include any “0”, the block address of the spare area is added to the block address of the non-spare area recorded in the File Allocation Table area.
A data storage system that changes the bit of “ 0” to “1” by additionally writing a memory and does not require erasure,
The number of information bits per page is n, the maximum number of bits that can be error-corrected in one page is t, and m is {2 ^m−1 −t × (m−1) −1} <n ≦ (2 ^m −t × m−1) When a natural number satisfying is satisfied,
A data storage system, wherein the number of memory cells in one page is (n + t × m) or more.
A non-spare area having a plurality of memory cell blocks and including pages connected to some of the memory cell blocks;
A spare area including a plurality of spare memory cell blocks in which data is pre-arranged to a certain value and including pages connected to some of these spare memory cell blocks;
File Allocation Tabl that has a plurality of memory cell blocks, includes pages connected to some of these memory cell blocks, and stores the block address of the non-spare area
e region,
A determination circuit that detects a data error of at least 2 bits when data is read from a page in the non-spare area and determines the number of error bits in the read page for each read page;
When the determination result by the determination circuit is 2 bits or more, the content of the read page is error-corrected and written to the page in the spare area. The block address of the spare area has a write status bit greater than an erase status bit. If the logical value of the write state is defined as “1” and the logical value of the erase state is defined as “0”, the logical inversion of the block address of the non-spare area and the block address of the spare area are defined. When the logical value of the result does not include any “0”, the block address of the spare area is added to the block address of the non-spare area recorded in the File Allocation Table area.
A data storage system that changes the bit of “ 0” to “1” by additionally writing a memory and does not require erasure,
The data storage system, wherein the non-spare area and the spare area are simultaneously erased on a plurality of pages.
When the block address of the spare area is class i (i is the number of “0” of the block address of the spare area), the block address of the spare area of the class having a small i is selectively selected in the non-spare area. The data storage system according to any one of claims 1 to 3, wherein logical inversion and operation of a block address are performed.

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