KR100946177B1 - Apparatus and method transmitting - receivering data - Google Patents

Abstract

The present invention relates to an apparatus and method for transmitting and receiving data, wherein the transmitter has a value equal to 1 from the LSB when the MSB of the parallel data is 0, and when the MSB is 1, the parallel data excluding the MSB is excluded from the LSB. An encoding unit for transition coding the number of transitions to be 0 or 1 by having a value equal to zero, the receiver adds the number of 1s in the coded data when the MSB of the transition coded data is 0, and the MSB is 1 Is a decoding unit that decodes the number of 1s from the coded data by taking a minus (-) in 2's complement, and the data transition is performed only once when serializing and transmitting N-bit parallel data. By coding to occur, low power data transmission is possible by reducing the number of data transitions that occur during data transmission. In addition, data serialization effects reduce the number of links required for data transmission.

Transmitter, Receiver, Bus Coding, OST Coding

Description

Device for transmitting and receiving data {APPARATUS AND METHOD TRANSMITTING-RECEIVERING DATA}

The present invention relates to an apparatus and method for transmitting and receiving data, and in particular, to code low-speed data by reducing the number of data transitions that occur during data transmission by coding data transitions to occur only once in serial transmission. The present invention relates to a data transmission / reception apparatus capable of reducing the number of links required for data transmission.

Conventional on-chip or off-chip parallel communication requires a large number of wires, and due to problems such as crosstalk and delay differences between wires, wired communication between electrical products, Internet communication between computers, and communication between functional blocks within the chip Serial communication has been widely used.

On the other hand, in recent years, as the performance of transistors improves, the performance of the link wires is smaller than that of the transistors.

In addition, as the degree of integration in the SoC increases, the number of modules to be integrated increases, and communication between modules becomes important, and the necessary links thereof become more and more complicated. Therefore, resources consumed by the link and power consumed are problematic.

One of the countermeasures is that bus invert coding, gray coding, and T0 coding reduce the number of transitions of data in order to efficiently transmit transmission of parallel data having a large number of bits in the past. Bus coding methods such as the above have been used a lot.

In another aspect, a bus serialization technique is also used in which time-splitting parallel data is converted to serial data in order to reduce wire link resources consumed in transmitting a large number of bits of parallel data.

Therefore, in order to solve the above problems, the present invention proposes a data transmission / reception apparatus including a coding method for reducing the number of transitions in the process of serializing parallel data, thereby enabling efficient data transmission by simultaneously realizing serialization and low power consumption. It is an object of the present invention to provide an apparatus and method for transmitting and receiving data.

In order to achieve the above technical problem, the present invention comprises a transmitter for serializing and transmitting parallel data, a serial link unit for transmitting serialized data, and a receiver for converting serialized data into parallel data. When the MSB of the parallel data is 0, the transmitter has 1 as the parallel data value from LSB (), and when the MSB is 1, the transmitter has 0 as the parallel data value except the MSB from the LSB. And an encoding unit for transition coding to be 0 or 1, wherein the receiver adds 1 to the coded data when the MSB of the transition coded data is 0, and adds 1 to the coded data when the MSB is 1 And a decoding unit that decodes the sum of the number of times by taking a minus (-) in two's complement. The.

The transmitter may include NMOS dynamic logic in which the coded data is input and serialized when the data coded by the encoding unit is changed from 0 to 1, and the coded data is input when the coded data is changed from 1 to 0. And may further include PMOS dynamic logic that is serialized.

The decoding unit may include a CSA (CARRY SAVE ADDER) configured of a plurality of full adders and a half adder to calculate the number of 1s of coded serial data.

In the data transmission / reception method of converting parallel data into serial data and transmitting / receiving, before serialization, if the MSB of parallel data is 0, the LSB has 1 as much as the parallel data value, and if the MSB is 1, the LSB. Transition coded the number of transitions to be 0 or 1 by having a value equal to 0 of parallel data except for MSB, and after receiving and parallelizing serial data, the MSB of the transition coded data is coded. When the number of 1s is added to the data and the MSB is 1, it is preferable to decode the number obtained by adding the number of 1s in the coded data by taking a minus (−) in two's complement.

According to the data transmission and reception apparatus and method according to the present invention as described above, by coding so that the data transition occurs only once when serializing and transmitting N-bit parallel data, the number of data transitions generated during data transmission In other words, low power data transmission is possible, and the data serialization effect reduces the number of links required for data transmission.

Hereinafter, a data transmitting and receiving device and method configured as described above will be described in detail with reference to the accompanying drawings.

1 is a block diagram showing the overall configuration of a data transmission and reception apparatus according to the present invention, Figure 2 is a table showing an OST coding table for N-bit data according to an embodiment of the present invention, Figure 3 according to the present invention 4 is a circuit diagram illustrating an NMOS dynamic logic constituting a transmitter of a data transceiver, and FIG. 4 is a circuit diagram illustrating PMOS dynamic logic constituting a transmitter of a data transceiver according to the present invention, and FIG. 5 is a diagram of a data transceiver according to the present invention. 6 is a block diagram showing the configuration of a transmitter, and FIG. 6 is a diagram showing the configuration of a decoding unit of a data transceiver according to the present invention.

As shown in FIG. 1, the apparatus for transmitting and receiving data according to the present invention includes a serial link unit 200 carrying serialized data with an encoding unit 110 of a transmitter 100 for sending parallel data and a receiver for parallelizing serialized data again. And a decoding unit 310 of 300.

Here, the transmitter 100 may include NMOS dynamic logic in which the coded data is input and serialized when the data coded by the encoding unit 110 changes from 0 to 1, and the coded data may change from 1 to 0. And further includes PMOS dynamic logic to input and serialize the coded data (see FIGS. 3 and 4).

In addition, the decoding unit 310 constituting the receiver 300 is a Carry Save Adder (CSA) consisting of a plurality of full adders and half adders to calculate the number of 1s of coded serial data. It converts the serial data into parallel data including (see FIG. 6).

On the other hand, assuming that N parallel data is serialized, the possible combinations of 0 and 1 may be 2 ^N , where the expected value of the number of transitions of the serialized data is 0.5 * N. When the next bit is serialized, it is easy to see that the expected value is 0.5 * N because the probability that the value will be maintained is 0.5 and the probability that it will change is 0.5.)

Accordingly, in order to reduce the number of transitions in the serialized data, the present invention codes the number of transitions to be 0 or 1, and hereinafter referred to as OST (Only Single Transition) coding.

As shown in FIG. 2, when describing the OST coding table for N-bit data according to an embodiment of the present invention, in order for the number of transitions to be 0 or 1, only once when serialization starts with 0 There is an opportunity to transition to. That is, if 0000, 0001, 0011, and 0111 are transitioned to 1 once, the next keeps 1.

On the contrary, when serialization starts with 1, transitions to 0 are performed once, such as 1111, 1110, 1100, and 1000. Therefore, the OST coding value obtained as a result of the coding according to the table of FIG. 2 is transitioned 0 or 1 in any case.

When the N-bit data Most Significant Bit (MSB) value is 0, the value obtained after OST coding starts with 0 and ends with 1 (if the input is 00 ... 00, it starts with 00..00 Equal to 0), the number of 1s from the Least Significant Bit (LSB) is equal to the value of the N bit data.

Conversely, if the N-bit data MSB value is 1, the OST coded value starts with 1 and ends with 0 (if the input is 10 ... 00, 11 ... 11 starts, the end is equal to 1) LSB The number of 0s is equal to the value of N-1 bits except for the MSB, which is a bit wrapped in N bits (or the number of 1s from the MSB is equal to the absolute value of N-bit data in two's complement).

If OST coding is performed in this manner, the number of possible combinations is 2 * M, assuming that the number of bits of the OST coded number is M. Therefore, in order to express 2 ^N , which is the number of all combinations that can be represented by the number of N bits, the following equations (1) and (2) must be established between N and M.

2 ^N = 2 * M (1)

M = 2^N-1 (2)

That is, the number of bits increases through OST coding. That is, when N = 3, M = 4, and when N = 4, M = 8.

To explain the above description in more detail, the average number of transitions is obtained when sending N-bit data and sending it after OST coding.

First of all, as mentioned above, the expected number of transitions when sending N-bit data is 0.5 * N.

In the case of OST coding, when the N: 1 coding is performed, the transition is 0 when the transition is 0 and the 2 is when the transition is ^2N . That is, the expected value is 0 * (2/2 ^N ) + 1 * (2 ^N -2) / 2 ^N = 1-1/2 ^N-1 . Considering the next N: 1 OST coding in this state, the next coding value is 0 or 1, so the transition code is 0 * 0.5 + 1 * 0.5 = 0.5 because it is independent of this coding. Therefore, the expected value of OST coding is (3/2-1/2 ^N-1 ) Becomes

If the ratio of the number of transitions of a normal transmission and a transmission after OST coding is obtained, Equation (3)

(3)

(3)

Is given by In other words, when N becomes large enough, the expected value of the transition after OST coding converges to 1.5, while in general, it becomes 0.5 * N, and the ratio approaches zero.

However, after OST coding, it is difficult to use for large N because the number of bits increases to 2 ^{N- 1} . The following table [1] summarizes the number of bits M and the degree of transition reduction in% when OST coding is applied to main N.

Table 1

N (length of data to serialize) M (data length after OST coding) Transition Reduction (%) 3 4 -16.7% 4 8 -31.25% 5 16 -42.5%

As N increases, M becomes twice as large, and it can be seen that actual implementation of N = 6 or more is difficult. However, even when N = 4, we can see that the number of transitions is reduced by 31.25%, which reduces the wire resources used by 1/4 by serializing 4: 1 serialization, while simultaneously consuming 31.25 of the power consumed by the link during data transmission. There is a significant effect that can be reduced by%.

Hereinafter, an implementation circuit for configuring a transmitter and a receiver for implementing OST coding that can simultaneously reduce the number of link resources and power consumption as described above will be described.

In general, since the bit widths of the parallel data to be mainly transmitted are 8, 16, 32, and the like, an embodiment of the case where N = 4 which is good to divide these numbers will be considered.

Referring to FIG. 2 described above, in the case where N is 4, the OST coding table is shown in the following table [2].

[Table 2]

N ([D3: D0]) OST coding ([O7: O0] 0000 00000000 0001 00000001 0010 00000011 0011 00000111 0100 00001111 0101 00011111 0110 00111111 0111 01111111 1000 11111111 1001 11111110 1010 11111100 1011 11111000 1100 11110000 1101 11100000 1110 11000000 1111 10000000

Thus, each bit of OST coded data can be obtained from the input data in a simple combination circuit, as follows. (Input data D3, D2, D1, D0-> OST data O7, O6, O5, O4, O3, O2, O1, O0 / D3, O7-MSB / D0, O0-LSB)

O7 = D3

(D2 · D1 · D0)O6 = D3

(D2D1D0)

(D2 · D1)O5 = D3

(D2D1)

(D2 · (D1 + D0))O4 = D3

(D2 (D1 + D0))

D2O3 = D3

D2

(D2 + D1 · D0)O2 = D3

(D2 + D1D0)

(D2 + D1)O1 = D3

(D2 + D1)

(D2 + D1 + D0)O0 = D3

(D2 + D1 + D0)

After OST coding, you need to replace this with serialized data. By focusing on OST coding taking only one transition, we can use a dynamic circuit that enables fast operation.

3 is a circuit diagram illustrating an NMOS dynamic logic constituting a transmitter of a data transceiver according to an embodiment of the present invention, in which a MSB is 0, that is, a serial conversion circuit for a case where an OST coded data changes from 0 to 1 once. Is showing.

Each OST coded data bit enters the NOR-connected transistor 120 of the dynamic circuit at regular time intervals from MSB to LSB by STR signals activated 0-> 1 at regular time intervals. That is, if any OST coding bit is 1, the precharged node will drop to 0, and continue to be 0 regardless of incoming input thereafter.

For example, if the OST coding input enters 0,0,1,1 at regular time intervals through the STR signal and the AND gate 130, the node that was precharged becomes 0 from the first time 1 is input. 1-> 1-> 0-> 0.

By inverting this signal, the serialized output will be 0-> 0-> 1-> 1 over time, which is the desired output signal. In other words, the OST coding is changed only once from 0 to> 1 using dynamic logic that can pull a node precharged with 1 to 0 only once.

If the input changes to 0,1,0,1 because of no OST coding, it cannot be implemented with dynamic circuits.

However, if the MSB is 1, the circuit must be complementary with FIG.

This is NMOS dynamic logic where FIG. 3 is precharged to 1 and the first 1 of the OST coding bits pulls the output to 0, as shown in FIG. 4, while FIG. 4 is precharged to 0 and the OST coding bits. You can see that the first zero consists of PMOS dynamic logic that pulls the output to 1.

As shown in FIG. 5, in order to configure the entire transmitter of the data transceiver according to the present invention, both the above-described circuits of FIGS. 3 and 4 are required, and the final output is determined by the MSB bit.

Here, the transmitter selects an output value of the NMOS dynamic logic 160 or the PMOS dynamic logic 170 shown in FIGS. 3 and 4 by a multiplexer (MUX.) 180 whose operation is controlled by the MSB signal.

In addition, serial data is transmitted using a latch circuit 190 to time division the selected output value and prevent a transition in the precharge period.

On the other hand, the serial data transmitted from the transmitter is converted again in parallel in the receiver (receiver, 300).

Parallel conversion uses the strobe signal STR transmitted together with the serialized data. In the serial conversion circuit, signals STR1, STR2, ..., STR7, and STR8 are sequentially activated based on the STR signal, and accordingly, OST coded O7 and O6. Since, ..., O1, O0 signals are transmitted, STR1, STR2, which informs timing information of O7, O6, ..., O1, O0 signals as long as the STR signal is also transmitted in the parallel conversion circuit. You can obtain the .., STR7, and STR8 signals.

The strobe signals can be used to obtain parallel data O7, O6, ..., O1, O0 from the serialized data. The parallelized OST coded signal must be decoded back into the original signal, and this process uses the number of 1s of the OST coded signal.

As seen in the above coding process, when the MSB is 0, the original data is equal to the number of 1s in the OST coding data. In contrast, when the MSB is 1, the original data is the same as adding-(in the two's complement number system) to the number of 1s in the OST coded data. That is, after inverting a number indicating the number of OST-coded data 1, it becomes equal to 1 plus.

6 is a block diagram of a decoding unit of a data transceiver according to an embodiment of the present invention, in which a full adder 320 and a half adder 330 are used to count the number of 1s of the OST coded data. Adder, 340).

That is, when the MSB of the transition coded data is 0 using the number of 1s counted through the CSA 340, the number of 1s is added to the coded data, and when the MSB is 1, the number of 1s in the coded data. By taking the number plus minus two's complement, it converts the original data into parallel data and outputs it.

In addition, the method for transmitting and receiving data by the data transmission / reception device configured as described above, first, if the MSB of the parallel data is 0 before serialization, has 1 as the value of the parallel data from the LSB, and if the MSB is 1, Transition coding is performed so that the number of transitions is 0 or 1 by having 0 as parallel data values except for the MSB from the LSB.

After receiving and parallelizing serial data, when the MSB of the transition coded data is 0, the number of 1s is added to the coded data, and when the MSB is 1, the number of 1s is added to the coded data. Decode by taking minus (-) from the complement of.

Accordingly, the present invention proposes a coding method that reduces the number of transitions in the serial data serialization process, thereby realizing serialization and low power consumption, thereby enabling efficient data transmission.

As described above, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features. Therefore, the exemplary embodiments described above are to be understood as illustrative and not restrictive in all respects, and the scope of the present invention is indicated by the following claims rather than the detailed description, and the meaning and scope of the claims and All changes or modifications derived from the equivalent concept should be interpreted as being included in the scope of the present invention.

1 is a block diagram showing the overall configuration of a data transmission and reception apparatus according to the present invention;

2 is a table showing an OST coding table for N-bit data according to an embodiment of the present invention;

3 is a circuit diagram showing an NMOS dynamic logic constituting a transmitter of a data transmitting and receiving device according to the present invention;

4 is a circuit diagram showing PMOS dynamic logic constituting a transmitter of a data transmitting and receiving device according to the present invention;

5 is a block diagram showing the configuration of a transmitter of a data transmitting and receiving device according to the present invention;

6 is a diagram showing the configuration of a decoding unit of a data transmitting and receiving apparatus according to the present invention.

Claims (4)

In the data transmitting and receiving device comprising a transmitter for serializing and transmitting parallel data, a serial link unit for transmitting serialized data, and a receiver for converting serialized data into parallel data, When the MSB of the parallel data is 0, the transmitter has 1 as the parallel data value from the LSB. When the MSB is 1, the transmitter has 0 as the parallel data value excluding the MSB from the LSB. An encoding unit for transition coding to be 0 or 1, The receiver adds the number of 1s in the coded data when the MSB of the transition coded data is 0, and adds the number of 1s in the coded data when the MSB is 1 and adds the number of 1s in the two's complement. A decoding unit for decoding by taking The transmitter may include NMOS dynamic logic in which the coded data is input and serialized when the data coded by the encoding unit is changed from 0 to 1, and the coded data is input when the coded data is changed from 1 to 0. Further comprising PMOS dynamic logic to be serialized. delete The method of claim 1, And the decoding unit comprises a CSA comprising a plurality of full adders and half adders to calculate the number of 1s or the complement of the coded serial data. delete

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